x86/kernel/tsc_msr.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * TSC frequency enumeration via MSR
0004  *
0005  * Copyright (C) 2013, 2018 Intel Corporation
0006  * Author: Bin Gao <bin.gao@intel.com>
0007  */
0008
0009 #include <linux/kernel.h>
0010 #include <linux/thread_info.h>
0011
0012 #include <asm/apic.h>
0013 #include <asm/cpu_device_id.h>
0014 #include <asm/intel-family.h>
0015 #include <asm/msr.h>
0016 #include <asm/param.h>
0017 #include <asm/tsc.h>
0018
0019 #define MAX_NUM_FREQS   16 /* 4 bits to select the frequency */
0020
0021 /*
0022  * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a
0023  * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs
0024  * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal
0025  * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is
0026  * unclear if the root PLL outputs are used directly by the CPU clock PLL or
0027  * if there is another PLL in between.
0028  * This does not matter though, we can model the chain of PLLs as a single PLL
0029  * with a quotient equal to the quotients of all PLLs in the chain multiplied.
0030  * So we can create a simplified model of the CPU clock setup using a reference
0031  * clock of 100 MHz plus a quotient which gets us as close to the frequency
0032  * from the SDM as possible.
0033  * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 =
0034  * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw.
0035  */
0036 #define TSC_REFERENCE_KHZ 100000
0037
0038 struct muldiv {
0039     u32 multiplier;
0040     u32 divider;
0041 };
0042
0043 /*
0044  * If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
0045  * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
0046  * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
0047  * so we need manually differentiate SoC families. This is what the
0048  * field use_msr_plat does.
0049  */
0050 struct freq_desc {
0051     bool use_msr_plat;
0052     struct muldiv muldiv[MAX_NUM_FREQS];
0053     /*
0054      * Some CPU frequencies in the SDM do not map to known PLL freqs, in
0055      * that case the muldiv array is empty and the freqs array is used.
0056      */
0057     u32 freqs[MAX_NUM_FREQS];
0058     u32 mask;
0059 };
0060
0061 /*
0062  * Penwell and Clovertrail use spread spectrum clock,
0063  * so the freq number is not exactly the same as reported
0064  * by MSR based on SDM.
0065  */
0066 static const struct freq_desc freq_desc_pnw = {
0067     .use_msr_plat = false,
0068     .freqs = { 0, 0, 0, 0, 0, 99840, 0, 83200 },
0069     .mask = 0x07,
0070 };
0071
0072 static const struct freq_desc freq_desc_clv = {
0073     .use_msr_plat = false,
0074     .freqs = { 0, 133200, 0, 0, 0, 99840, 0, 83200 },
0075     .mask = 0x07,
0076 };
0077
0078 /*
0079  * Bay Trail SDM MSR_FSB_FREQ frequencies simplified PLL model:
0080  *  000:   100 *  5 /  6  =  83.3333 MHz
0081  *  001:   100 *  1 /  1  = 100.0000 MHz
0082  *  010:   100 *  4 /  3  = 133.3333 MHz
0083  *  011:   100 *  7 /  6  = 116.6667 MHz
0084  *  100:   100 *  4 /  5  =  80.0000 MHz
0085  */
0086 static const struct freq_desc freq_desc_byt = {
0087     .use_msr_plat = true,
0088     .muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 7, 6 },
0089             { 4, 5 } },
0090     .mask = 0x07,
0091 };
0092
0093 /*
0094  * Cherry Trail SDM MSR_FSB_FREQ frequencies simplified PLL model:
0095  * 0000:   100 *  5 /  6  =  83.3333 MHz
0096  * 0001:   100 *  1 /  1  = 100.0000 MHz
0097  * 0010:   100 *  4 /  3  = 133.3333 MHz
0098  * 0011:   100 *  7 /  6  = 116.6667 MHz
0099  * 0100:   100 *  4 /  5  =  80.0000 MHz
0100  * 0101:   100 * 14 / 15  =  93.3333 MHz
0101  * 0110:   100 *  9 / 10  =  90.0000 MHz
0102  * 0111:   100 *  8 /  9  =  88.8889 MHz
0103  * 1000:   100 *  7 /  8  =  87.5000 MHz
0104  */
0105 static const struct freq_desc freq_desc_cht = {
0106     .use_msr_plat = true,
0107     .muldiv = { { 5, 6 }, {  1,  1 }, { 4,  3 }, { 7, 6 },
0108             { 4, 5 }, { 14, 15 }, { 9, 10 }, { 8, 9 },
0109             { 7, 8 } },
0110     .mask = 0x0f,
0111 };
0112
0113 /*
0114  * Merriefield SDM MSR_FSB_FREQ frequencies simplified PLL model:
0115  * 0001:   100 *  1 /  1  = 100.0000 MHz
0116  * 0010:   100 *  4 /  3  = 133.3333 MHz
0117  */
0118 static const struct freq_desc freq_desc_tng = {
0119     .use_msr_plat = true,
0120     .muldiv = { { 0, 0 }, { 1, 1 }, { 4, 3 } },
0121     .mask = 0x07,
0122 };
0123
0124 /*
0125  * Moorefield SDM MSR_FSB_FREQ frequencies simplified PLL model:
0126  * 0000:   100 *  5 /  6  =  83.3333 MHz
0127  * 0001:   100 *  1 /  1  = 100.0000 MHz
0128  * 0010:   100 *  4 /  3  = 133.3333 MHz
0129  * 0011:   100 *  1 /  1  = 100.0000 MHz
0130  */
0131 static const struct freq_desc freq_desc_ann = {
0132     .use_msr_plat = true,
0133     .muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 1, 1 } },
0134     .mask = 0x0f,
0135 };
0136
0137 /*
0138  * 24 MHz crystal? : 24 * 13 / 4 = 78 MHz
0139  * Frequency step for Lightning Mountain SoC is fixed to 78 MHz,
0140  * so all the frequency entries are 78000.
0141  */
0142 static const struct freq_desc freq_desc_lgm = {
0143     .use_msr_plat = true,
0144     .freqs = { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000,
0145            78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 },
0146     .mask = 0x0f,
0147 };
0148
0149 static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
0150     X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID,   &freq_desc_pnw),
0151     X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_TABLET,&freq_desc_clv),
0152     X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &freq_desc_byt),
0153     X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &freq_desc_tng),
0154     X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT,    &freq_desc_cht),
0155     X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_MID,    &freq_desc_ann),
0156     X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_NP, &freq_desc_lgm),
0157     {}
0158 };
0159
0160 /*
0161  * MSR-based CPU/TSC frequency discovery for certain CPUs.
0162  *
0163  * Set global "lapic_timer_period" to bus_clock_cycles/jiffy
0164  * Return processor base frequency in KHz, or 0 on failure.
0165  */
0166 unsigned long cpu_khz_from_msr(void)
0167 {
0168     u32 lo, hi, ratio, freq, tscref;
0169     const struct freq_desc *freq_desc;
0170     const struct x86_cpu_id *id;
0171     const struct muldiv *md;
0172     unsigned long res;
0173     int index;
0174
0175     id = x86_match_cpu(tsc_msr_cpu_ids);
0176     if (!id)
0177         return 0;
0178
0179     freq_desc = (struct freq_desc *)id->driver_data;
0180     if (freq_desc->use_msr_plat) {
0181         rdmsr(MSR_PLATFORM_INFO, lo, hi);
0182         ratio = (lo >> 8) & 0xff;
0183     } else {
0184         rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
0185         ratio = (hi >> 8) & 0x1f;
0186     }
0187
0188     /* Get FSB FREQ ID */
0189     rdmsr(MSR_FSB_FREQ, lo, hi);
0190     index = lo & freq_desc->mask;
0191     md = &freq_desc->muldiv[index];
0192
0193     /*
0194      * Note this also catches cases where the index points to an unpopulated
0195      * part of muldiv, in that case the else will set freq and res to 0.
0196      */
0197     if (md->divider) {
0198         tscref = TSC_REFERENCE_KHZ * md->multiplier;
0199         freq = DIV_ROUND_CLOSEST(tscref, md->divider);
0200         /*
0201          * Multiplying by ratio before the division has better
0202          * accuracy than just calculating freq * ratio.
0203          */
0204         res = DIV_ROUND_CLOSEST(tscref * ratio, md->divider);
0205     } else {
0206         freq = freq_desc->freqs[index];
0207         res = freq * ratio;
0208     }
0209
0210     if (freq == 0)
0211         pr_err("Error MSR_FSB_FREQ index %d is unknown\n", index);
0212
0213 #ifdef CONFIG_X86_LOCAL_APIC
0214     lapic_timer_period = (freq * 1000) / HZ;
0215 #endif
0216
0217     /*
0218      * TSC frequency determined by MSR is always considered "known"
0219      * because it is reported by HW.
0220      * Another fact is that on MSR capable platforms, PIT/HPET is
0221      * generally not available so calibration won't work at all.
0222      */
0223     setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
0224
0225     /*
0226      * Unfortunately there is no way for hardware to tell whether the
0227      * TSC is reliable.  We were told by silicon design team that TSC
0228      * on Atom SoCs are always "reliable". TSC is also the only
0229      * reliable clocksource on these SoCs (HPET is either not present
0230      * or not functional) so mark TSC reliable which removes the
0231      * requirement for a watchdog clocksource.
0232      */
0233     setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
0234
0235     return res;
0236 }