x86/kernel/smp.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Intel SMP support routines.
0004  *
0005  *  (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
0006  *  (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com>
0007  *      (c) 2002,2003 Andi Kleen, SuSE Labs.
0008  *
0009  *  i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com>
0010  */
0011
0012 #include <linux/init.h>
0013
0014 #include <linux/mm.h>
0015 #include <linux/delay.h>
0016 #include <linux/spinlock.h>
0017 #include <linux/export.h>
0018 #include <linux/kernel_stat.h>
0019 #include <linux/mc146818rtc.h>
0020 #include <linux/cache.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/cpu.h>
0023 #include <linux/gfp.h>
0024
0025 #include <asm/mtrr.h>
0026 #include <asm/tlbflush.h>
0027 #include <asm/mmu_context.h>
0028 #include <asm/proto.h>
0029 #include <asm/apic.h>
0030 #include <asm/idtentry.h>
0031 #include <asm/nmi.h>
0032 #include <asm/mce.h>
0033 #include <asm/trace/irq_vectors.h>
0034 #include <asm/kexec.h>
0035 #include <asm/virtext.h>
0036
0037 /*
0038  *  Some notes on x86 processor bugs affecting SMP operation:
0039  *
0040  *  Pentium, Pentium Pro, II, III (and all CPUs) have bugs.
0041  *  The Linux implications for SMP are handled as follows:
0042  *
0043  *  Pentium III / [Xeon]
0044  *      None of the E1AP-E3AP errata are visible to the user.
0045  *
0046  *  E1AP.   see PII A1AP
0047  *  E2AP.   see PII A2AP
0048  *  E3AP.   see PII A3AP
0049  *
0050  *  Pentium II / [Xeon]
0051  *      None of the A1AP-A3AP errata are visible to the user.
0052  *
0053  *  A1AP.   see PPro 1AP
0054  *  A2AP.   see PPro 2AP
0055  *  A3AP.   see PPro 7AP
0056  *
0057  *  Pentium Pro
0058  *      None of 1AP-9AP errata are visible to the normal user,
0059  *  except occasional delivery of 'spurious interrupt' as trap #15.
0060  *  This is very rare and a non-problem.
0061  *
0062  *  1AP.    Linux maps APIC as non-cacheable
0063  *  2AP.    worked around in hardware
0064  *  3AP.    fixed in C0 and above steppings microcode update.
0065  *      Linux does not use excessive STARTUP_IPIs.
0066  *  4AP.    worked around in hardware
0067  *  5AP.    symmetric IO mode (normal Linux operation) not affected.
0068  *      'noapic' mode has vector 0xf filled out properly.
0069  *  6AP.    'noapic' mode might be affected - fixed in later steppings
0070  *  7AP.    We do not assume writes to the LVT deasserting IRQs
0071  *  8AP.    We do not enable low power mode (deep sleep) during MP bootup
0072  *  9AP.    We do not use mixed mode
0073  *
0074  *  Pentium
0075  *      There is a marginal case where REP MOVS on 100MHz SMP
0076  *  machines with B stepping processors can fail. XXX should provide
0077  *  an L1cache=Writethrough or L1cache=off option.
0078  *
0079  *      B stepping CPUs may hang. There are hardware work arounds
0080  *  for this. We warn about it in case your board doesn't have the work
0081  *  arounds. Basically that's so I can tell anyone with a B stepping
0082  *  CPU and SMP problems "tough".
0083  *
0084  *  Specific items [From Pentium Processor Specification Update]
0085  *
0086  *  1AP.    Linux doesn't use remote read
0087  *  2AP.    Linux doesn't trust APIC errors
0088  *  3AP.    We work around this
0089  *  4AP.    Linux never generated 3 interrupts of the same priority
0090  *      to cause a lost local interrupt.
0091  *  5AP.    Remote read is never used
0092  *  6AP.    not affected - worked around in hardware
0093  *  7AP.    not affected - worked around in hardware
0094  *  8AP.    worked around in hardware - we get explicit CS errors if not
0095  *  9AP.    only 'noapic' mode affected. Might generate spurious
0096  *      interrupts, we log only the first one and count the
0097  *      rest silently.
0098  *  10AP.   not affected - worked around in hardware
0099  *  11AP.   Linux reads the APIC between writes to avoid this, as per
0100  *      the documentation. Make sure you preserve this as it affects
0101  *      the C stepping chips too.
0102  *  12AP.   not affected - worked around in hardware
0103  *  13AP.   not affected - worked around in hardware
0104  *  14AP.   we always deassert INIT during bootup
0105  *  15AP.   not affected - worked around in hardware
0106  *  16AP.   not affected - worked around in hardware
0107  *  17AP.   not affected - worked around in hardware
0108  *  18AP.   not affected - worked around in hardware
0109  *  19AP.   not affected - worked around in BIOS
0110  *
0111  *  If this sounds worrying believe me these bugs are either ___RARE___,
0112  *  or are signal timing bugs worked around in hardware and there's
0113  *  about nothing of note with C stepping upwards.
0114  */
0115
0116 static atomic_t stopping_cpu = ATOMIC_INIT(-1);
0117 static bool smp_no_nmi_ipi = false;
0118
0119 static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs)
0120 {
0121     /* We are registered on stopping cpu too, avoid spurious NMI */
0122     if (raw_smp_processor_id() == atomic_read(&stopping_cpu))
0123         return NMI_HANDLED;
0124
0125     cpu_emergency_vmxoff();
0126     stop_this_cpu(NULL);
0127
0128     return NMI_HANDLED;
0129 }
0130
0131 /*
0132  * this function calls the 'stop' function on all other CPUs in the system.
0133  */
0134 DEFINE_IDTENTRY_SYSVEC(sysvec_reboot)
0135 {
0136     ack_APIC_irq();
0137     cpu_emergency_vmxoff();
0138     stop_this_cpu(NULL);
0139 }
0140
0141 static int register_stop_handler(void)
0142 {
0143     return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback,
0144                     NMI_FLAG_FIRST, "smp_stop");
0145 }
0146
0147 static void native_stop_other_cpus(int wait)
0148 {
0149     unsigned long flags;
0150     unsigned long timeout;
0151
0152     if (reboot_force)
0153         return;
0154
0155     /*
0156      * Use an own vector here because smp_call_function
0157      * does lots of things not suitable in a panic situation.
0158      */
0159
0160     /*
0161      * We start by using the REBOOT_VECTOR irq.
0162      * The irq is treated as a sync point to allow critical
0163      * regions of code on other cpus to release their spin locks
0164      * and re-enable irqs.  Jumping straight to an NMI might
0165      * accidentally cause deadlocks with further shutdown/panic
0166      * code.  By syncing, we give the cpus up to one second to
0167      * finish their work before we force them off with the NMI.
0168      */
0169     if (num_online_cpus() > 1) {
0170         /* did someone beat us here? */
0171         if (atomic_cmpxchg(&stopping_cpu, -1, safe_smp_processor_id()) != -1)
0172             return;
0173
0174         /* sync above data before sending IRQ */
0175         wmb();
0176
0177         apic_send_IPI_allbutself(REBOOT_VECTOR);
0178
0179         /*
0180          * Don't wait longer than a second for IPI completion. The
0181          * wait request is not checked here because that would
0182          * prevent an NMI shutdown attempt in case that not all
0183          * CPUs reach shutdown state.
0184          */
0185         timeout = USEC_PER_SEC;
0186         while (num_online_cpus() > 1 && timeout--)
0187             udelay(1);
0188     }
0189
0190     /* if the REBOOT_VECTOR didn't work, try with the NMI */
0191     if (num_online_cpus() > 1) {
0192         /*
0193          * If NMI IPI is enabled, try to register the stop handler
0194          * and send the IPI. In any case try to wait for the other
0195          * CPUs to stop.
0196          */
0197         if (!smp_no_nmi_ipi && !register_stop_handler()) {
0198             /* Sync above data before sending IRQ */
0199             wmb();
0200
0201             pr_emerg("Shutting down cpus with NMI\n");
0202
0203             apic_send_IPI_allbutself(NMI_VECTOR);
0204         }
0205         /*
0206          * Don't wait longer than 10 ms if the caller didn't
0207          * request it. If wait is true, the machine hangs here if
0208          * one or more CPUs do not reach shutdown state.
0209          */
0210         timeout = USEC_PER_MSEC * 10;
0211         while (num_online_cpus() > 1 && (wait || timeout--))
0212             udelay(1);
0213     }
0214
0215     local_irq_save(flags);
0216     disable_local_APIC();
0217     mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
0218     local_irq_restore(flags);
0219 }
0220
0221 /*
0222  * Reschedule call back. KVM uses this interrupt to force a cpu out of
0223  * guest mode.
0224  */
0225 DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_reschedule_ipi)
0226 {
0227     ack_APIC_irq();
0228     trace_reschedule_entry(RESCHEDULE_VECTOR);
0229     inc_irq_stat(irq_resched_count);
0230     scheduler_ipi();
0231     trace_reschedule_exit(RESCHEDULE_VECTOR);
0232 }
0233
0234 DEFINE_IDTENTRY_SYSVEC(sysvec_call_function)
0235 {
0236     ack_APIC_irq();
0237     trace_call_function_entry(CALL_FUNCTION_VECTOR);
0238     inc_irq_stat(irq_call_count);
0239     generic_smp_call_function_interrupt();
0240     trace_call_function_exit(CALL_FUNCTION_VECTOR);
0241 }
0242
0243 DEFINE_IDTENTRY_SYSVEC(sysvec_call_function_single)
0244 {
0245     ack_APIC_irq();
0246     trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR);
0247     inc_irq_stat(irq_call_count);
0248     generic_smp_call_function_single_interrupt();
0249     trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR);
0250 }
0251
0252 static int __init nonmi_ipi_setup(char *str)
0253 {
0254     smp_no_nmi_ipi = true;
0255     return 1;
0256 }
0257
0258 __setup("nonmi_ipi", nonmi_ipi_setup);
0259
0260 struct smp_ops smp_ops = {
0261     .smp_prepare_boot_cpu   = native_smp_prepare_boot_cpu,
0262     .smp_prepare_cpus   = native_smp_prepare_cpus,
0263     .smp_cpus_done      = native_smp_cpus_done,
0264
0265     .stop_other_cpus    = native_stop_other_cpus,
0266 #if defined(CONFIG_KEXEC_CORE)
0267     .crash_stop_other_cpus  = kdump_nmi_shootdown_cpus,
0268 #endif
0269     .smp_send_reschedule    = native_smp_send_reschedule,
0270
0271     .cpu_up         = native_cpu_up,
0272     .cpu_die        = native_cpu_die,
0273     .cpu_disable        = native_cpu_disable,
0274     .play_dead      = native_play_dead,
0275
0276     .send_call_func_ipi = native_send_call_func_ipi,
0277     .send_call_func_single_ipi = native_send_call_func_single_ipi,
0278 };
0279 EXPORT_SYMBOL_GPL(smp_ops);