x86/kernel/mmconf-fam10h_64.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * AMD Family 10h mmconfig enablement
0004  */
0005
0006 #include <linux/types.h>
0007 #include <linux/mm.h>
0008 #include <linux/string.h>
0009 #include <linux/pci.h>
0010 #include <linux/dmi.h>
0011 #include <linux/range.h>
0012
0013 #include <asm/pci-direct.h>
0014 #include <linux/sort.h>
0015 #include <asm/io.h>
0016 #include <asm/msr.h>
0017 #include <asm/acpi.h>
0018 #include <asm/mmconfig.h>
0019 #include <asm/pci_x86.h>
0020
0021 struct pci_hostbridge_probe {
0022     u32 bus;
0023     u32 slot;
0024     u32 vendor;
0025     u32 device;
0026 };
0027
0028 static u64 fam10h_pci_mmconf_base;
0029
0030 static struct pci_hostbridge_probe pci_probes[] = {
0031     { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
0032     { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
0033 };
0034
0035 static int cmp_range(const void *x1, const void *x2)
0036 {
0037     const struct range *r1 = x1;
0038     const struct range *r2 = x2;
0039     int start1, start2;
0040
0041     start1 = r1->start >> 32;
0042     start2 = r2->start >> 32;
0043
0044     return start1 - start2;
0045 }
0046
0047 #define MMCONF_UNIT (1ULL << FAM10H_MMIO_CONF_BASE_SHIFT)
0048 #define MMCONF_MASK (~(MMCONF_UNIT - 1))
0049 #define MMCONF_SIZE (MMCONF_UNIT << 8)
0050 /* need to avoid (0xfd<<32), (0xfe<<32), and (0xff<<32), ht used space */
0051 #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
0052 #define BASE_VALID(b) ((b) + MMCONF_SIZE <= (0xfdULL<<32) || (b) >= (1ULL<<40))
0053 static void get_fam10h_pci_mmconf_base(void)
0054 {
0055     int i;
0056     unsigned bus;
0057     unsigned slot;
0058     int found;
0059
0060     u64 val;
0061     u32 address;
0062     u64 tom2;
0063     u64 base = FAM10H_PCI_MMCONF_BASE;
0064
0065     int hi_mmio_num;
0066     struct range range[8];
0067
0068     /* only try to get setting from BSP */
0069     if (fam10h_pci_mmconf_base)
0070         return;
0071
0072     if (!early_pci_allowed())
0073         return;
0074
0075     found = 0;
0076     for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
0077         u32 id;
0078         u16 device;
0079         u16 vendor;
0080
0081         bus = pci_probes[i].bus;
0082         slot = pci_probes[i].slot;
0083         id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
0084
0085         vendor = id & 0xffff;
0086         device = (id>>16) & 0xffff;
0087         if (pci_probes[i].vendor == vendor &&
0088             pci_probes[i].device == device) {
0089             found = 1;
0090             break;
0091         }
0092     }
0093
0094     if (!found)
0095         return;
0096
0097     /* SYS_CFG */
0098     address = MSR_AMD64_SYSCFG;
0099     rdmsrl(address, val);
0100
0101     /* TOP_MEM2 is not enabled? */
0102     if (!(val & (1<<21))) {
0103         tom2 = 1ULL << 32;
0104     } else {
0105         /* TOP_MEM2 */
0106         address = MSR_K8_TOP_MEM2;
0107         rdmsrl(address, val);
0108         tom2 = max(val & 0xffffff800000ULL, 1ULL << 32);
0109     }
0110
0111     if (base <= tom2)
0112         base = (tom2 + 2 * MMCONF_UNIT - 1) & MMCONF_MASK;
0113
0114     /*
0115      * need to check if the range is in the high mmio range that is
0116      * above 4G
0117      */
0118     hi_mmio_num = 0;
0119     for (i = 0; i < 8; i++) {
0120         u32 reg;
0121         u64 start;
0122         u64 end;
0123         reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
0124         if (!(reg & 3))
0125             continue;
0126
0127         start = (u64)(reg & 0xffffff00) << 8; /* 39:16 on 31:8*/
0128         reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
0129         end = ((u64)(reg & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/
0130
0131         if (end < tom2)
0132             continue;
0133
0134         range[hi_mmio_num].start = start;
0135         range[hi_mmio_num].end = end;
0136         hi_mmio_num++;
0137     }
0138
0139     if (!hi_mmio_num)
0140         goto out;
0141
0142     /* sort the range */
0143     sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
0144
0145     if (range[hi_mmio_num - 1].end < base)
0146         goto out;
0147     if (range[0].start > base + MMCONF_SIZE)
0148         goto out;
0149
0150     /* need to find one window */
0151     base = (range[0].start & MMCONF_MASK) - MMCONF_UNIT;
0152     if ((base > tom2) && BASE_VALID(base))
0153         goto out;
0154     base = (range[hi_mmio_num - 1].end + MMCONF_UNIT) & MMCONF_MASK;
0155     if (BASE_VALID(base))
0156         goto out;
0157     /* need to find window between ranges */
0158     for (i = 1; i < hi_mmio_num; i++) {
0159         base = (range[i - 1].end + MMCONF_UNIT) & MMCONF_MASK;
0160         val = range[i].start & MMCONF_MASK;
0161         if (val >= base + MMCONF_SIZE && BASE_VALID(base))
0162             goto out;
0163     }
0164     return;
0165
0166 out:
0167     fam10h_pci_mmconf_base = base;
0168 }
0169
0170 void fam10h_check_enable_mmcfg(void)
0171 {
0172     u64 val;
0173     u32 address;
0174
0175     if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
0176         return;
0177
0178     address = MSR_FAM10H_MMIO_CONF_BASE;
0179     rdmsrl(address, val);
0180
0181     /* try to make sure that AP's setting is identical to BSP setting */
0182     if (val & FAM10H_MMIO_CONF_ENABLE) {
0183         unsigned busnbits;
0184         busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
0185             FAM10H_MMIO_CONF_BUSRANGE_MASK;
0186
0187         /* only trust the one handle 256 buses, if acpi=off */
0188         if (!acpi_pci_disabled || busnbits >= 8) {
0189             u64 base = val & MMCONF_MASK;
0190
0191             if (!fam10h_pci_mmconf_base) {
0192                 fam10h_pci_mmconf_base = base;
0193                 return;
0194             } else if (fam10h_pci_mmconf_base ==  base)
0195                 return;
0196         }
0197     }
0198
0199     /*
0200      * if it is not enabled, try to enable it and assume only one segment
0201      * with 256 buses
0202      */
0203     get_fam10h_pci_mmconf_base();
0204     if (!fam10h_pci_mmconf_base) {
0205         pci_probe &= ~PCI_CHECK_ENABLE_AMD_MMCONF;
0206         return;
0207     }
0208
0209     printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
0210     val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
0211          (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
0212     val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
0213            FAM10H_MMIO_CONF_ENABLE;
0214     wrmsrl(address, val);
0215 }
0216
0217 static int __init set_check_enable_amd_mmconf(const struct dmi_system_id *d)
0218 {
0219         pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
0220         return 0;
0221 }
0222
0223 static const struct dmi_system_id __initconst mmconf_dmi_table[] = {
0224         {
0225                 .callback = set_check_enable_amd_mmconf,
0226                 .ident = "Sun Microsystems Machine",
0227                 .matches = {
0228                         DMI_MATCH(DMI_SYS_VENDOR, "Sun Microsystems"),
0229                 },
0230         },
0231     {}
0232 };
0233
0234 /* Called from a non __init function, but only on the BSP. */
0235 void __ref check_enable_amd_mmconf_dmi(void)
0236 {
0237     dmi_check_system(mmconf_dmi_table);
0238 }