x86/kernel/irqinit.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/linkage.h>
0003 #include <linux/errno.h>
0004 #include <linux/signal.h>
0005 #include <linux/sched.h>
0006 #include <linux/ioport.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/irq.h>
0009 #include <linux/timex.h>
0010 #include <linux/random.h>
0011 #include <linux/kprobes.h>
0012 #include <linux/init.h>
0013 #include <linux/kernel_stat.h>
0014 #include <linux/device.h>
0015 #include <linux/bitops.h>
0016 #include <linux/acpi.h>
0017 #include <linux/io.h>
0018 #include <linux/delay.h>
0019 #include <linux/pgtable.h>
0020
0021 #include <linux/atomic.h>
0022 #include <asm/timer.h>
0023 #include <asm/hw_irq.h>
0024 #include <asm/desc.h>
0025 #include <asm/io_apic.h>
0026 #include <asm/acpi.h>
0027 #include <asm/apic.h>
0028 #include <asm/setup.h>
0029 #include <asm/i8259.h>
0030 #include <asm/traps.h>
0031 #include <asm/prom.h>
0032
0033 /*
0034  * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
0035  * (these are usually mapped to vectors 0x30-0x3f)
0036  */
0037
0038 /*
0039  * The IO-APIC gives us many more interrupt sources. Most of these
0040  * are unused but an SMP system is supposed to have enough memory ...
0041  * sometimes (mostly wrt. hw bugs) we get corrupted vectors all
0042  * across the spectrum, so we really want to be prepared to get all
0043  * of these. Plus, more powerful systems might have more than 64
0044  * IO-APIC registers.
0045  *
0046  * (these are usually mapped into the 0x30-0xff vector range)
0047  */
0048
0049 DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
0050     [0 ... NR_VECTORS - 1] = VECTOR_UNUSED,
0051 };
0052
0053 void __init init_ISA_irqs(void)
0054 {
0055     struct irq_chip *chip = legacy_pic->chip;
0056     int i;
0057
0058     /*
0059      * Try to set up the through-local-APIC virtual wire mode earlier.
0060      *
0061      * On some 32-bit UP machines, whose APIC has been disabled by BIOS
0062      * and then got re-enabled by "lapic", it hangs at boot time without this.
0063      */
0064     init_bsp_APIC();
0065
0066     legacy_pic->init(0);
0067
0068     for (i = 0; i < nr_legacy_irqs(); i++)
0069         irq_set_chip_and_handler(i, chip, handle_level_irq);
0070 }
0071
0072 void __init init_IRQ(void)
0073 {
0074     int i;
0075
0076     /*
0077      * On cpu 0, Assign ISA_IRQ_VECTOR(irq) to IRQ 0..15.
0078      * If these IRQ's are handled by legacy interrupt-controllers like PIC,
0079      * then this configuration will likely be static after the boot. If
0080      * these IRQs are handled by more modern controllers like IO-APIC,
0081      * then this vector space can be freed and re-used dynamically as the
0082      * irq's migrate etc.
0083      */
0084     for (i = 0; i < nr_legacy_irqs(); i++)
0085         per_cpu(vector_irq, 0)[ISA_IRQ_VECTOR(i)] = irq_to_desc(i);
0086
0087     BUG_ON(irq_init_percpu_irqstack(smp_processor_id()));
0088
0089     x86_init.irqs.intr_init();
0090 }
0091
0092 void __init native_init_IRQ(void)
0093 {
0094     /* Execute any quirks before the call gates are initialised: */
0095     x86_init.irqs.pre_vector_init();
0096
0097     idt_setup_apic_and_irq_gates();
0098     lapic_assign_system_vectors();
0099
0100     if (!acpi_ioapic && !of_ioapic && nr_legacy_irqs()) {
0101         /* IRQ2 is cascade interrupt to second interrupt controller */
0102         if (request_irq(2, no_action, IRQF_NO_THREAD, "cascade", NULL))
0103             pr_err("%s: request_irq() failed\n", "cascade");
0104     }
0105 }