x86/kernel/idt.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Interrupt descriptor table related code
0004  */
0005 #include <linux/interrupt.h>
0006
0007 #include <asm/cpu_entry_area.h>
0008 #include <asm/set_memory.h>
0009 #include <asm/traps.h>
0010 #include <asm/proto.h>
0011 #include <asm/desc.h>
0012 #include <asm/hw_irq.h>
0013 #include <asm/idtentry.h>
0014
0015 #define DPL0        0x0
0016 #define DPL3        0x3
0017
0018 #define DEFAULT_STACK   0
0019
0020 #define G(_vector, _addr, _ist, _type, _dpl, _segment)  \
0021     {                       \
0022         .vector     = _vector,      \
0023         .bits.ist   = _ist,         \
0024         .bits.type  = _type,        \
0025         .bits.dpl   = _dpl,         \
0026         .bits.p     = 1,            \
0027         .addr       = _addr,        \
0028         .segment    = _segment,     \
0029     }
0030
0031 /* Interrupt gate */
0032 #define INTG(_vector, _addr)                \
0033     G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
0034
0035 /* System interrupt gate */
0036 #define SYSG(_vector, _addr)                \
0037     G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
0038
0039 #ifdef CONFIG_X86_64
0040 /*
0041  * Interrupt gate with interrupt stack. The _ist index is the index in
0042  * the tss.ist[] array, but for the descriptor it needs to start at 1.
0043  */
0044 #define ISTG(_vector, _addr, _ist)          \
0045     G(_vector, _addr, _ist + 1, GATE_INTERRUPT, DPL0, __KERNEL_CS)
0046 #else
0047 #define ISTG(_vector, _addr, _ist)  INTG(_vector, _addr)
0048 #endif
0049
0050 /* Task gate */
0051 #define TSKG(_vector, _gdt)             \
0052     G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
0053
0054 #define IDT_TABLE_SIZE      (IDT_ENTRIES * sizeof(gate_desc))
0055
0056 static bool idt_setup_done __initdata;
0057
0058 /*
0059  * Early traps running on the DEFAULT_STACK because the other interrupt
0060  * stacks work only after cpu_init().
0061  */
0062 static const __initconst struct idt_data early_idts[] = {
0063     INTG(X86_TRAP_DB,       asm_exc_debug),
0064     SYSG(X86_TRAP_BP,       asm_exc_int3),
0065
0066 #ifdef CONFIG_X86_32
0067     /*
0068      * Not possible on 64-bit. See idt_setup_early_pf() for details.
0069      */
0070     INTG(X86_TRAP_PF,       asm_exc_page_fault),
0071 #endif
0072 #ifdef CONFIG_INTEL_TDX_GUEST
0073     INTG(X86_TRAP_VE,       asm_exc_virtualization_exception),
0074 #endif
0075 };
0076
0077 /*
0078  * The default IDT entries which are set up in trap_init() before
0079  * cpu_init() is invoked. Interrupt stacks cannot be used at that point and
0080  * the traps which use them are reinitialized with IST after cpu_init() has
0081  * set up TSS.
0082  */
0083 static const __initconst struct idt_data def_idts[] = {
0084     INTG(X86_TRAP_DE,       asm_exc_divide_error),
0085     ISTG(X86_TRAP_NMI,      asm_exc_nmi, IST_INDEX_NMI),
0086     INTG(X86_TRAP_BR,       asm_exc_bounds),
0087     INTG(X86_TRAP_UD,       asm_exc_invalid_op),
0088     INTG(X86_TRAP_NM,       asm_exc_device_not_available),
0089     INTG(X86_TRAP_OLD_MF,       asm_exc_coproc_segment_overrun),
0090     INTG(X86_TRAP_TS,       asm_exc_invalid_tss),
0091     INTG(X86_TRAP_NP,       asm_exc_segment_not_present),
0092     INTG(X86_TRAP_SS,       asm_exc_stack_segment),
0093     INTG(X86_TRAP_GP,       asm_exc_general_protection),
0094     INTG(X86_TRAP_SPURIOUS,     asm_exc_spurious_interrupt_bug),
0095     INTG(X86_TRAP_MF,       asm_exc_coprocessor_error),
0096     INTG(X86_TRAP_AC,       asm_exc_alignment_check),
0097     INTG(X86_TRAP_XF,       asm_exc_simd_coprocessor_error),
0098
0099 #ifdef CONFIG_X86_32
0100     TSKG(X86_TRAP_DF,       GDT_ENTRY_DOUBLEFAULT_TSS),
0101 #else
0102     ISTG(X86_TRAP_DF,       asm_exc_double_fault, IST_INDEX_DF),
0103 #endif
0104     ISTG(X86_TRAP_DB,       asm_exc_debug, IST_INDEX_DB),
0105
0106 #ifdef CONFIG_X86_MCE
0107     ISTG(X86_TRAP_MC,       asm_exc_machine_check, IST_INDEX_MCE),
0108 #endif
0109
0110 #ifdef CONFIG_X86_KERNEL_IBT
0111     INTG(X86_TRAP_CP,       asm_exc_control_protection),
0112 #endif
0113
0114 #ifdef CONFIG_AMD_MEM_ENCRYPT
0115     ISTG(X86_TRAP_VC,       asm_exc_vmm_communication, IST_INDEX_VC),
0116 #endif
0117
0118     SYSG(X86_TRAP_OF,       asm_exc_overflow),
0119 #if defined(CONFIG_IA32_EMULATION)
0120     SYSG(IA32_SYSCALL_VECTOR,   entry_INT80_compat),
0121 #elif defined(CONFIG_X86_32)
0122     SYSG(IA32_SYSCALL_VECTOR,   entry_INT80_32),
0123 #endif
0124 };
0125
0126 /*
0127  * The APIC and SMP idt entries
0128  */
0129 static const __initconst struct idt_data apic_idts[] = {
0130 #ifdef CONFIG_SMP
0131     INTG(RESCHEDULE_VECTOR,         asm_sysvec_reschedule_ipi),
0132     INTG(CALL_FUNCTION_VECTOR,      asm_sysvec_call_function),
0133     INTG(CALL_FUNCTION_SINGLE_VECTOR,   asm_sysvec_call_function_single),
0134     INTG(IRQ_MOVE_CLEANUP_VECTOR,       asm_sysvec_irq_move_cleanup),
0135     INTG(REBOOT_VECTOR,         asm_sysvec_reboot),
0136 #endif
0137
0138 #ifdef CONFIG_X86_THERMAL_VECTOR
0139     INTG(THERMAL_APIC_VECTOR,       asm_sysvec_thermal),
0140 #endif
0141
0142 #ifdef CONFIG_X86_MCE_THRESHOLD
0143     INTG(THRESHOLD_APIC_VECTOR,     asm_sysvec_threshold),
0144 #endif
0145
0146 #ifdef CONFIG_X86_MCE_AMD
0147     INTG(DEFERRED_ERROR_VECTOR,     asm_sysvec_deferred_error),
0148 #endif
0149
0150 #ifdef CONFIG_X86_LOCAL_APIC
0151     INTG(LOCAL_TIMER_VECTOR,        asm_sysvec_apic_timer_interrupt),
0152     INTG(X86_PLATFORM_IPI_VECTOR,       asm_sysvec_x86_platform_ipi),
0153 # ifdef CONFIG_HAVE_KVM
0154     INTG(POSTED_INTR_VECTOR,        asm_sysvec_kvm_posted_intr_ipi),
0155     INTG(POSTED_INTR_WAKEUP_VECTOR,     asm_sysvec_kvm_posted_intr_wakeup_ipi),
0156     INTG(POSTED_INTR_NESTED_VECTOR,     asm_sysvec_kvm_posted_intr_nested_ipi),
0157 # endif
0158 # ifdef CONFIG_IRQ_WORK
0159     INTG(IRQ_WORK_VECTOR,           asm_sysvec_irq_work),
0160 # endif
0161     INTG(SPURIOUS_APIC_VECTOR,      asm_sysvec_spurious_apic_interrupt),
0162     INTG(ERROR_APIC_VECTOR,         asm_sysvec_error_interrupt),
0163 #endif
0164 };
0165
0166 /* Must be page-aligned because the real IDT is used in the cpu entry area */
0167 static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;
0168
0169 static struct desc_ptr idt_descr __ro_after_init = {
0170     .size       = IDT_TABLE_SIZE - 1,
0171     .address    = (unsigned long) idt_table,
0172 };
0173
0174 void load_current_idt(void)
0175 {
0176     lockdep_assert_irqs_disabled();
0177     load_idt(&idt_descr);
0178 }
0179
0180 #ifdef CONFIG_X86_F00F_BUG
0181 bool idt_is_f00f_address(unsigned long address)
0182 {
0183     return ((address - idt_descr.address) >> 3) == 6;
0184 }
0185 #endif
0186
0187 static __init void
0188 idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size, bool sys)
0189 {
0190     gate_desc desc;
0191
0192     for (; size > 0; t++, size--) {
0193         idt_init_desc(&desc, t);
0194         write_idt_entry(idt, t->vector, &desc);
0195         if (sys)
0196             set_bit(t->vector, system_vectors);
0197     }
0198 }
0199
0200 static __init void set_intr_gate(unsigned int n, const void *addr)
0201 {
0202     struct idt_data data;
0203
0204     init_idt_data(&data, n, addr);
0205
0206     idt_setup_from_table(idt_table, &data, 1, false);
0207 }
0208
0209 /**
0210  * idt_setup_early_traps - Initialize the idt table with early traps
0211  *
0212  * On X8664 these traps do not use interrupt stacks as they can't work
0213  * before cpu_init() is invoked and sets up TSS. The IST variants are
0214  * installed after that.
0215  */
0216 void __init idt_setup_early_traps(void)
0217 {
0218     idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts),
0219                  true);
0220     load_idt(&idt_descr);
0221 }
0222
0223 /**
0224  * idt_setup_traps - Initialize the idt table with default traps
0225  */
0226 void __init idt_setup_traps(void)
0227 {
0228     idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts), true);
0229 }
0230
0231 #ifdef CONFIG_X86_64
0232 /*
0233  * Early traps running on the DEFAULT_STACK because the other interrupt
0234  * stacks work only after cpu_init().
0235  */
0236 static const __initconst struct idt_data early_pf_idts[] = {
0237     INTG(X86_TRAP_PF,       asm_exc_page_fault),
0238 };
0239
0240 /**
0241  * idt_setup_early_pf - Initialize the idt table with early pagefault handler
0242  *
0243  * On X8664 this does not use interrupt stacks as they can't work before
0244  * cpu_init() is invoked and sets up TSS. The IST variant is installed
0245  * after that.
0246  *
0247  * Note, that X86_64 cannot install the real #PF handler in
0248  * idt_setup_early_traps() because the memory initialization needs the #PF
0249  * handler from the early_idt_handler_array to initialize the early page
0250  * tables.
0251  */
0252 void __init idt_setup_early_pf(void)
0253 {
0254     idt_setup_from_table(idt_table, early_pf_idts,
0255                  ARRAY_SIZE(early_pf_idts), true);
0256 }
0257 #endif
0258
0259 static void __init idt_map_in_cea(void)
0260 {
0261     /*
0262      * Set the IDT descriptor to a fixed read-only location in the cpu
0263      * entry area, so that the "sidt" instruction will not leak the
0264      * location of the kernel, and to defend the IDT against arbitrary
0265      * memory write vulnerabilities.
0266      */
0267     cea_set_pte(CPU_ENTRY_AREA_RO_IDT_VADDR, __pa_symbol(idt_table),
0268             PAGE_KERNEL_RO);
0269     idt_descr.address = CPU_ENTRY_AREA_RO_IDT;
0270 }
0271
0272 /**
0273  * idt_setup_apic_and_irq_gates - Setup APIC/SMP and normal interrupt gates
0274  */
0275 void __init idt_setup_apic_and_irq_gates(void)
0276 {
0277     int i = FIRST_EXTERNAL_VECTOR;
0278     void *entry;
0279
0280     idt_setup_from_table(idt_table, apic_idts, ARRAY_SIZE(apic_idts), true);
0281
0282     for_each_clear_bit_from(i, system_vectors, FIRST_SYSTEM_VECTOR) {
0283         entry = irq_entries_start + IDT_ALIGN * (i - FIRST_EXTERNAL_VECTOR);
0284         set_intr_gate(i, entry);
0285     }
0286
0287 #ifdef CONFIG_X86_LOCAL_APIC
0288     for_each_clear_bit_from(i, system_vectors, NR_VECTORS) {
0289         /*
0290          * Don't set the non assigned system vectors in the
0291          * system_vectors bitmap. Otherwise they show up in
0292          * /proc/interrupts.
0293          */
0294         entry = spurious_entries_start + IDT_ALIGN * (i - FIRST_SYSTEM_VECTOR);
0295         set_intr_gate(i, entry);
0296     }
0297 #endif
0298     /* Map IDT into CPU entry area and reload it. */
0299     idt_map_in_cea();
0300     load_idt(&idt_descr);
0301
0302     /* Make the IDT table read only */
0303     set_memory_ro((unsigned long)&idt_table, 1);
0304
0305     idt_setup_done = true;
0306 }
0307
0308 /**
0309  * idt_setup_early_handler - Initializes the idt table with early handlers
0310  */
0311 void __init idt_setup_early_handler(void)
0312 {
0313     int i;
0314
0315     for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
0316         set_intr_gate(i, early_idt_handler_array[i]);
0317 #ifdef CONFIG_X86_32
0318     for ( ; i < NR_VECTORS; i++)
0319         set_intr_gate(i, early_ignore_irq);
0320 #endif
0321     load_idt(&idt_descr);
0322 }
0323
0324 /**
0325  * idt_invalidate - Invalidate interrupt descriptor table
0326  */
0327 void idt_invalidate(void)
0328 {
0329     static const struct desc_ptr idt = { .address = 0, .size = 0 };
0330
0331     load_idt(&idt);
0332 }
0333
0334 void __init alloc_intr_gate(unsigned int n, const void *addr)
0335 {
0336     if (WARN_ON(n < FIRST_SYSTEM_VECTOR))
0337         return;
0338
0339     if (WARN_ON(idt_setup_done))
0340         return;
0341
0342     if (!WARN_ON(test_and_set_bit(n, system_vectors)))
0343         set_intr_gate(n, addr);
0344 }