Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 #include <linux/clockchips.h>
0003 #include <linux/interrupt.h>
0004 #include <linux/export.h>
0005 #include <linux/delay.h>
0006 #include <linux/hpet.h>
0007 #include <linux/cpu.h>
0008 #include <linux/irq.h>
0009 
0010 #include <asm/irq_remapping.h>
0011 #include <asm/hpet.h>
0012 #include <asm/time.h>
0013 #include <asm/mwait.h>
0014 
0015 #undef  pr_fmt
0016 #define pr_fmt(fmt) "hpet: " fmt
0017 
0018 enum hpet_mode {
0019     HPET_MODE_UNUSED,
0020     HPET_MODE_LEGACY,
0021     HPET_MODE_CLOCKEVT,
0022     HPET_MODE_DEVICE,
0023 };
0024 
0025 struct hpet_channel {
0026     struct clock_event_device   evt;
0027     unsigned int            num;
0028     unsigned int            cpu;
0029     unsigned int            irq;
0030     unsigned int            in_use;
0031     enum hpet_mode          mode;
0032     unsigned int            boot_cfg;
0033     char                name[10];
0034 };
0035 
0036 struct hpet_base {
0037     unsigned int            nr_channels;
0038     unsigned int            nr_clockevents;
0039     unsigned int            boot_cfg;
0040     struct hpet_channel     *channels;
0041 };
0042 
0043 #define HPET_MASK           CLOCKSOURCE_MASK(32)
0044 
0045 #define HPET_MIN_CYCLES         128
0046 #define HPET_MIN_PROG_DELTA     (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
0047 
0048 /*
0049  * HPET address is set in acpi/boot.c, when an ACPI entry exists
0050  */
0051 unsigned long               hpet_address;
0052 u8                  hpet_blockid; /* OS timer block num */
0053 bool                    hpet_msi_disable;
0054 
0055 #ifdef CONFIG_GENERIC_MSI_IRQ
0056 static DEFINE_PER_CPU(struct hpet_channel *, cpu_hpet_channel);
0057 static struct irq_domain        *hpet_domain;
0058 #endif
0059 
0060 static void __iomem         *hpet_virt_address;
0061 
0062 static struct hpet_base         hpet_base;
0063 
0064 static bool             hpet_legacy_int_enabled;
0065 static unsigned long            hpet_freq;
0066 
0067 bool                    boot_hpet_disable;
0068 bool                    hpet_force_user;
0069 static bool             hpet_verbose;
0070 
0071 static inline
0072 struct hpet_channel *clockevent_to_channel(struct clock_event_device *evt)
0073 {
0074     return container_of(evt, struct hpet_channel, evt);
0075 }
0076 
0077 inline unsigned int hpet_readl(unsigned int a)
0078 {
0079     return readl(hpet_virt_address + a);
0080 }
0081 
0082 static inline void hpet_writel(unsigned int d, unsigned int a)
0083 {
0084     writel(d, hpet_virt_address + a);
0085 }
0086 
0087 static inline void hpet_set_mapping(void)
0088 {
0089     hpet_virt_address = ioremap(hpet_address, HPET_MMAP_SIZE);
0090 }
0091 
0092 static inline void hpet_clear_mapping(void)
0093 {
0094     iounmap(hpet_virt_address);
0095     hpet_virt_address = NULL;
0096 }
0097 
0098 /*
0099  * HPET command line enable / disable
0100  */
0101 static int __init hpet_setup(char *str)
0102 {
0103     while (str) {
0104         char *next = strchr(str, ',');
0105 
0106         if (next)
0107             *next++ = 0;
0108         if (!strncmp("disable", str, 7))
0109             boot_hpet_disable = true;
0110         if (!strncmp("force", str, 5))
0111             hpet_force_user = true;
0112         if (!strncmp("verbose", str, 7))
0113             hpet_verbose = true;
0114         str = next;
0115     }
0116     return 1;
0117 }
0118 __setup("hpet=", hpet_setup);
0119 
0120 static int __init disable_hpet(char *str)
0121 {
0122     boot_hpet_disable = true;
0123     return 1;
0124 }
0125 __setup("nohpet", disable_hpet);
0126 
0127 static inline int is_hpet_capable(void)
0128 {
0129     return !boot_hpet_disable && hpet_address;
0130 }
0131 
0132 /**
0133  * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
0134  */
0135 int is_hpet_enabled(void)
0136 {
0137     return is_hpet_capable() && hpet_legacy_int_enabled;
0138 }
0139 EXPORT_SYMBOL_GPL(is_hpet_enabled);
0140 
0141 static void _hpet_print_config(const char *function, int line)
0142 {
0143     u32 i, id, period, cfg, status, channels, l, h;
0144 
0145     pr_info("%s(%d):\n", function, line);
0146 
0147     id = hpet_readl(HPET_ID);
0148     period = hpet_readl(HPET_PERIOD);
0149     pr_info("ID: 0x%x, PERIOD: 0x%x\n", id, period);
0150 
0151     cfg = hpet_readl(HPET_CFG);
0152     status = hpet_readl(HPET_STATUS);
0153     pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status);
0154 
0155     l = hpet_readl(HPET_COUNTER);
0156     h = hpet_readl(HPET_COUNTER+4);
0157     pr_info("COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
0158 
0159     channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
0160 
0161     for (i = 0; i < channels; i++) {
0162         l = hpet_readl(HPET_Tn_CFG(i));
0163         h = hpet_readl(HPET_Tn_CFG(i)+4);
0164         pr_info("T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", i, l, h);
0165 
0166         l = hpet_readl(HPET_Tn_CMP(i));
0167         h = hpet_readl(HPET_Tn_CMP(i)+4);
0168         pr_info("T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", i, l, h);
0169 
0170         l = hpet_readl(HPET_Tn_ROUTE(i));
0171         h = hpet_readl(HPET_Tn_ROUTE(i)+4);
0172         pr_info("T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", i, l, h);
0173     }
0174 }
0175 
0176 #define hpet_print_config()                 \
0177 do {                                \
0178     if (hpet_verbose)                   \
0179         _hpet_print_config(__func__, __LINE__); \
0180 } while (0)
0181 
0182 /*
0183  * When the HPET driver (/dev/hpet) is enabled, we need to reserve
0184  * timer 0 and timer 1 in case of RTC emulation.
0185  */
0186 #ifdef CONFIG_HPET
0187 
0188 static void __init hpet_reserve_platform_timers(void)
0189 {
0190     struct hpet_data hd;
0191     unsigned int i;
0192 
0193     memset(&hd, 0, sizeof(hd));
0194     hd.hd_phys_address  = hpet_address;
0195     hd.hd_address       = hpet_virt_address;
0196     hd.hd_nirqs     = hpet_base.nr_channels;
0197 
0198     /*
0199      * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
0200      * is wrong for i8259!) not the output IRQ.  Many BIOS writers
0201      * don't bother configuring *any* comparator interrupts.
0202      */
0203     hd.hd_irq[0] = HPET_LEGACY_8254;
0204     hd.hd_irq[1] = HPET_LEGACY_RTC;
0205 
0206     for (i = 0; i < hpet_base.nr_channels; i++) {
0207         struct hpet_channel *hc = hpet_base.channels + i;
0208 
0209         if (i >= 2)
0210             hd.hd_irq[i] = hc->irq;
0211 
0212         switch (hc->mode) {
0213         case HPET_MODE_UNUSED:
0214         case HPET_MODE_DEVICE:
0215             hc->mode = HPET_MODE_DEVICE;
0216             break;
0217         case HPET_MODE_CLOCKEVT:
0218         case HPET_MODE_LEGACY:
0219             hpet_reserve_timer(&hd, hc->num);
0220             break;
0221         }
0222     }
0223 
0224     hpet_alloc(&hd);
0225 }
0226 
0227 static void __init hpet_select_device_channel(void)
0228 {
0229     int i;
0230 
0231     for (i = 0; i < hpet_base.nr_channels; i++) {
0232         struct hpet_channel *hc = hpet_base.channels + i;
0233 
0234         /* Associate the first unused channel to /dev/hpet */
0235         if (hc->mode == HPET_MODE_UNUSED) {
0236             hc->mode = HPET_MODE_DEVICE;
0237             return;
0238         }
0239     }
0240 }
0241 
0242 #else
0243 static inline void hpet_reserve_platform_timers(void) { }
0244 static inline void hpet_select_device_channel(void) {}
0245 #endif
0246 
0247 /* Common HPET functions */
0248 static void hpet_stop_counter(void)
0249 {
0250     u32 cfg = hpet_readl(HPET_CFG);
0251 
0252     cfg &= ~HPET_CFG_ENABLE;
0253     hpet_writel(cfg, HPET_CFG);
0254 }
0255 
0256 static void hpet_reset_counter(void)
0257 {
0258     hpet_writel(0, HPET_COUNTER);
0259     hpet_writel(0, HPET_COUNTER + 4);
0260 }
0261 
0262 static void hpet_start_counter(void)
0263 {
0264     unsigned int cfg = hpet_readl(HPET_CFG);
0265 
0266     cfg |= HPET_CFG_ENABLE;
0267     hpet_writel(cfg, HPET_CFG);
0268 }
0269 
0270 static void hpet_restart_counter(void)
0271 {
0272     hpet_stop_counter();
0273     hpet_reset_counter();
0274     hpet_start_counter();
0275 }
0276 
0277 static void hpet_resume_device(void)
0278 {
0279     force_hpet_resume();
0280 }
0281 
0282 static void hpet_resume_counter(struct clocksource *cs)
0283 {
0284     hpet_resume_device();
0285     hpet_restart_counter();
0286 }
0287 
0288 static void hpet_enable_legacy_int(void)
0289 {
0290     unsigned int cfg = hpet_readl(HPET_CFG);
0291 
0292     cfg |= HPET_CFG_LEGACY;
0293     hpet_writel(cfg, HPET_CFG);
0294     hpet_legacy_int_enabled = true;
0295 }
0296 
0297 static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt)
0298 {
0299     unsigned int channel = clockevent_to_channel(evt)->num;
0300     unsigned int cfg, cmp, now;
0301     uint64_t delta;
0302 
0303     hpet_stop_counter();
0304     delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
0305     delta >>= evt->shift;
0306     now = hpet_readl(HPET_COUNTER);
0307     cmp = now + (unsigned int)delta;
0308     cfg = hpet_readl(HPET_Tn_CFG(channel));
0309     cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
0310            HPET_TN_32BIT;
0311     hpet_writel(cfg, HPET_Tn_CFG(channel));
0312     hpet_writel(cmp, HPET_Tn_CMP(channel));
0313     udelay(1);
0314     /*
0315      * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
0316      * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
0317      * bit is automatically cleared after the first write.
0318      * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
0319      * Publication # 24674)
0320      */
0321     hpet_writel((unsigned int)delta, HPET_Tn_CMP(channel));
0322     hpet_start_counter();
0323     hpet_print_config();
0324 
0325     return 0;
0326 }
0327 
0328 static int hpet_clkevt_set_state_oneshot(struct clock_event_device *evt)
0329 {
0330     unsigned int channel = clockevent_to_channel(evt)->num;
0331     unsigned int cfg;
0332 
0333     cfg = hpet_readl(HPET_Tn_CFG(channel));
0334     cfg &= ~HPET_TN_PERIODIC;
0335     cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
0336     hpet_writel(cfg, HPET_Tn_CFG(channel));
0337 
0338     return 0;
0339 }
0340 
0341 static int hpet_clkevt_set_state_shutdown(struct clock_event_device *evt)
0342 {
0343     unsigned int channel = clockevent_to_channel(evt)->num;
0344     unsigned int cfg;
0345 
0346     cfg = hpet_readl(HPET_Tn_CFG(channel));
0347     cfg &= ~HPET_TN_ENABLE;
0348     hpet_writel(cfg, HPET_Tn_CFG(channel));
0349 
0350     return 0;
0351 }
0352 
0353 static int hpet_clkevt_legacy_resume(struct clock_event_device *evt)
0354 {
0355     hpet_enable_legacy_int();
0356     hpet_print_config();
0357     return 0;
0358 }
0359 
0360 static int
0361 hpet_clkevt_set_next_event(unsigned long delta, struct clock_event_device *evt)
0362 {
0363     unsigned int channel = clockevent_to_channel(evt)->num;
0364     u32 cnt;
0365     s32 res;
0366 
0367     cnt = hpet_readl(HPET_COUNTER);
0368     cnt += (u32) delta;
0369     hpet_writel(cnt, HPET_Tn_CMP(channel));
0370 
0371     /*
0372      * HPETs are a complete disaster. The compare register is
0373      * based on a equal comparison and neither provides a less
0374      * than or equal functionality (which would require to take
0375      * the wraparound into account) nor a simple count down event
0376      * mode. Further the write to the comparator register is
0377      * delayed internally up to two HPET clock cycles in certain
0378      * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
0379      * longer delays. We worked around that by reading back the
0380      * compare register, but that required another workaround for
0381      * ICH9,10 chips where the first readout after write can
0382      * return the old stale value. We already had a minimum
0383      * programming delta of 5us enforced, but a NMI or SMI hitting
0384      * between the counter readout and the comparator write can
0385      * move us behind that point easily. Now instead of reading
0386      * the compare register back several times, we make the ETIME
0387      * decision based on the following: Return ETIME if the
0388      * counter value after the write is less than HPET_MIN_CYCLES
0389      * away from the event or if the counter is already ahead of
0390      * the event. The minimum programming delta for the generic
0391      * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
0392      */
0393     res = (s32)(cnt - hpet_readl(HPET_COUNTER));
0394 
0395     return res < HPET_MIN_CYCLES ? -ETIME : 0;
0396 }
0397 
0398 static void hpet_init_clockevent(struct hpet_channel *hc, unsigned int rating)
0399 {
0400     struct clock_event_device *evt = &hc->evt;
0401 
0402     evt->rating     = rating;
0403     evt->irq        = hc->irq;
0404     evt->name       = hc->name;
0405     evt->cpumask        = cpumask_of(hc->cpu);
0406     evt->set_state_oneshot  = hpet_clkevt_set_state_oneshot;
0407     evt->set_next_event = hpet_clkevt_set_next_event;
0408     evt->set_state_shutdown = hpet_clkevt_set_state_shutdown;
0409 
0410     evt->features = CLOCK_EVT_FEAT_ONESHOT;
0411     if (hc->boot_cfg & HPET_TN_PERIODIC) {
0412         evt->features       |= CLOCK_EVT_FEAT_PERIODIC;
0413         evt->set_state_periodic = hpet_clkevt_set_state_periodic;
0414     }
0415 }
0416 
0417 static void __init hpet_legacy_clockevent_register(struct hpet_channel *hc)
0418 {
0419     /*
0420      * Start HPET with the boot CPU's cpumask and make it global after
0421      * the IO_APIC has been initialized.
0422      */
0423     hc->cpu = boot_cpu_data.cpu_index;
0424     strncpy(hc->name, "hpet", sizeof(hc->name));
0425     hpet_init_clockevent(hc, 50);
0426 
0427     hc->evt.tick_resume = hpet_clkevt_legacy_resume;
0428 
0429     /*
0430      * Legacy horrors and sins from the past. HPET used periodic mode
0431      * unconditionally forever on the legacy channel 0. Removing the
0432      * below hack and using the conditional in hpet_init_clockevent()
0433      * makes at least Qemu and one hardware machine fail to boot.
0434      * There are two issues which cause the boot failure:
0435      *
0436      * #1 After the timer delivery test in IOAPIC and the IOAPIC setup
0437      *    the next interrupt is not delivered despite the HPET channel
0438      *    being programmed correctly. Reprogramming the HPET after
0439      *    switching to IOAPIC makes it work again. After fixing this,
0440      *    the next issue surfaces:
0441      *
0442      * #2 Due to the unconditional periodic mode availability the Local
0443      *    APIC timer calibration can hijack the global clockevents
0444      *    event handler without causing damage. Using oneshot at this
0445      *    stage makes if hang because the HPET does not get
0446      *    reprogrammed due to the handler hijacking. Duh, stupid me!
0447      *
0448      * Both issues require major surgery and especially the kick HPET
0449      * again after enabling IOAPIC results in really nasty hackery.
0450      * This 'assume periodic works' magic has survived since HPET
0451      * support got added, so it's questionable whether this should be
0452      * fixed. Both Qemu and the failing hardware machine support
0453      * periodic mode despite the fact that both don't advertise it in
0454      * the configuration register and both need that extra kick after
0455      * switching to IOAPIC. Seems to be a feature...
0456      */
0457     hc->evt.features        |= CLOCK_EVT_FEAT_PERIODIC;
0458     hc->evt.set_state_periodic  = hpet_clkevt_set_state_periodic;
0459 
0460     /* Start HPET legacy interrupts */
0461     hpet_enable_legacy_int();
0462 
0463     clockevents_config_and_register(&hc->evt, hpet_freq,
0464                     HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
0465     global_clock_event = &hc->evt;
0466     pr_debug("Clockevent registered\n");
0467 }
0468 
0469 /*
0470  * HPET MSI Support
0471  */
0472 #ifdef CONFIG_GENERIC_MSI_IRQ
0473 static void hpet_msi_unmask(struct irq_data *data)
0474 {
0475     struct hpet_channel *hc = irq_data_get_irq_handler_data(data);
0476     unsigned int cfg;
0477 
0478     cfg = hpet_readl(HPET_Tn_CFG(hc->num));
0479     cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
0480     hpet_writel(cfg, HPET_Tn_CFG(hc->num));
0481 }
0482 
0483 static void hpet_msi_mask(struct irq_data *data)
0484 {
0485     struct hpet_channel *hc = irq_data_get_irq_handler_data(data);
0486     unsigned int cfg;
0487 
0488     cfg = hpet_readl(HPET_Tn_CFG(hc->num));
0489     cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
0490     hpet_writel(cfg, HPET_Tn_CFG(hc->num));
0491 }
0492 
0493 static void hpet_msi_write(struct hpet_channel *hc, struct msi_msg *msg)
0494 {
0495     hpet_writel(msg->data, HPET_Tn_ROUTE(hc->num));
0496     hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hc->num) + 4);
0497 }
0498 
0499 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
0500 {
0501     hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
0502 }
0503 
0504 static struct irq_chip hpet_msi_controller __ro_after_init = {
0505     .name = "HPET-MSI",
0506     .irq_unmask = hpet_msi_unmask,
0507     .irq_mask = hpet_msi_mask,
0508     .irq_ack = irq_chip_ack_parent,
0509     .irq_set_affinity = msi_domain_set_affinity,
0510     .irq_retrigger = irq_chip_retrigger_hierarchy,
0511     .irq_write_msi_msg = hpet_msi_write_msg,
0512     .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_AFFINITY_PRE_STARTUP,
0513 };
0514 
0515 static int hpet_msi_init(struct irq_domain *domain,
0516              struct msi_domain_info *info, unsigned int virq,
0517              irq_hw_number_t hwirq, msi_alloc_info_t *arg)
0518 {
0519     irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
0520     irq_domain_set_info(domain, virq, arg->hwirq, info->chip, NULL,
0521                 handle_edge_irq, arg->data, "edge");
0522 
0523     return 0;
0524 }
0525 
0526 static void hpet_msi_free(struct irq_domain *domain,
0527               struct msi_domain_info *info, unsigned int virq)
0528 {
0529     irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
0530 }
0531 
0532 static struct msi_domain_ops hpet_msi_domain_ops = {
0533     .msi_init   = hpet_msi_init,
0534     .msi_free   = hpet_msi_free,
0535 };
0536 
0537 static struct msi_domain_info hpet_msi_domain_info = {
0538     .ops        = &hpet_msi_domain_ops,
0539     .chip       = &hpet_msi_controller,
0540     .flags      = MSI_FLAG_USE_DEF_DOM_OPS,
0541 };
0542 
0543 static struct irq_domain *hpet_create_irq_domain(int hpet_id)
0544 {
0545     struct msi_domain_info *domain_info;
0546     struct irq_domain *parent, *d;
0547     struct fwnode_handle *fn;
0548     struct irq_fwspec fwspec;
0549 
0550     if (x86_vector_domain == NULL)
0551         return NULL;
0552 
0553     domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
0554     if (!domain_info)
0555         return NULL;
0556 
0557     *domain_info = hpet_msi_domain_info;
0558     domain_info->data = (void *)(long)hpet_id;
0559 
0560     fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
0561                           hpet_id);
0562     if (!fn) {
0563         kfree(domain_info);
0564         return NULL;
0565     }
0566 
0567     fwspec.fwnode = fn;
0568     fwspec.param_count = 1;
0569     fwspec.param[0] = hpet_id;
0570 
0571     parent = irq_find_matching_fwspec(&fwspec, DOMAIN_BUS_ANY);
0572     if (!parent) {
0573         irq_domain_free_fwnode(fn);
0574         kfree(domain_info);
0575         return NULL;
0576     }
0577     if (parent != x86_vector_domain)
0578         hpet_msi_controller.name = "IR-HPET-MSI";
0579 
0580     d = msi_create_irq_domain(fn, domain_info, parent);
0581     if (!d) {
0582         irq_domain_free_fwnode(fn);
0583         kfree(domain_info);
0584     }
0585     return d;
0586 }
0587 
0588 static inline int hpet_dev_id(struct irq_domain *domain)
0589 {
0590     struct msi_domain_info *info = msi_get_domain_info(domain);
0591 
0592     return (int)(long)info->data;
0593 }
0594 
0595 static int hpet_assign_irq(struct irq_domain *domain, struct hpet_channel *hc,
0596                int dev_num)
0597 {
0598     struct irq_alloc_info info;
0599 
0600     init_irq_alloc_info(&info, NULL);
0601     info.type = X86_IRQ_ALLOC_TYPE_HPET;
0602     info.data = hc;
0603     info.devid = hpet_dev_id(domain);
0604     info.hwirq = dev_num;
0605 
0606     return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);
0607 }
0608 
0609 static int hpet_clkevt_msi_resume(struct clock_event_device *evt)
0610 {
0611     struct hpet_channel *hc = clockevent_to_channel(evt);
0612     struct irq_data *data = irq_get_irq_data(hc->irq);
0613     struct msi_msg msg;
0614 
0615     /* Restore the MSI msg and unmask the interrupt */
0616     irq_chip_compose_msi_msg(data, &msg);
0617     hpet_msi_write(hc, &msg);
0618     hpet_msi_unmask(data);
0619     return 0;
0620 }
0621 
0622 static irqreturn_t hpet_msi_interrupt_handler(int irq, void *data)
0623 {
0624     struct hpet_channel *hc = data;
0625     struct clock_event_device *evt = &hc->evt;
0626 
0627     if (!evt->event_handler) {
0628         pr_info("Spurious interrupt HPET channel %d\n", hc->num);
0629         return IRQ_HANDLED;
0630     }
0631 
0632     evt->event_handler(evt);
0633     return IRQ_HANDLED;
0634 }
0635 
0636 static int hpet_setup_msi_irq(struct hpet_channel *hc)
0637 {
0638     if (request_irq(hc->irq, hpet_msi_interrupt_handler,
0639             IRQF_TIMER | IRQF_NOBALANCING,
0640             hc->name, hc))
0641         return -1;
0642 
0643     disable_irq(hc->irq);
0644     irq_set_affinity(hc->irq, cpumask_of(hc->cpu));
0645     enable_irq(hc->irq);
0646 
0647     pr_debug("%s irq %u for MSI\n", hc->name, hc->irq);
0648 
0649     return 0;
0650 }
0651 
0652 /* Invoked from the hotplug callback on @cpu */
0653 static void init_one_hpet_msi_clockevent(struct hpet_channel *hc, int cpu)
0654 {
0655     struct clock_event_device *evt = &hc->evt;
0656 
0657     hc->cpu = cpu;
0658     per_cpu(cpu_hpet_channel, cpu) = hc;
0659     hpet_setup_msi_irq(hc);
0660 
0661     hpet_init_clockevent(hc, 110);
0662     evt->tick_resume = hpet_clkevt_msi_resume;
0663 
0664     clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
0665                     0x7FFFFFFF);
0666 }
0667 
0668 static struct hpet_channel *hpet_get_unused_clockevent(void)
0669 {
0670     int i;
0671 
0672     for (i = 0; i < hpet_base.nr_channels; i++) {
0673         struct hpet_channel *hc = hpet_base.channels + i;
0674 
0675         if (hc->mode != HPET_MODE_CLOCKEVT || hc->in_use)
0676             continue;
0677         hc->in_use = 1;
0678         return hc;
0679     }
0680     return NULL;
0681 }
0682 
0683 static int hpet_cpuhp_online(unsigned int cpu)
0684 {
0685     struct hpet_channel *hc = hpet_get_unused_clockevent();
0686 
0687     if (hc)
0688         init_one_hpet_msi_clockevent(hc, cpu);
0689     return 0;
0690 }
0691 
0692 static int hpet_cpuhp_dead(unsigned int cpu)
0693 {
0694     struct hpet_channel *hc = per_cpu(cpu_hpet_channel, cpu);
0695 
0696     if (!hc)
0697         return 0;
0698     free_irq(hc->irq, hc);
0699     hc->in_use = 0;
0700     per_cpu(cpu_hpet_channel, cpu) = NULL;
0701     return 0;
0702 }
0703 
0704 static void __init hpet_select_clockevents(void)
0705 {
0706     unsigned int i;
0707 
0708     hpet_base.nr_clockevents = 0;
0709 
0710     /* No point if MSI is disabled or CPU has an Always Runing APIC Timer */
0711     if (hpet_msi_disable || boot_cpu_has(X86_FEATURE_ARAT))
0712         return;
0713 
0714     hpet_print_config();
0715 
0716     hpet_domain = hpet_create_irq_domain(hpet_blockid);
0717     if (!hpet_domain)
0718         return;
0719 
0720     for (i = 0; i < hpet_base.nr_channels; i++) {
0721         struct hpet_channel *hc = hpet_base.channels + i;
0722         int irq;
0723 
0724         if (hc->mode != HPET_MODE_UNUSED)
0725             continue;
0726 
0727         /* Only consider HPET channel with MSI support */
0728         if (!(hc->boot_cfg & HPET_TN_FSB_CAP))
0729             continue;
0730 
0731         sprintf(hc->name, "hpet%d", i);
0732 
0733         irq = hpet_assign_irq(hpet_domain, hc, hc->num);
0734         if (irq <= 0)
0735             continue;
0736 
0737         hc->irq = irq;
0738         hc->mode = HPET_MODE_CLOCKEVT;
0739 
0740         if (++hpet_base.nr_clockevents == num_possible_cpus())
0741             break;
0742     }
0743 
0744     pr_info("%d channels of %d reserved for per-cpu timers\n",
0745         hpet_base.nr_channels, hpet_base.nr_clockevents);
0746 }
0747 
0748 #else
0749 
0750 static inline void hpet_select_clockevents(void) { }
0751 
0752 #define hpet_cpuhp_online   NULL
0753 #define hpet_cpuhp_dead     NULL
0754 
0755 #endif
0756 
0757 /*
0758  * Clock source related code
0759  */
0760 #if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
0761 /*
0762  * Reading the HPET counter is a very slow operation. If a large number of
0763  * CPUs are trying to access the HPET counter simultaneously, it can cause
0764  * massive delays and slow down system performance dramatically. This may
0765  * happen when HPET is the default clock source instead of TSC. For a
0766  * really large system with hundreds of CPUs, the slowdown may be so
0767  * severe, that it can actually crash the system because of a NMI watchdog
0768  * soft lockup, for example.
0769  *
0770  * If multiple CPUs are trying to access the HPET counter at the same time,
0771  * we don't actually need to read the counter multiple times. Instead, the
0772  * other CPUs can use the counter value read by the first CPU in the group.
0773  *
0774  * This special feature is only enabled on x86-64 systems. It is unlikely
0775  * that 32-bit x86 systems will have enough CPUs to require this feature
0776  * with its associated locking overhead. We also need 64-bit atomic read.
0777  *
0778  * The lock and the HPET value are stored together and can be read in a
0779  * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
0780  * is 32 bits in size.
0781  */
0782 union hpet_lock {
0783     struct {
0784         arch_spinlock_t lock;
0785         u32 value;
0786     };
0787     u64 lockval;
0788 };
0789 
0790 static union hpet_lock hpet __cacheline_aligned = {
0791     { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
0792 };
0793 
0794 static u64 read_hpet(struct clocksource *cs)
0795 {
0796     unsigned long flags;
0797     union hpet_lock old, new;
0798 
0799     BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
0800 
0801     /*
0802      * Read HPET directly if in NMI.
0803      */
0804     if (in_nmi())
0805         return (u64)hpet_readl(HPET_COUNTER);
0806 
0807     /*
0808      * Read the current state of the lock and HPET value atomically.
0809      */
0810     old.lockval = READ_ONCE(hpet.lockval);
0811 
0812     if (arch_spin_is_locked(&old.lock))
0813         goto contended;
0814 
0815     local_irq_save(flags);
0816     if (arch_spin_trylock(&hpet.lock)) {
0817         new.value = hpet_readl(HPET_COUNTER);
0818         /*
0819          * Use WRITE_ONCE() to prevent store tearing.
0820          */
0821         WRITE_ONCE(hpet.value, new.value);
0822         arch_spin_unlock(&hpet.lock);
0823         local_irq_restore(flags);
0824         return (u64)new.value;
0825     }
0826     local_irq_restore(flags);
0827 
0828 contended:
0829     /*
0830      * Contended case
0831      * --------------
0832      * Wait until the HPET value change or the lock is free to indicate
0833      * its value is up-to-date.
0834      *
0835      * It is possible that old.value has already contained the latest
0836      * HPET value while the lock holder was in the process of releasing
0837      * the lock. Checking for lock state change will enable us to return
0838      * the value immediately instead of waiting for the next HPET reader
0839      * to come along.
0840      */
0841     do {
0842         cpu_relax();
0843         new.lockval = READ_ONCE(hpet.lockval);
0844     } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
0845 
0846     return (u64)new.value;
0847 }
0848 #else
0849 /*
0850  * For UP or 32-bit.
0851  */
0852 static u64 read_hpet(struct clocksource *cs)
0853 {
0854     return (u64)hpet_readl(HPET_COUNTER);
0855 }
0856 #endif
0857 
0858 static struct clocksource clocksource_hpet = {
0859     .name       = "hpet",
0860     .rating     = 250,
0861     .read       = read_hpet,
0862     .mask       = HPET_MASK,
0863     .flags      = CLOCK_SOURCE_IS_CONTINUOUS,
0864     .resume     = hpet_resume_counter,
0865 };
0866 
0867 /*
0868  * AMD SB700 based systems with spread spectrum enabled use a SMM based
0869  * HPET emulation to provide proper frequency setting.
0870  *
0871  * On such systems the SMM code is initialized with the first HPET register
0872  * access and takes some time to complete. During this time the config
0873  * register reads 0xffffffff. We check for max 1000 loops whether the
0874  * config register reads a non-0xffffffff value to make sure that the
0875  * HPET is up and running before we proceed any further.
0876  *
0877  * A counting loop is safe, as the HPET access takes thousands of CPU cycles.
0878  *
0879  * On non-SB700 based machines this check is only done once and has no
0880  * side effects.
0881  */
0882 static bool __init hpet_cfg_working(void)
0883 {
0884     int i;
0885 
0886     for (i = 0; i < 1000; i++) {
0887         if (hpet_readl(HPET_CFG) != 0xFFFFFFFF)
0888             return true;
0889     }
0890 
0891     pr_warn("Config register invalid. Disabling HPET\n");
0892     return false;
0893 }
0894 
0895 static bool __init hpet_counting(void)
0896 {
0897     u64 start, now, t1;
0898 
0899     hpet_restart_counter();
0900 
0901     t1 = hpet_readl(HPET_COUNTER);
0902     start = rdtsc();
0903 
0904     /*
0905      * We don't know the TSC frequency yet, but waiting for
0906      * 200000 TSC cycles is safe:
0907      * 4 GHz == 50us
0908      * 1 GHz == 200us
0909      */
0910     do {
0911         if (t1 != hpet_readl(HPET_COUNTER))
0912             return true;
0913         now = rdtsc();
0914     } while ((now - start) < 200000UL);
0915 
0916     pr_warn("Counter not counting. HPET disabled\n");
0917     return false;
0918 }
0919 
0920 static bool __init mwait_pc10_supported(void)
0921 {
0922     unsigned int eax, ebx, ecx, mwait_substates;
0923 
0924     if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
0925         return false;
0926 
0927     if (!cpu_feature_enabled(X86_FEATURE_MWAIT))
0928         return false;
0929 
0930     if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
0931         return false;
0932 
0933     cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
0934 
0935     return (ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) &&
0936            (ecx & CPUID5_ECX_INTERRUPT_BREAK) &&
0937            (mwait_substates & (0xF << 28));
0938 }
0939 
0940 /*
0941  * Check whether the system supports PC10. If so force disable HPET as that
0942  * stops counting in PC10. This check is overbroad as it does not take any
0943  * of the following into account:
0944  *
0945  *  - ACPI tables
0946  *  - Enablement of intel_idle
0947  *  - Command line arguments which limit intel_idle C-state support
0948  *
0949  * That's perfectly fine. HPET is a piece of hardware designed by committee
0950  * and the only reasons why it is still in use on modern systems is the
0951  * fact that it is impossible to reliably query TSC and CPU frequency via
0952  * CPUID or firmware.
0953  *
0954  * If HPET is functional it is useful for calibrating TSC, but this can be
0955  * done via PMTIMER as well which seems to be the last remaining timer on
0956  * X86/INTEL platforms that has not been completely wreckaged by feature
0957  * creep.
0958  *
0959  * In theory HPET support should be removed altogether, but there are older
0960  * systems out there which depend on it because TSC and APIC timer are
0961  * dysfunctional in deeper C-states.
0962  *
0963  * It's only 20 years now that hardware people have been asked to provide
0964  * reliable and discoverable facilities which can be used for timekeeping
0965  * and per CPU timer interrupts.
0966  *
0967  * The probability that this problem is going to be solved in the
0968  * forseeable future is close to zero, so the kernel has to be cluttered
0969  * with heuristics to keep up with the ever growing amount of hardware and
0970  * firmware trainwrecks. Hopefully some day hardware people will understand
0971  * that the approach of "This can be fixed in software" is not sustainable.
0972  * Hope dies last...
0973  */
0974 static bool __init hpet_is_pc10_damaged(void)
0975 {
0976     unsigned long long pcfg;
0977 
0978     /* Check whether PC10 substates are supported */
0979     if (!mwait_pc10_supported())
0980         return false;
0981 
0982     /* Check whether PC10 is enabled in PKG C-state limit */
0983     rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, pcfg);
0984     if ((pcfg & 0xF) < 8)
0985         return false;
0986 
0987     if (hpet_force_user) {
0988         pr_warn("HPET force enabled via command line, but dysfunctional in PC10.\n");
0989         return false;
0990     }
0991 
0992     pr_info("HPET dysfunctional in PC10. Force disabled.\n");
0993     boot_hpet_disable = true;
0994     return true;
0995 }
0996 
0997 /**
0998  * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
0999  */
1000 int __init hpet_enable(void)
1001 {
1002     u32 hpet_period, cfg, id, irq;
1003     unsigned int i, channels;
1004     struct hpet_channel *hc;
1005     u64 freq;
1006 
1007     if (!is_hpet_capable())
1008         return 0;
1009 
1010     if (hpet_is_pc10_damaged())
1011         return 0;
1012 
1013     hpet_set_mapping();
1014     if (!hpet_virt_address)
1015         return 0;
1016 
1017     /* Validate that the config register is working */
1018     if (!hpet_cfg_working())
1019         goto out_nohpet;
1020 
1021     /*
1022      * Read the period and check for a sane value:
1023      */
1024     hpet_period = hpet_readl(HPET_PERIOD);
1025     if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
1026         goto out_nohpet;
1027 
1028     /* The period is a femtoseconds value. Convert it to a frequency. */
1029     freq = FSEC_PER_SEC;
1030     do_div(freq, hpet_period);
1031     hpet_freq = freq;
1032 
1033     /*
1034      * Read the HPET ID register to retrieve the IRQ routing
1035      * information and the number of channels
1036      */
1037     id = hpet_readl(HPET_ID);
1038     hpet_print_config();
1039 
1040     /* This is the HPET channel number which is zero based */
1041     channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
1042 
1043     /*
1044      * The legacy routing mode needs at least two channels, tick timer
1045      * and the rtc emulation channel.
1046      */
1047     if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC) && channels < 2)
1048         goto out_nohpet;
1049 
1050     hc = kcalloc(channels, sizeof(*hc), GFP_KERNEL);
1051     if (!hc) {
1052         pr_warn("Disabling HPET.\n");
1053         goto out_nohpet;
1054     }
1055     hpet_base.channels = hc;
1056     hpet_base.nr_channels = channels;
1057 
1058     /* Read, store and sanitize the global configuration */
1059     cfg = hpet_readl(HPET_CFG);
1060     hpet_base.boot_cfg = cfg;
1061     cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
1062     hpet_writel(cfg, HPET_CFG);
1063     if (cfg)
1064         pr_warn("Global config: Unknown bits %#x\n", cfg);
1065 
1066     /* Read, store and sanitize the per channel configuration */
1067     for (i = 0; i < channels; i++, hc++) {
1068         hc->num = i;
1069 
1070         cfg = hpet_readl(HPET_Tn_CFG(i));
1071         hc->boot_cfg = cfg;
1072         irq = (cfg & Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
1073         hc->irq = irq;
1074 
1075         cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
1076         hpet_writel(cfg, HPET_Tn_CFG(i));
1077 
1078         cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
1079              | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
1080              | HPET_TN_FSB | HPET_TN_FSB_CAP);
1081         if (cfg)
1082             pr_warn("Channel #%u config: Unknown bits %#x\n", i, cfg);
1083     }
1084     hpet_print_config();
1085 
1086     /*
1087      * Validate that the counter is counting. This needs to be done
1088      * after sanitizing the config registers to properly deal with
1089      * force enabled HPETs.
1090      */
1091     if (!hpet_counting())
1092         goto out_nohpet;
1093 
1094     clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
1095 
1096     if (id & HPET_ID_LEGSUP) {
1097         hpet_legacy_clockevent_register(&hpet_base.channels[0]);
1098         hpet_base.channels[0].mode = HPET_MODE_LEGACY;
1099         if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC))
1100             hpet_base.channels[1].mode = HPET_MODE_LEGACY;
1101         return 1;
1102     }
1103     return 0;
1104 
1105 out_nohpet:
1106     kfree(hpet_base.channels);
1107     hpet_base.channels = NULL;
1108     hpet_base.nr_channels = 0;
1109     hpet_clear_mapping();
1110     hpet_address = 0;
1111     return 0;
1112 }
1113 
1114 /*
1115  * The late initialization runs after the PCI quirks have been invoked
1116  * which might have detected a system on which the HPET can be enforced.
1117  *
1118  * Also, the MSI machinery is not working yet when the HPET is initialized
1119  * early.
1120  *
1121  * If the HPET is enabled, then:
1122  *
1123  *  1) Reserve one channel for /dev/hpet if CONFIG_HPET=y
1124  *  2) Reserve up to num_possible_cpus() channels as per CPU clockevents
1125  *  3) Setup /dev/hpet if CONFIG_HPET=y
1126  *  4) Register hotplug callbacks when clockevents are available
1127  */
1128 static __init int hpet_late_init(void)
1129 {
1130     int ret;
1131 
1132     if (!hpet_address) {
1133         if (!force_hpet_address)
1134             return -ENODEV;
1135 
1136         hpet_address = force_hpet_address;
1137         hpet_enable();
1138     }
1139 
1140     if (!hpet_virt_address)
1141         return -ENODEV;
1142 
1143     hpet_select_device_channel();
1144     hpet_select_clockevents();
1145     hpet_reserve_platform_timers();
1146     hpet_print_config();
1147 
1148     if (!hpet_base.nr_clockevents)
1149         return 0;
1150 
1151     ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online",
1152                 hpet_cpuhp_online, NULL);
1153     if (ret)
1154         return ret;
1155     ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL,
1156                 hpet_cpuhp_dead);
1157     if (ret)
1158         goto err_cpuhp;
1159     return 0;
1160 
1161 err_cpuhp:
1162     cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
1163     return ret;
1164 }
1165 fs_initcall(hpet_late_init);
1166 
1167 void hpet_disable(void)
1168 {
1169     unsigned int i;
1170     u32 cfg;
1171 
1172     if (!is_hpet_capable() || !hpet_virt_address)
1173         return;
1174 
1175     /* Restore boot configuration with the enable bit cleared */
1176     cfg = hpet_base.boot_cfg;
1177     cfg &= ~HPET_CFG_ENABLE;
1178     hpet_writel(cfg, HPET_CFG);
1179 
1180     /* Restore the channel boot configuration */
1181     for (i = 0; i < hpet_base.nr_channels; i++)
1182         hpet_writel(hpet_base.channels[i].boot_cfg, HPET_Tn_CFG(i));
1183 
1184     /* If the HPET was enabled at boot time, reenable it */
1185     if (hpet_base.boot_cfg & HPET_CFG_ENABLE)
1186         hpet_writel(hpet_base.boot_cfg, HPET_CFG);
1187 }
1188 
1189 #ifdef CONFIG_HPET_EMULATE_RTC
1190 
1191 /*
1192  * HPET in LegacyReplacement mode eats up the RTC interrupt line. When HPET
1193  * is enabled, we support RTC interrupt functionality in software.
1194  *
1195  * RTC has 3 kinds of interrupts:
1196  *
1197  *  1) Update Interrupt - generate an interrupt, every second, when the
1198  *     RTC clock is updated
1199  *  2) Alarm Interrupt - generate an interrupt at a specific time of day
1200  *  3) Periodic Interrupt - generate periodic interrupt, with frequencies
1201  *     2Hz-8192Hz (2Hz-64Hz for non-root user) (all frequencies in powers of 2)
1202  *
1203  * (1) and (2) above are implemented using polling at a frequency of 64 Hz:
1204  * DEFAULT_RTC_INT_FREQ.
1205  *
1206  * The exact frequency is a tradeoff between accuracy and interrupt overhead.
1207  *
1208  * For (3), we use interrupts at 64 Hz, or the user specified periodic frequency,
1209  * if it's higher.
1210  */
1211 #include <linux/mc146818rtc.h>
1212 #include <linux/rtc.h>
1213 
1214 #define DEFAULT_RTC_INT_FREQ    64
1215 #define DEFAULT_RTC_SHIFT   6
1216 #define RTC_NUM_INTS        1
1217 
1218 static unsigned long hpet_rtc_flags;
1219 static int hpet_prev_update_sec;
1220 static struct rtc_time hpet_alarm_time;
1221 static unsigned long hpet_pie_count;
1222 static u32 hpet_t1_cmp;
1223 static u32 hpet_default_delta;
1224 static u32 hpet_pie_delta;
1225 static unsigned long hpet_pie_limit;
1226 
1227 static rtc_irq_handler irq_handler;
1228 
1229 /*
1230  * Check that the HPET counter c1 is ahead of c2
1231  */
1232 static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1233 {
1234     return (s32)(c2 - c1) < 0;
1235 }
1236 
1237 /*
1238  * Registers a IRQ handler.
1239  */
1240 int hpet_register_irq_handler(rtc_irq_handler handler)
1241 {
1242     if (!is_hpet_enabled())
1243         return -ENODEV;
1244     if (irq_handler)
1245         return -EBUSY;
1246 
1247     irq_handler = handler;
1248 
1249     return 0;
1250 }
1251 EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1252 
1253 /*
1254  * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1255  * and does cleanup.
1256  */
1257 void hpet_unregister_irq_handler(rtc_irq_handler handler)
1258 {
1259     if (!is_hpet_enabled())
1260         return;
1261 
1262     irq_handler = NULL;
1263     hpet_rtc_flags = 0;
1264 }
1265 EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1266 
1267 /*
1268  * Channel 1 for RTC emulation. We use one shot mode, as periodic mode
1269  * is not supported by all HPET implementations for channel 1.
1270  *
1271  * hpet_rtc_timer_init() is called when the rtc is initialized.
1272  */
1273 int hpet_rtc_timer_init(void)
1274 {
1275     unsigned int cfg, cnt, delta;
1276     unsigned long flags;
1277 
1278     if (!is_hpet_enabled())
1279         return 0;
1280 
1281     if (!hpet_default_delta) {
1282         struct clock_event_device *evt = &hpet_base.channels[0].evt;
1283         uint64_t clc;
1284 
1285         clc = (uint64_t) evt->mult * NSEC_PER_SEC;
1286         clc >>= evt->shift + DEFAULT_RTC_SHIFT;
1287         hpet_default_delta = clc;
1288     }
1289 
1290     if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1291         delta = hpet_default_delta;
1292     else
1293         delta = hpet_pie_delta;
1294 
1295     local_irq_save(flags);
1296 
1297     cnt = delta + hpet_readl(HPET_COUNTER);
1298     hpet_writel(cnt, HPET_T1_CMP);
1299     hpet_t1_cmp = cnt;
1300 
1301     cfg = hpet_readl(HPET_T1_CFG);
1302     cfg &= ~HPET_TN_PERIODIC;
1303     cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1304     hpet_writel(cfg, HPET_T1_CFG);
1305 
1306     local_irq_restore(flags);
1307 
1308     return 1;
1309 }
1310 EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1311 
1312 static void hpet_disable_rtc_channel(void)
1313 {
1314     u32 cfg = hpet_readl(HPET_T1_CFG);
1315 
1316     cfg &= ~HPET_TN_ENABLE;
1317     hpet_writel(cfg, HPET_T1_CFG);
1318 }
1319 
1320 /*
1321  * The functions below are called from rtc driver.
1322  * Return 0 if HPET is not being used.
1323  * Otherwise do the necessary changes and return 1.
1324  */
1325 int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1326 {
1327     if (!is_hpet_enabled())
1328         return 0;
1329 
1330     hpet_rtc_flags &= ~bit_mask;
1331     if (unlikely(!hpet_rtc_flags))
1332         hpet_disable_rtc_channel();
1333 
1334     return 1;
1335 }
1336 EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1337 
1338 int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1339 {
1340     unsigned long oldbits = hpet_rtc_flags;
1341 
1342     if (!is_hpet_enabled())
1343         return 0;
1344 
1345     hpet_rtc_flags |= bit_mask;
1346 
1347     if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1348         hpet_prev_update_sec = -1;
1349 
1350     if (!oldbits)
1351         hpet_rtc_timer_init();
1352 
1353     return 1;
1354 }
1355 EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1356 
1357 int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
1358 {
1359     if (!is_hpet_enabled())
1360         return 0;
1361 
1362     hpet_alarm_time.tm_hour = hrs;
1363     hpet_alarm_time.tm_min = min;
1364     hpet_alarm_time.tm_sec = sec;
1365 
1366     return 1;
1367 }
1368 EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1369 
1370 int hpet_set_periodic_freq(unsigned long freq)
1371 {
1372     uint64_t clc;
1373 
1374     if (!is_hpet_enabled())
1375         return 0;
1376 
1377     if (freq <= DEFAULT_RTC_INT_FREQ) {
1378         hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1379     } else {
1380         struct clock_event_device *evt = &hpet_base.channels[0].evt;
1381 
1382         clc = (uint64_t) evt->mult * NSEC_PER_SEC;
1383         do_div(clc, freq);
1384         clc >>= evt->shift;
1385         hpet_pie_delta = clc;
1386         hpet_pie_limit = 0;
1387     }
1388 
1389     return 1;
1390 }
1391 EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1392 
1393 int hpet_rtc_dropped_irq(void)
1394 {
1395     return is_hpet_enabled();
1396 }
1397 EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1398 
1399 static void hpet_rtc_timer_reinit(void)
1400 {
1401     unsigned int delta;
1402     int lost_ints = -1;
1403 
1404     if (unlikely(!hpet_rtc_flags))
1405         hpet_disable_rtc_channel();
1406 
1407     if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1408         delta = hpet_default_delta;
1409     else
1410         delta = hpet_pie_delta;
1411 
1412     /*
1413      * Increment the comparator value until we are ahead of the
1414      * current count.
1415      */
1416     do {
1417         hpet_t1_cmp += delta;
1418         hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1419         lost_ints++;
1420     } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1421 
1422     if (lost_ints) {
1423         if (hpet_rtc_flags & RTC_PIE)
1424             hpet_pie_count += lost_ints;
1425         if (printk_ratelimit())
1426             pr_warn("Lost %d RTC interrupts\n", lost_ints);
1427     }
1428 }
1429 
1430 irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1431 {
1432     struct rtc_time curr_time;
1433     unsigned long rtc_int_flag = 0;
1434 
1435     hpet_rtc_timer_reinit();
1436     memset(&curr_time, 0, sizeof(struct rtc_time));
1437 
1438     if (hpet_rtc_flags & (RTC_UIE | RTC_AIE)) {
1439         if (unlikely(mc146818_get_time(&curr_time) < 0)) {
1440             pr_err_ratelimited("unable to read current time from RTC\n");
1441             return IRQ_HANDLED;
1442         }
1443     }
1444 
1445     if (hpet_rtc_flags & RTC_UIE &&
1446         curr_time.tm_sec != hpet_prev_update_sec) {
1447         if (hpet_prev_update_sec >= 0)
1448             rtc_int_flag = RTC_UF;
1449         hpet_prev_update_sec = curr_time.tm_sec;
1450     }
1451 
1452     if (hpet_rtc_flags & RTC_PIE && ++hpet_pie_count >= hpet_pie_limit) {
1453         rtc_int_flag |= RTC_PF;
1454         hpet_pie_count = 0;
1455     }
1456 
1457     if (hpet_rtc_flags & RTC_AIE &&
1458         (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1459         (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1460         (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1461         rtc_int_flag |= RTC_AF;
1462 
1463     if (rtc_int_flag) {
1464         rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1465         if (irq_handler)
1466             irq_handler(rtc_int_flag, dev_id);
1467     }
1468     return IRQ_HANDLED;
1469 }
1470 EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1471 #endif
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!