kernel/cpu/zhaoxin.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/sched.h>
0003 #include <linux/sched/clock.h>
0004
0005 #include <asm/cpu.h>
0006 #include <asm/cpufeature.h>
0007
0008 #include "cpu.h"
0009
0010 #define MSR_ZHAOXIN_FCR57 0x00001257
0011
0012 #define ACE_PRESENT (1 << 6)
0013 #define ACE_ENABLED (1 << 7)
0014 #define ACE_FCR     (1 << 7)    /* MSR_ZHAOXIN_FCR */
0015
0016 #define RNG_PRESENT (1 << 2)
0017 #define RNG_ENABLED (1 << 3)
0018 #define RNG_ENABLE  (1 << 8)    /* MSR_ZHAOXIN_RNG */
0019
0020 static void init_zhaoxin_cap(struct cpuinfo_x86 *c)
0021 {
0022     u32  lo, hi;
0023
0024     /* Test for Extended Feature Flags presence */
0025     if (cpuid_eax(0xC0000000) >= 0xC0000001) {
0026         u32 tmp = cpuid_edx(0xC0000001);
0027
0028         /* Enable ACE unit, if present and disabled */
0029         if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
0030             rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
0031             /* Enable ACE unit */
0032             lo |= ACE_FCR;
0033             wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
0034             pr_info("CPU: Enabled ACE h/w crypto\n");
0035         }
0036
0037         /* Enable RNG unit, if present and disabled */
0038         if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
0039             rdmsr(MSR_ZHAOXIN_FCR57, lo, hi);
0040             /* Enable RNG unit */
0041             lo |= RNG_ENABLE;
0042             wrmsr(MSR_ZHAOXIN_FCR57, lo, hi);
0043             pr_info("CPU: Enabled h/w RNG\n");
0044         }
0045
0046         /*
0047          * Store Extended Feature Flags as word 5 of the CPU
0048          * capability bit array
0049          */
0050         c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
0051     }
0052
0053     if (c->x86 >= 0x6)
0054         set_cpu_cap(c, X86_FEATURE_REP_GOOD);
0055 }
0056
0057 static void early_init_zhaoxin(struct cpuinfo_x86 *c)
0058 {
0059     if (c->x86 >= 0x6)
0060         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
0061 #ifdef CONFIG_X86_64
0062     set_cpu_cap(c, X86_FEATURE_SYSENTER32);
0063 #endif
0064     if (c->x86_power & (1 << 8)) {
0065         set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
0066         set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
0067     }
0068
0069     if (c->cpuid_level >= 0x00000001) {
0070         u32 eax, ebx, ecx, edx;
0071
0072         cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
0073         /*
0074          * If HTT (EDX[28]) is set EBX[16:23] contain the number of
0075          * apicids which are reserved per package. Store the resulting
0076          * shift value for the package management code.
0077          */
0078         if (edx & (1U << 28))
0079             c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
0080     }
0081
0082 }
0083
0084 static void init_zhaoxin(struct cpuinfo_x86 *c)
0085 {
0086     early_init_zhaoxin(c);
0087     init_intel_cacheinfo(c);
0088     detect_num_cpu_cores(c);
0089 #ifdef CONFIG_X86_32
0090     detect_ht(c);
0091 #endif
0092
0093     if (c->cpuid_level > 9) {
0094         unsigned int eax = cpuid_eax(10);
0095
0096         /*
0097          * Check for version and the number of counters
0098          * Version(eax[7:0]) can't be 0;
0099          * Counters(eax[15:8]) should be greater than 1;
0100          */
0101         if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
0102             set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
0103     }
0104
0105     if (c->x86 >= 0x6)
0106         init_zhaoxin_cap(c);
0107 #ifdef CONFIG_X86_64
0108     set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
0109 #endif
0110
0111     init_ia32_feat_ctl(c);
0112 }
0113
0114 #ifdef CONFIG_X86_32
0115 static unsigned int
0116 zhaoxin_size_cache(struct cpuinfo_x86 *c, unsigned int size)
0117 {
0118     return size;
0119 }
0120 #endif
0121
0122 static const struct cpu_dev zhaoxin_cpu_dev = {
0123     .c_vendor   = "zhaoxin",
0124     .c_ident    = { "  Shanghai  " },
0125     .c_early_init   = early_init_zhaoxin,
0126     .c_init     = init_zhaoxin,
0127 #ifdef CONFIG_X86_32
0128     .legacy_cache_size = zhaoxin_size_cache,
0129 #endif
0130     .c_x86_vendor   = X86_VENDOR_ZHAOXIN,
0131 };
0132
0133 cpu_dev_register(zhaoxin_cpu_dev);