kernel/cpu/scattered.c

0001 /*
0002  *  Routines to identify additional cpu features that are scattered in
0003  *  cpuid space.
0004  */
0005 #include <linux/cpu.h>
0006
0007 #include <asm/memtype.h>
0008 #include <asm/apic.h>
0009 #include <asm/processor.h>
0010
0011 #include "cpu.h"
0012
0013 struct cpuid_bit {
0014     u16 feature;
0015     u8 reg;
0016     u8 bit;
0017     u32 level;
0018     u32 sub_leaf;
0019 };
0020
0021 /*
0022  * Please keep the leaf sorted by cpuid_bit.level for faster search.
0023  * X86_FEATURE_MBA is supported by both Intel and AMD. But the CPUID
0024  * levels are different and there is a separate entry for each.
0025  */
0026 static const struct cpuid_bit cpuid_bits[] = {
0027     { X86_FEATURE_APERFMPERF,       CPUID_ECX,  0, 0x00000006, 0 },
0028     { X86_FEATURE_EPB,      CPUID_ECX,  3, 0x00000006, 0 },
0029     { X86_FEATURE_INTEL_PPIN,   CPUID_EBX,  0, 0x00000007, 1 },
0030     { X86_FEATURE_RRSBA_CTRL,   CPUID_EDX,  2, 0x00000007, 2 },
0031     { X86_FEATURE_CQM_LLC,      CPUID_EDX,  1, 0x0000000f, 0 },
0032     { X86_FEATURE_CQM_OCCUP_LLC,    CPUID_EDX,  0, 0x0000000f, 1 },
0033     { X86_FEATURE_CQM_MBM_TOTAL,    CPUID_EDX,  1, 0x0000000f, 1 },
0034     { X86_FEATURE_CQM_MBM_LOCAL,    CPUID_EDX,  2, 0x0000000f, 1 },
0035     { X86_FEATURE_CAT_L3,       CPUID_EBX,  1, 0x00000010, 0 },
0036     { X86_FEATURE_CAT_L2,       CPUID_EBX,  2, 0x00000010, 0 },
0037     { X86_FEATURE_CDP_L3,       CPUID_ECX,  2, 0x00000010, 1 },
0038     { X86_FEATURE_CDP_L2,       CPUID_ECX,  2, 0x00000010, 2 },
0039     { X86_FEATURE_MBA,      CPUID_EBX,  3, 0x00000010, 0 },
0040     { X86_FEATURE_PER_THREAD_MBA,   CPUID_ECX,  0, 0x00000010, 3 },
0041     { X86_FEATURE_SGX1,     CPUID_EAX,  0, 0x00000012, 0 },
0042     { X86_FEATURE_SGX2,     CPUID_EAX,  1, 0x00000012, 0 },
0043     { X86_FEATURE_HW_PSTATE,    CPUID_EDX,  7, 0x80000007, 0 },
0044     { X86_FEATURE_CPB,      CPUID_EDX,  9, 0x80000007, 0 },
0045     { X86_FEATURE_PROC_FEEDBACK,    CPUID_EDX, 11, 0x80000007, 0 },
0046     { X86_FEATURE_MBA,      CPUID_EBX,  6, 0x80000008, 0 },
0047     { X86_FEATURE_PERFMON_V2,   CPUID_EAX,  0, 0x80000022, 0 },
0048     { 0, 0, 0, 0, 0 }
0049 };
0050
0051 void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
0052 {
0053     u32 max_level;
0054     u32 regs[4];
0055     const struct cpuid_bit *cb;
0056
0057     for (cb = cpuid_bits; cb->feature; cb++) {
0058
0059         /* Verify that the level is valid */
0060         max_level = cpuid_eax(cb->level & 0xffff0000);
0061         if (max_level < cb->level ||
0062             max_level > (cb->level | 0xffff))
0063             continue;
0064
0065         cpuid_count(cb->level, cb->sub_leaf, &regs[CPUID_EAX],
0066                 &regs[CPUID_EBX], &regs[CPUID_ECX],
0067                 &regs[CPUID_EDX]);
0068
0069         if (regs[cb->reg] & (1 << cb->bit))
0070             set_cpu_cap(c, cb->feature);
0071     }
0072 }