cpu/mtrr/amd.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/init.h>
0003 #include <linux/mm.h>
0004 #include <asm/mtrr.h>
0005 #include <asm/msr.h>
0006
0007 #include "mtrr.h"
0008
0009 static void
0010 amd_get_mtrr(unsigned int reg, unsigned long *base,
0011          unsigned long *size, mtrr_type *type)
0012 {
0013     unsigned long low, high;
0014
0015     rdmsr(MSR_K6_UWCCR, low, high);
0016     /* Upper dword is region 1, lower is region 0 */
0017     if (reg == 1)
0018         low = high;
0019     /* The base masks off on the right alignment */
0020     *base = (low & 0xFFFE0000) >> PAGE_SHIFT;
0021     *type = 0;
0022     if (low & 1)
0023         *type = MTRR_TYPE_UNCACHABLE;
0024     if (low & 2)
0025         *type = MTRR_TYPE_WRCOMB;
0026     if (!(low & 3)) {
0027         *size = 0;
0028         return;
0029     }
0030     /*
0031      * This needs a little explaining. The size is stored as an
0032      * inverted mask of bits of 128K granularity 15 bits long offset
0033      * 2 bits.
0034      *
0035      * So to get a size we do invert the mask and add 1 to the lowest
0036      * mask bit (4 as its 2 bits in). This gives us a size we then shift
0037      * to turn into 128K blocks.
0038      *
0039      * eg              111 1111 1111 1100      is 512K
0040      *
0041      * invert          000 0000 0000 0011
0042      * +1              000 0000 0000 0100
0043      * *128K   ...
0044      */
0045     low = (~low) & 0x1FFFC;
0046     *size = (low + 4) << (15 - PAGE_SHIFT);
0047 }
0048
0049 /**
0050  * amd_set_mtrr - Set variable MTRR register on the local CPU.
0051  *
0052  * @reg The register to set.
0053  * @base The base address of the region.
0054  * @size The size of the region. If this is 0 the region is disabled.
0055  * @type The type of the region.
0056  *
0057  * Returns nothing.
0058  */
0059 static void
0060 amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
0061 {
0062     u32 regs[2];
0063
0064     /*
0065      * Low is MTRR0, High MTRR 1
0066      */
0067     rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
0068     /*
0069      * Blank to disable
0070      */
0071     if (size == 0) {
0072         regs[reg] = 0;
0073     } else {
0074         /*
0075          * Set the register to the base, the type (off by one) and an
0076          * inverted bitmask of the size The size is the only odd
0077          * bit. We are fed say 512K We invert this and we get 111 1111
0078          * 1111 1011 but if you subtract one and invert you get the
0079          * desired 111 1111 1111 1100 mask
0080          *
0081          *  But ~(x - 1) == ~x + 1 == -x. Two's complement rocks!
0082          */
0083         regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC)
0084             | (base << PAGE_SHIFT) | (type + 1);
0085     }
0086
0087     /*
0088      * The writeback rule is quite specific. See the manual. Its
0089      * disable local interrupts, write back the cache, set the mtrr
0090      */
0091     wbinvd();
0092     wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
0093 }
0094
0095 static int
0096 amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
0097 {
0098     /*
0099      * Apply the K6 block alignment and size rules
0100      * In order
0101      * o Uncached or gathering only
0102      * o 128K or bigger block
0103      * o Power of 2 block
0104      * o base suitably aligned to the power
0105      */
0106     if (type > MTRR_TYPE_WRCOMB || size < (1 << (17 - PAGE_SHIFT))
0107         || (size & ~(size - 1)) - size || (base & (size - 1)))
0108         return -EINVAL;
0109     return 0;
0110 }
0111
0112 static const struct mtrr_ops amd_mtrr_ops = {
0113     .vendor            = X86_VENDOR_AMD,
0114     .set               = amd_set_mtrr,
0115     .get               = amd_get_mtrr,
0116     .get_free_region   = generic_get_free_region,
0117     .validate_add_page = amd_validate_add_page,
0118     .have_wrcomb       = positive_have_wrcomb,
0119 };
0120
0121 int __init amd_init_mtrr(void)
0122 {
0123     set_mtrr_ops(&amd_mtrr_ops);
0124     return 0;
0125 }