cpu/mce/p5.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * P5 specific Machine Check Exception Reporting
0004  * (C) Copyright 2002 Alan Cox <alan@lxorguk.ukuu.org.uk>
0005  */
0006 #include <linux/interrupt.h>
0007 #include <linux/kernel.h>
0008 #include <linux/types.h>
0009 #include <linux/smp.h>
0010 #include <linux/hardirq.h>
0011
0012 #include <asm/processor.h>
0013 #include <asm/traps.h>
0014 #include <asm/tlbflush.h>
0015 #include <asm/mce.h>
0016 #include <asm/msr.h>
0017
0018 #include "internal.h"
0019
0020 /* By default disabled */
0021 int mce_p5_enabled __read_mostly;
0022
0023 /* Machine check handler for Pentium class Intel CPUs: */
0024 noinstr void pentium_machine_check(struct pt_regs *regs)
0025 {
0026     u32 loaddr, hi, lotype;
0027
0028     instrumentation_begin();
0029     rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
0030     rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
0031
0032     pr_emerg("CPU#%d: Machine Check Exception:  0x%8X (type 0x%8X).\n",
0033          smp_processor_id(), loaddr, lotype);
0034
0035     if (lotype & (1<<5)) {
0036         pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n",
0037              smp_processor_id());
0038     }
0039
0040     add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
0041     instrumentation_end();
0042 }
0043
0044 /* Set up machine check reporting for processors with Intel style MCE: */
0045 void intel_p5_mcheck_init(struct cpuinfo_x86 *c)
0046 {
0047     u32 l, h;
0048
0049     /* Default P5 to off as its often misconnected: */
0050     if (!mce_p5_enabled)
0051         return;
0052
0053     /* Check for MCE support: */
0054     if (!cpu_has(c, X86_FEATURE_MCE))
0055         return;
0056
0057     /* Read registers before enabling: */
0058     rdmsr(MSR_IA32_P5_MC_ADDR, l, h);
0059     rdmsr(MSR_IA32_P5_MC_TYPE, l, h);
0060     pr_info("Intel old style machine check architecture supported.\n");
0061
0062     /* Enable MCE: */
0063     cr4_set_bits(X86_CR4_MCE);
0064     pr_info("Intel old style machine check reporting enabled on CPU#%d.\n",
0065         smp_processor_id());
0066 }