cpu/mce/apei.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Bridge between MCE and APEI
0004  *
0005  * On some machine, corrected memory errors are reported via APEI
0006  * generic hardware error source (GHES) instead of corrected Machine
0007  * Check. These corrected memory errors can be reported to user space
0008  * through /dev/mcelog via faking a corrected Machine Check, so that
0009  * the error memory page can be offlined by /sbin/mcelog if the error
0010  * count for one page is beyond the threshold.
0011  *
0012  * For fatal MCE, save MCE record into persistent storage via ERST, so
0013  * that the MCE record can be logged after reboot via ERST.
0014  *
0015  * Copyright 2010 Intel Corp.
0016  *   Author: Huang Ying <ying.huang@intel.com>
0017  */
0018
0019 #include <linux/export.h>
0020 #include <linux/kernel.h>
0021 #include <linux/acpi.h>
0022 #include <linux/cper.h>
0023 #include <acpi/apei.h>
0024 #include <acpi/ghes.h>
0025 #include <asm/mce.h>
0026
0027 #include "internal.h"
0028
0029 void apei_mce_report_mem_error(int severity, struct cper_sec_mem_err *mem_err)
0030 {
0031     struct mce m;
0032
0033     if (!(mem_err->validation_bits & CPER_MEM_VALID_PA))
0034         return;
0035
0036     mce_setup(&m);
0037     m.bank = -1;
0038     /* Fake a memory read error with unknown channel */
0039     m.status = MCI_STATUS_VAL | MCI_STATUS_EN | MCI_STATUS_ADDRV | MCI_STATUS_MISCV | 0x9f;
0040     m.misc = (MCI_MISC_ADDR_PHYS << 6) | PAGE_SHIFT;
0041
0042     if (severity >= GHES_SEV_RECOVERABLE)
0043         m.status |= MCI_STATUS_UC;
0044
0045     if (severity >= GHES_SEV_PANIC) {
0046         m.status |= MCI_STATUS_PCC;
0047         m.tsc = rdtsc();
0048     }
0049
0050     m.addr = mem_err->physical_addr;
0051     mce_log(&m);
0052 }
0053 EXPORT_SYMBOL_GPL(apei_mce_report_mem_error);
0054
0055 int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info, u64 lapic_id)
0056 {
0057     const u64 *i_mce = ((const u64 *) (ctx_info + 1));
0058     unsigned int cpu;
0059     struct mce m;
0060
0061     if (!boot_cpu_has(X86_FEATURE_SMCA))
0062         return -EINVAL;
0063
0064     /*
0065      * The starting address of the register array extracted from BERT must
0066      * match with the first expected register in the register layout of
0067      * SMCA address space. This address corresponds to banks's MCA_STATUS
0068      * register.
0069      *
0070      * Match any MCi_STATUS register by turning off bank numbers.
0071      */
0072     if ((ctx_info->msr_addr & MSR_AMD64_SMCA_MC0_STATUS) !=
0073                   MSR_AMD64_SMCA_MC0_STATUS)
0074         return -EINVAL;
0075
0076     /*
0077      * The register array size must be large enough to include all the
0078      * SMCA registers which need to be extracted.
0079      *
0080      * The number of registers in the register array is determined by
0081      * Register Array Size/8 as defined in UEFI spec v2.8, sec N.2.4.2.2.
0082      * The register layout is fixed and currently the raw data in the
0083      * register array includes 6 SMCA registers which the kernel can
0084      * extract.
0085      */
0086     if (ctx_info->reg_arr_size < 48)
0087         return -EINVAL;
0088
0089     mce_setup(&m);
0090
0091     m.extcpu = -1;
0092     m.socketid = -1;
0093
0094     for_each_possible_cpu(cpu) {
0095         if (cpu_data(cpu).initial_apicid == lapic_id) {
0096             m.extcpu = cpu;
0097             m.socketid = cpu_data(m.extcpu).phys_proc_id;
0098             break;
0099         }
0100     }
0101
0102     m.apicid = lapic_id;
0103     m.bank = (ctx_info->msr_addr >> 4) & 0xFF;
0104     m.status = *i_mce;
0105     m.addr = *(i_mce + 1);
0106     m.misc = *(i_mce + 2);
0107     /* Skipping MCA_CONFIG */
0108     m.ipid = *(i_mce + 4);
0109     m.synd = *(i_mce + 5);
0110
0111     mce_log(&m);
0112
0113     return 0;
0114 }
0115
0116 #define CPER_CREATOR_MCE                        \
0117     GUID_INIT(0x75a574e3, 0x5052, 0x4b29, 0x8a, 0x8e, 0xbe, 0x2c,   \
0118           0x64, 0x90, 0xb8, 0x9d)
0119 #define CPER_SECTION_TYPE_MCE                       \
0120     GUID_INIT(0xfe08ffbe, 0x95e4, 0x4be7, 0xbc, 0x73, 0x40, 0x96,   \
0121           0x04, 0x4a, 0x38, 0xfc)
0122
0123 /*
0124  * CPER specification (in UEFI specification 2.3 appendix N) requires
0125  * byte-packed.
0126  */
0127 struct cper_mce_record {
0128     struct cper_record_header hdr;
0129     struct cper_section_descriptor sec_hdr;
0130     struct mce mce;
0131 } __packed;
0132
0133 int apei_write_mce(struct mce *m)
0134 {
0135     struct cper_mce_record rcd;
0136
0137     memset(&rcd, 0, sizeof(rcd));
0138     memcpy(rcd.hdr.signature, CPER_SIG_RECORD, CPER_SIG_SIZE);
0139     rcd.hdr.revision = CPER_RECORD_REV;
0140     rcd.hdr.signature_end = CPER_SIG_END;
0141     rcd.hdr.section_count = 1;
0142     rcd.hdr.error_severity = CPER_SEV_FATAL;
0143     /* timestamp, platform_id, partition_id are all invalid */
0144     rcd.hdr.validation_bits = 0;
0145     rcd.hdr.record_length = sizeof(rcd);
0146     rcd.hdr.creator_id = CPER_CREATOR_MCE;
0147     rcd.hdr.notification_type = CPER_NOTIFY_MCE;
0148     rcd.hdr.record_id = cper_next_record_id();
0149     rcd.hdr.flags = CPER_HW_ERROR_FLAGS_PREVERR;
0150
0151     rcd.sec_hdr.section_offset = (void *)&rcd.mce - (void *)&rcd;
0152     rcd.sec_hdr.section_length = sizeof(rcd.mce);
0153     rcd.sec_hdr.revision = CPER_SEC_REV;
0154     /* fru_id and fru_text is invalid */
0155     rcd.sec_hdr.validation_bits = 0;
0156     rcd.sec_hdr.flags = CPER_SEC_PRIMARY;
0157     rcd.sec_hdr.section_type = CPER_SECTION_TYPE_MCE;
0158     rcd.sec_hdr.section_severity = CPER_SEV_FATAL;
0159
0160     memcpy(&rcd.mce, m, sizeof(*m));
0161
0162     return erst_write(&rcd.hdr);
0163 }
0164
0165 ssize_t apei_read_mce(struct mce *m, u64 *record_id)
0166 {
0167     struct cper_mce_record rcd;
0168     int rc, pos;
0169
0170     rc = erst_get_record_id_begin(&pos);
0171     if (rc)
0172         return rc;
0173 retry:
0174     rc = erst_get_record_id_next(&pos, record_id);
0175     if (rc)
0176         goto out;
0177     /* no more record */
0178     if (*record_id == APEI_ERST_INVALID_RECORD_ID)
0179         goto out;
0180     rc = erst_read_record(*record_id, &rcd.hdr, sizeof(rcd), sizeof(rcd),
0181             &CPER_CREATOR_MCE);
0182     /* someone else has cleared the record, try next one */
0183     if (rc == -ENOENT)
0184         goto retry;
0185     else if (rc < 0)
0186         goto out;
0187
0188     memcpy(m, &rcd.mce, sizeof(*m));
0189     rc = sizeof(*m);
0190 out:
0191     erst_get_record_id_end();
0192
0193     return rc;
0194 }
0195
0196 /* Check whether there is record in ERST */
0197 int apei_check_mce(void)
0198 {
0199     return erst_get_record_count();
0200 }
0201
0202 int apei_clear_mce(u64 record_id)
0203 {
0204     return erst_clear(record_id);
0205 }