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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  (c) 2005-2016 Advanced Micro Devices, Inc.
0004  *
0005  *  Written by Jacob Shin - AMD, Inc.
0006  *  Maintained by: Borislav Petkov <bp@alien8.de>
0007  *
0008  *  All MC4_MISCi registers are shared between cores on a node.
0009  */
0010 #include <linux/interrupt.h>
0011 #include <linux/notifier.h>
0012 #include <linux/kobject.h>
0013 #include <linux/percpu.h>
0014 #include <linux/errno.h>
0015 #include <linux/sched.h>
0016 #include <linux/sysfs.h>
0017 #include <linux/slab.h>
0018 #include <linux/init.h>
0019 #include <linux/cpu.h>
0020 #include <linux/smp.h>
0021 #include <linux/string.h>
0022 
0023 #include <asm/amd_nb.h>
0024 #include <asm/traps.h>
0025 #include <asm/apic.h>
0026 #include <asm/mce.h>
0027 #include <asm/msr.h>
0028 #include <asm/trace/irq_vectors.h>
0029 
0030 #include "internal.h"
0031 
0032 #define NR_BLOCKS         5
0033 #define THRESHOLD_MAX     0xFFF
0034 #define INT_TYPE_APIC     0x00020000
0035 #define MASK_VALID_HI     0x80000000
0036 #define MASK_CNTP_HI      0x40000000
0037 #define MASK_LOCKED_HI    0x20000000
0038 #define MASK_LVTOFF_HI    0x00F00000
0039 #define MASK_COUNT_EN_HI  0x00080000
0040 #define MASK_INT_TYPE_HI  0x00060000
0041 #define MASK_OVERFLOW_HI  0x00010000
0042 #define MASK_ERR_COUNT_HI 0x00000FFF
0043 #define MASK_BLKPTR_LO    0xFF000000
0044 #define MCG_XBLK_ADDR     0xC0000400
0045 
0046 /* Deferred error settings */
0047 #define MSR_CU_DEF_ERR      0xC0000410
0048 #define MASK_DEF_LVTOFF     0x000000F0
0049 #define MASK_DEF_INT_TYPE   0x00000006
0050 #define DEF_LVT_OFF     0x2
0051 #define DEF_INT_TYPE_APIC   0x2
0052 
0053 /* Scalable MCA: */
0054 
0055 /* Threshold LVT offset is at MSR0xC0000410[15:12] */
0056 #define SMCA_THR_LVT_OFF    0xF000
0057 
0058 static bool thresholding_irq_en;
0059 
0060 static const char * const th_names[] = {
0061     "load_store",
0062     "insn_fetch",
0063     "combined_unit",
0064     "decode_unit",
0065     "northbridge",
0066     "execution_unit",
0067 };
0068 
0069 static const char * const smca_umc_block_names[] = {
0070     "dram_ecc",
0071     "misc_umc"
0072 };
0073 
0074 #define HWID_MCATYPE(hwid, mcatype) (((hwid) << 16) | (mcatype))
0075 
0076 struct smca_hwid {
0077     unsigned int bank_type; /* Use with smca_bank_types for easy indexing. */
0078     u32 hwid_mcatype;   /* (hwid,mcatype) tuple */
0079 };
0080 
0081 struct smca_bank {
0082     const struct smca_hwid *hwid;
0083     u32 id;         /* Value of MCA_IPID[InstanceId]. */
0084     u8 sysfs_id;        /* Value used for sysfs name. */
0085 };
0086 
0087 static DEFINE_PER_CPU_READ_MOSTLY(struct smca_bank[MAX_NR_BANKS], smca_banks);
0088 static DEFINE_PER_CPU_READ_MOSTLY(u8[N_SMCA_BANK_TYPES], smca_bank_counts);
0089 
0090 struct smca_bank_name {
0091     const char *name;   /* Short name for sysfs */
0092     const char *long_name;  /* Long name for pretty-printing */
0093 };
0094 
0095 static struct smca_bank_name smca_names[] = {
0096     [SMCA_LS ... SMCA_LS_V2]    = { "load_store",   "Load Store Unit" },
0097     [SMCA_IF]           = { "insn_fetch",   "Instruction Fetch Unit" },
0098     [SMCA_L2_CACHE]         = { "l2_cache",     "L2 Cache" },
0099     [SMCA_DE]           = { "decode_unit",  "Decode Unit" },
0100     [SMCA_RESERVED]         = { "reserved",     "Reserved" },
0101     [SMCA_EX]           = { "execution_unit",   "Execution Unit" },
0102     [SMCA_FP]           = { "floating_point",   "Floating Point Unit" },
0103     [SMCA_L3_CACHE]         = { "l3_cache",     "L3 Cache" },
0104     [SMCA_CS ... SMCA_CS_V2]    = { "coherent_slave",   "Coherent Slave" },
0105     [SMCA_PIE]          = { "pie",      "Power, Interrupts, etc." },
0106 
0107     /* UMC v2 is separate because both of them can exist in a single system. */
0108     [SMCA_UMC]          = { "umc",      "Unified Memory Controller" },
0109     [SMCA_UMC_V2]           = { "umc_v2",       "Unified Memory Controller v2" },
0110     [SMCA_PB]           = { "param_block",  "Parameter Block" },
0111     [SMCA_PSP ... SMCA_PSP_V2]  = { "psp",      "Platform Security Processor" },
0112     [SMCA_SMU ... SMCA_SMU_V2]  = { "smu",      "System Management Unit" },
0113     [SMCA_MP5]          = { "mp5",      "Microprocessor 5 Unit" },
0114     [SMCA_MPDMA]            = { "mpdma",        "MPDMA Unit" },
0115     [SMCA_NBIO]         = { "nbio",     "Northbridge IO Unit" },
0116     [SMCA_PCIE ... SMCA_PCIE_V2]    = { "pcie",     "PCI Express Unit" },
0117     [SMCA_XGMI_PCS]         = { "xgmi_pcs",     "Ext Global Memory Interconnect PCS Unit" },
0118     [SMCA_NBIF]         = { "nbif",     "NBIF Unit" },
0119     [SMCA_SHUB]         = { "shub",     "System Hub Unit" },
0120     [SMCA_SATA]         = { "sata",     "SATA Unit" },
0121     [SMCA_USB]          = { "usb",      "USB Unit" },
0122     [SMCA_GMI_PCS]          = { "gmi_pcs",      "Global Memory Interconnect PCS Unit" },
0123     [SMCA_XGMI_PHY]         = { "xgmi_phy",     "Ext Global Memory Interconnect PHY Unit" },
0124     [SMCA_WAFL_PHY]         = { "wafl_phy",     "WAFL PHY Unit" },
0125     [SMCA_GMI_PHY]          = { "gmi_phy",      "Global Memory Interconnect PHY Unit" },
0126 };
0127 
0128 static const char *smca_get_name(enum smca_bank_types t)
0129 {
0130     if (t >= N_SMCA_BANK_TYPES)
0131         return NULL;
0132 
0133     return smca_names[t].name;
0134 }
0135 
0136 const char *smca_get_long_name(enum smca_bank_types t)
0137 {
0138     if (t >= N_SMCA_BANK_TYPES)
0139         return NULL;
0140 
0141     return smca_names[t].long_name;
0142 }
0143 EXPORT_SYMBOL_GPL(smca_get_long_name);
0144 
0145 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank)
0146 {
0147     struct smca_bank *b;
0148 
0149     if (bank >= MAX_NR_BANKS)
0150         return N_SMCA_BANK_TYPES;
0151 
0152     b = &per_cpu(smca_banks, cpu)[bank];
0153     if (!b->hwid)
0154         return N_SMCA_BANK_TYPES;
0155 
0156     return b->hwid->bank_type;
0157 }
0158 EXPORT_SYMBOL_GPL(smca_get_bank_type);
0159 
0160 static const struct smca_hwid smca_hwid_mcatypes[] = {
0161     /* { bank_type, hwid_mcatype } */
0162 
0163     /* Reserved type */
0164     { SMCA_RESERVED, HWID_MCATYPE(0x00, 0x0)    },
0165 
0166     /* ZN Core (HWID=0xB0) MCA types */
0167     { SMCA_LS,   HWID_MCATYPE(0xB0, 0x0)    },
0168     { SMCA_LS_V2,    HWID_MCATYPE(0xB0, 0x10)   },
0169     { SMCA_IF,   HWID_MCATYPE(0xB0, 0x1)    },
0170     { SMCA_L2_CACHE, HWID_MCATYPE(0xB0, 0x2)    },
0171     { SMCA_DE,   HWID_MCATYPE(0xB0, 0x3)    },
0172     /* HWID 0xB0 MCATYPE 0x4 is Reserved */
0173     { SMCA_EX,   HWID_MCATYPE(0xB0, 0x5)    },
0174     { SMCA_FP,   HWID_MCATYPE(0xB0, 0x6)    },
0175     { SMCA_L3_CACHE, HWID_MCATYPE(0xB0, 0x7)    },
0176 
0177     /* Data Fabric MCA types */
0178     { SMCA_CS,   HWID_MCATYPE(0x2E, 0x0)    },
0179     { SMCA_PIE,  HWID_MCATYPE(0x2E, 0x1)    },
0180     { SMCA_CS_V2,    HWID_MCATYPE(0x2E, 0x2)    },
0181 
0182     /* Unified Memory Controller MCA type */
0183     { SMCA_UMC,  HWID_MCATYPE(0x96, 0x0)    },
0184     { SMCA_UMC_V2,   HWID_MCATYPE(0x96, 0x1)    },
0185 
0186     /* Parameter Block MCA type */
0187     { SMCA_PB,   HWID_MCATYPE(0x05, 0x0)    },
0188 
0189     /* Platform Security Processor MCA type */
0190     { SMCA_PSP,  HWID_MCATYPE(0xFF, 0x0)    },
0191     { SMCA_PSP_V2,   HWID_MCATYPE(0xFF, 0x1)    },
0192 
0193     /* System Management Unit MCA type */
0194     { SMCA_SMU,  HWID_MCATYPE(0x01, 0x0)    },
0195     { SMCA_SMU_V2,   HWID_MCATYPE(0x01, 0x1)    },
0196 
0197     /* Microprocessor 5 Unit MCA type */
0198     { SMCA_MP5,  HWID_MCATYPE(0x01, 0x2)    },
0199 
0200     /* MPDMA MCA type */
0201     { SMCA_MPDMA,    HWID_MCATYPE(0x01, 0x3)    },
0202 
0203     /* Northbridge IO Unit MCA type */
0204     { SMCA_NBIO,     HWID_MCATYPE(0x18, 0x0)    },
0205 
0206     /* PCI Express Unit MCA type */
0207     { SMCA_PCIE,     HWID_MCATYPE(0x46, 0x0)    },
0208     { SMCA_PCIE_V2,  HWID_MCATYPE(0x46, 0x1)    },
0209 
0210     { SMCA_XGMI_PCS, HWID_MCATYPE(0x50, 0x0)    },
0211     { SMCA_NBIF,     HWID_MCATYPE(0x6C, 0x0)    },
0212     { SMCA_SHUB,     HWID_MCATYPE(0x80, 0x0)    },
0213     { SMCA_SATA,     HWID_MCATYPE(0xA8, 0x0)    },
0214     { SMCA_USB,  HWID_MCATYPE(0xAA, 0x0)    },
0215     { SMCA_GMI_PCS,  HWID_MCATYPE(0x241, 0x0)   },
0216     { SMCA_XGMI_PHY, HWID_MCATYPE(0x259, 0x0)   },
0217     { SMCA_WAFL_PHY, HWID_MCATYPE(0x267, 0x0)   },
0218     { SMCA_GMI_PHY,  HWID_MCATYPE(0x269, 0x0)   },
0219 };
0220 
0221 /*
0222  * In SMCA enabled processors, we can have multiple banks for a given IP type.
0223  * So to define a unique name for each bank, we use a temp c-string to append
0224  * the MCA_IPID[InstanceId] to type's name in get_name().
0225  *
0226  * InstanceId is 32 bits which is 8 characters. Make sure MAX_MCATYPE_NAME_LEN
0227  * is greater than 8 plus 1 (for underscore) plus length of longest type name.
0228  */
0229 #define MAX_MCATYPE_NAME_LEN    30
0230 static char buf_mcatype[MAX_MCATYPE_NAME_LEN];
0231 
0232 static DEFINE_PER_CPU(struct threshold_bank **, threshold_banks);
0233 
0234 /*
0235  * A list of the banks enabled on each logical CPU. Controls which respective
0236  * descriptors to initialize later in mce_threshold_create_device().
0237  */
0238 static DEFINE_PER_CPU(unsigned int, bank_map);
0239 
0240 /* Map of banks that have more than MCA_MISC0 available. */
0241 static DEFINE_PER_CPU(u32, smca_misc_banks_map);
0242 
0243 static void amd_threshold_interrupt(void);
0244 static void amd_deferred_error_interrupt(void);
0245 
0246 static void default_deferred_error_interrupt(void)
0247 {
0248     pr_err("Unexpected deferred interrupt at vector %x\n", DEFERRED_ERROR_VECTOR);
0249 }
0250 void (*deferred_error_int_vector)(void) = default_deferred_error_interrupt;
0251 
0252 static void smca_set_misc_banks_map(unsigned int bank, unsigned int cpu)
0253 {
0254     u32 low, high;
0255 
0256     /*
0257      * For SMCA enabled processors, BLKPTR field of the first MISC register
0258      * (MCx_MISC0) indicates presence of additional MISC regs set (MISC1-4).
0259      */
0260     if (rdmsr_safe(MSR_AMD64_SMCA_MCx_CONFIG(bank), &low, &high))
0261         return;
0262 
0263     if (!(low & MCI_CONFIG_MCAX))
0264         return;
0265 
0266     if (rdmsr_safe(MSR_AMD64_SMCA_MCx_MISC(bank), &low, &high))
0267         return;
0268 
0269     if (low & MASK_BLKPTR_LO)
0270         per_cpu(smca_misc_banks_map, cpu) |= BIT(bank);
0271 
0272 }
0273 
0274 static void smca_configure(unsigned int bank, unsigned int cpu)
0275 {
0276     u8 *bank_counts = this_cpu_ptr(smca_bank_counts);
0277     const struct smca_hwid *s_hwid;
0278     unsigned int i, hwid_mcatype;
0279     u32 high, low;
0280     u32 smca_config = MSR_AMD64_SMCA_MCx_CONFIG(bank);
0281 
0282     /* Set appropriate bits in MCA_CONFIG */
0283     if (!rdmsr_safe(smca_config, &low, &high)) {
0284         /*
0285          * OS is required to set the MCAX bit to acknowledge that it is
0286          * now using the new MSR ranges and new registers under each
0287          * bank. It also means that the OS will configure deferred
0288          * errors in the new MCx_CONFIG register. If the bit is not set,
0289          * uncorrectable errors will cause a system panic.
0290          *
0291          * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.)
0292          */
0293         high |= BIT(0);
0294 
0295         /*
0296          * SMCA sets the Deferred Error Interrupt type per bank.
0297          *
0298          * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us
0299          * if the DeferredIntType bit field is available.
0300          *
0301          * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the
0302          * high portion of the MSR). OS should set this to 0x1 to enable
0303          * APIC based interrupt. First, check that no interrupt has been
0304          * set.
0305          */
0306         if ((low & BIT(5)) && !((high >> 5) & 0x3))
0307             high |= BIT(5);
0308 
0309         wrmsr(smca_config, low, high);
0310     }
0311 
0312     smca_set_misc_banks_map(bank, cpu);
0313 
0314     if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) {
0315         pr_warn("Failed to read MCA_IPID for bank %d\n", bank);
0316         return;
0317     }
0318 
0319     hwid_mcatype = HWID_MCATYPE(high & MCI_IPID_HWID,
0320                     (high & MCI_IPID_MCATYPE) >> 16);
0321 
0322     for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) {
0323         s_hwid = &smca_hwid_mcatypes[i];
0324 
0325         if (hwid_mcatype == s_hwid->hwid_mcatype) {
0326             this_cpu_ptr(smca_banks)[bank].hwid = s_hwid;
0327             this_cpu_ptr(smca_banks)[bank].id = low;
0328             this_cpu_ptr(smca_banks)[bank].sysfs_id = bank_counts[s_hwid->bank_type]++;
0329             break;
0330         }
0331     }
0332 }
0333 
0334 struct thresh_restart {
0335     struct threshold_block  *b;
0336     int         reset;
0337     int         set_lvt_off;
0338     int         lvt_off;
0339     u16         old_limit;
0340 };
0341 
0342 static inline bool is_shared_bank(int bank)
0343 {
0344     /*
0345      * Scalable MCA provides for only one core to have access to the MSRs of
0346      * a shared bank.
0347      */
0348     if (mce_flags.smca)
0349         return false;
0350 
0351     /* Bank 4 is for northbridge reporting and is thus shared */
0352     return (bank == 4);
0353 }
0354 
0355 static const char *bank4_names(const struct threshold_block *b)
0356 {
0357     switch (b->address) {
0358     /* MSR4_MISC0 */
0359     case 0x00000413:
0360         return "dram";
0361 
0362     case 0xc0000408:
0363         return "ht_links";
0364 
0365     case 0xc0000409:
0366         return "l3_cache";
0367 
0368     default:
0369         WARN(1, "Funny MSR: 0x%08x\n", b->address);
0370         return "";
0371     }
0372 };
0373 
0374 
0375 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
0376 {
0377     /*
0378      * bank 4 supports APIC LVT interrupts implicitly since forever.
0379      */
0380     if (bank == 4)
0381         return true;
0382 
0383     /*
0384      * IntP: interrupt present; if this bit is set, the thresholding
0385      * bank can generate APIC LVT interrupts
0386      */
0387     return msr_high_bits & BIT(28);
0388 }
0389 
0390 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
0391 {
0392     int msr = (hi & MASK_LVTOFF_HI) >> 20;
0393 
0394     if (apic < 0) {
0395         pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
0396                "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
0397                b->bank, b->block, b->address, hi, lo);
0398         return 0;
0399     }
0400 
0401     if (apic != msr) {
0402         /*
0403          * On SMCA CPUs, LVT offset is programmed at a different MSR, and
0404          * the BIOS provides the value. The original field where LVT offset
0405          * was set is reserved. Return early here:
0406          */
0407         if (mce_flags.smca)
0408             return 0;
0409 
0410         pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
0411                "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
0412                b->cpu, apic, b->bank, b->block, b->address, hi, lo);
0413         return 0;
0414     }
0415 
0416     return 1;
0417 };
0418 
0419 /* Reprogram MCx_MISC MSR behind this threshold bank. */
0420 static void threshold_restart_bank(void *_tr)
0421 {
0422     struct thresh_restart *tr = _tr;
0423     u32 hi, lo;
0424 
0425     /* sysfs write might race against an offline operation */
0426     if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off)
0427         return;
0428 
0429     rdmsr(tr->b->address, lo, hi);
0430 
0431     if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
0432         tr->reset = 1;  /* limit cannot be lower than err count */
0433 
0434     if (tr->reset) {        /* reset err count and overflow bit */
0435         hi =
0436             (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
0437             (THRESHOLD_MAX - tr->b->threshold_limit);
0438     } else if (tr->old_limit) { /* change limit w/o reset */
0439         int new_count = (hi & THRESHOLD_MAX) +
0440             (tr->old_limit - tr->b->threshold_limit);
0441 
0442         hi = (hi & ~MASK_ERR_COUNT_HI) |
0443             (new_count & THRESHOLD_MAX);
0444     }
0445 
0446     /* clear IntType */
0447     hi &= ~MASK_INT_TYPE_HI;
0448 
0449     if (!tr->b->interrupt_capable)
0450         goto done;
0451 
0452     if (tr->set_lvt_off) {
0453         if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
0454             /* set new lvt offset */
0455             hi &= ~MASK_LVTOFF_HI;
0456             hi |= tr->lvt_off << 20;
0457         }
0458     }
0459 
0460     if (tr->b->interrupt_enable)
0461         hi |= INT_TYPE_APIC;
0462 
0463  done:
0464 
0465     hi |= MASK_COUNT_EN_HI;
0466     wrmsr(tr->b->address, lo, hi);
0467 }
0468 
0469 static void mce_threshold_block_init(struct threshold_block *b, int offset)
0470 {
0471     struct thresh_restart tr = {
0472         .b          = b,
0473         .set_lvt_off        = 1,
0474         .lvt_off        = offset,
0475     };
0476 
0477     b->threshold_limit      = THRESHOLD_MAX;
0478     threshold_restart_bank(&tr);
0479 };
0480 
0481 static int setup_APIC_mce_threshold(int reserved, int new)
0482 {
0483     if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
0484                           APIC_EILVT_MSG_FIX, 0))
0485         return new;
0486 
0487     return reserved;
0488 }
0489 
0490 static int setup_APIC_deferred_error(int reserved, int new)
0491 {
0492     if (reserved < 0 && !setup_APIC_eilvt(new, DEFERRED_ERROR_VECTOR,
0493                           APIC_EILVT_MSG_FIX, 0))
0494         return new;
0495 
0496     return reserved;
0497 }
0498 
0499 static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
0500 {
0501     u32 low = 0, high = 0;
0502     int def_offset = -1, def_new;
0503 
0504     if (rdmsr_safe(MSR_CU_DEF_ERR, &low, &high))
0505         return;
0506 
0507     def_new = (low & MASK_DEF_LVTOFF) >> 4;
0508     if (!(low & MASK_DEF_LVTOFF)) {
0509         pr_err(FW_BUG "Your BIOS is not setting up LVT offset 0x2 for deferred error IRQs correctly.\n");
0510         def_new = DEF_LVT_OFF;
0511         low = (low & ~MASK_DEF_LVTOFF) | (DEF_LVT_OFF << 4);
0512     }
0513 
0514     def_offset = setup_APIC_deferred_error(def_offset, def_new);
0515     if ((def_offset == def_new) &&
0516         (deferred_error_int_vector != amd_deferred_error_interrupt))
0517         deferred_error_int_vector = amd_deferred_error_interrupt;
0518 
0519     if (!mce_flags.smca)
0520         low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
0521 
0522     wrmsr(MSR_CU_DEF_ERR, low, high);
0523 }
0524 
0525 static u32 smca_get_block_address(unsigned int bank, unsigned int block,
0526                   unsigned int cpu)
0527 {
0528     if (!block)
0529         return MSR_AMD64_SMCA_MCx_MISC(bank);
0530 
0531     if (!(per_cpu(smca_misc_banks_map, cpu) & BIT(bank)))
0532         return 0;
0533 
0534     return MSR_AMD64_SMCA_MCx_MISCy(bank, block - 1);
0535 }
0536 
0537 static u32 get_block_address(u32 current_addr, u32 low, u32 high,
0538                  unsigned int bank, unsigned int block,
0539                  unsigned int cpu)
0540 {
0541     u32 addr = 0, offset = 0;
0542 
0543     if ((bank >= per_cpu(mce_num_banks, cpu)) || (block >= NR_BLOCKS))
0544         return addr;
0545 
0546     if (mce_flags.smca)
0547         return smca_get_block_address(bank, block, cpu);
0548 
0549     /* Fall back to method we used for older processors: */
0550     switch (block) {
0551     case 0:
0552         addr = mca_msr_reg(bank, MCA_MISC);
0553         break;
0554     case 1:
0555         offset = ((low & MASK_BLKPTR_LO) >> 21);
0556         if (offset)
0557             addr = MCG_XBLK_ADDR + offset;
0558         break;
0559     default:
0560         addr = ++current_addr;
0561     }
0562     return addr;
0563 }
0564 
0565 static int
0566 prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr,
0567             int offset, u32 misc_high)
0568 {
0569     unsigned int cpu = smp_processor_id();
0570     u32 smca_low, smca_high;
0571     struct threshold_block b;
0572     int new;
0573 
0574     if (!block)
0575         per_cpu(bank_map, cpu) |= (1 << bank);
0576 
0577     memset(&b, 0, sizeof(b));
0578     b.cpu           = cpu;
0579     b.bank          = bank;
0580     b.block         = block;
0581     b.address       = addr;
0582     b.interrupt_capable = lvt_interrupt_supported(bank, misc_high);
0583 
0584     if (!b.interrupt_capable)
0585         goto done;
0586 
0587     b.interrupt_enable = 1;
0588 
0589     if (!mce_flags.smca) {
0590         new = (misc_high & MASK_LVTOFF_HI) >> 20;
0591         goto set_offset;
0592     }
0593 
0594     /* Gather LVT offset for thresholding: */
0595     if (rdmsr_safe(MSR_CU_DEF_ERR, &smca_low, &smca_high))
0596         goto out;
0597 
0598     new = (smca_low & SMCA_THR_LVT_OFF) >> 12;
0599 
0600 set_offset:
0601     offset = setup_APIC_mce_threshold(offset, new);
0602     if (offset == new)
0603         thresholding_irq_en = true;
0604 
0605 done:
0606     mce_threshold_block_init(&b, offset);
0607 
0608 out:
0609     return offset;
0610 }
0611 
0612 bool amd_filter_mce(struct mce *m)
0613 {
0614     enum smca_bank_types bank_type = smca_get_bank_type(m->extcpu, m->bank);
0615     struct cpuinfo_x86 *c = &boot_cpu_data;
0616 
0617     /* See Family 17h Models 10h-2Fh Erratum #1114. */
0618     if (c->x86 == 0x17 &&
0619         c->x86_model >= 0x10 && c->x86_model <= 0x2F &&
0620         bank_type == SMCA_IF && XEC(m->status, 0x3f) == 10)
0621         return true;
0622 
0623     /* NB GART TLB error reporting is disabled by default. */
0624     if (c->x86 < 0x17) {
0625         if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5)
0626             return true;
0627     }
0628 
0629     return false;
0630 }
0631 
0632 /*
0633  * Turn off thresholding banks for the following conditions:
0634  * - MC4_MISC thresholding is not supported on Family 0x15.
0635  * - Prevent possible spurious interrupts from the IF bank on Family 0x17
0636  *   Models 0x10-0x2F due to Erratum #1114.
0637  */
0638 static void disable_err_thresholding(struct cpuinfo_x86 *c, unsigned int bank)
0639 {
0640     int i, num_msrs;
0641     u64 hwcr;
0642     bool need_toggle;
0643     u32 msrs[NR_BLOCKS];
0644 
0645     if (c->x86 == 0x15 && bank == 4) {
0646         msrs[0] = 0x00000413; /* MC4_MISC0 */
0647         msrs[1] = 0xc0000408; /* MC4_MISC1 */
0648         num_msrs = 2;
0649     } else if (c->x86 == 0x17 &&
0650            (c->x86_model >= 0x10 && c->x86_model <= 0x2F)) {
0651 
0652         if (smca_get_bank_type(smp_processor_id(), bank) != SMCA_IF)
0653             return;
0654 
0655         msrs[0] = MSR_AMD64_SMCA_MCx_MISC(bank);
0656         num_msrs = 1;
0657     } else {
0658         return;
0659     }
0660 
0661     rdmsrl(MSR_K7_HWCR, hwcr);
0662 
0663     /* McStatusWrEn has to be set */
0664     need_toggle = !(hwcr & BIT(18));
0665     if (need_toggle)
0666         wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
0667 
0668     /* Clear CntP bit safely */
0669     for (i = 0; i < num_msrs; i++)
0670         msr_clear_bit(msrs[i], 62);
0671 
0672     /* restore old settings */
0673     if (need_toggle)
0674         wrmsrl(MSR_K7_HWCR, hwcr);
0675 }
0676 
0677 /* cpu init entry point, called from mce.c with preempt off */
0678 void mce_amd_feature_init(struct cpuinfo_x86 *c)
0679 {
0680     unsigned int bank, block, cpu = smp_processor_id();
0681     u32 low = 0, high = 0, address = 0;
0682     int offset = -1;
0683 
0684 
0685     for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
0686         if (mce_flags.smca)
0687             smca_configure(bank, cpu);
0688 
0689         disable_err_thresholding(c, bank);
0690 
0691         for (block = 0; block < NR_BLOCKS; ++block) {
0692             address = get_block_address(address, low, high, bank, block, cpu);
0693             if (!address)
0694                 break;
0695 
0696             if (rdmsr_safe(address, &low, &high))
0697                 break;
0698 
0699             if (!(high & MASK_VALID_HI))
0700                 continue;
0701 
0702             if (!(high & MASK_CNTP_HI)  ||
0703                  (high & MASK_LOCKED_HI))
0704                 continue;
0705 
0706             offset = prepare_threshold_block(bank, block, address, offset, high);
0707         }
0708     }
0709 
0710     if (mce_flags.succor)
0711         deferred_error_interrupt_enable(c);
0712 }
0713 
0714 bool amd_mce_is_memory_error(struct mce *m)
0715 {
0716     /* ErrCodeExt[20:16] */
0717     u8 xec = (m->status >> 16) & 0x1f;
0718 
0719     if (mce_flags.smca)
0720         return smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC && xec == 0x0;
0721 
0722     return m->bank == 4 && xec == 0x8;
0723 }
0724 
0725 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
0726 {
0727     struct mce m;
0728 
0729     mce_setup(&m);
0730 
0731     m.status = status;
0732     m.misc   = misc;
0733     m.bank   = bank;
0734     m.tsc    = rdtsc();
0735 
0736     if (m.status & MCI_STATUS_ADDRV) {
0737         m.addr = addr;
0738 
0739         /*
0740          * Extract [55:<lsb>] where lsb is the least significant
0741          * *valid* bit of the address bits.
0742          */
0743         if (mce_flags.smca) {
0744             u8 lsb = (m.addr >> 56) & 0x3f;
0745 
0746             m.addr &= GENMASK_ULL(55, lsb);
0747         }
0748     }
0749 
0750     if (mce_flags.smca) {
0751         rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), m.ipid);
0752 
0753         if (m.status & MCI_STATUS_SYNDV)
0754             rdmsrl(MSR_AMD64_SMCA_MCx_SYND(bank), m.synd);
0755     }
0756 
0757     mce_log(&m);
0758 }
0759 
0760 DEFINE_IDTENTRY_SYSVEC(sysvec_deferred_error)
0761 {
0762     trace_deferred_error_apic_entry(DEFERRED_ERROR_VECTOR);
0763     inc_irq_stat(irq_deferred_error_count);
0764     deferred_error_int_vector();
0765     trace_deferred_error_apic_exit(DEFERRED_ERROR_VECTOR);
0766     ack_APIC_irq();
0767 }
0768 
0769 /*
0770  * Returns true if the logged error is deferred. False, otherwise.
0771  */
0772 static inline bool
0773 _log_error_bank(unsigned int bank, u32 msr_stat, u32 msr_addr, u64 misc)
0774 {
0775     u64 status, addr = 0;
0776 
0777     rdmsrl(msr_stat, status);
0778     if (!(status & MCI_STATUS_VAL))
0779         return false;
0780 
0781     if (status & MCI_STATUS_ADDRV)
0782         rdmsrl(msr_addr, addr);
0783 
0784     __log_error(bank, status, addr, misc);
0785 
0786     wrmsrl(msr_stat, 0);
0787 
0788     return status & MCI_STATUS_DEFERRED;
0789 }
0790 
0791 /*
0792  * We have three scenarios for checking for Deferred errors:
0793  *
0794  * 1) Non-SMCA systems check MCA_STATUS and log error if found.
0795  * 2) SMCA systems check MCA_STATUS. If error is found then log it and also
0796  *    clear MCA_DESTAT.
0797  * 3) SMCA systems check MCA_DESTAT, if error was not found in MCA_STATUS, and
0798  *    log it.
0799  */
0800 static void log_error_deferred(unsigned int bank)
0801 {
0802     bool defrd;
0803 
0804     defrd = _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS),
0805                 mca_msr_reg(bank, MCA_ADDR), 0);
0806 
0807     if (!mce_flags.smca)
0808         return;
0809 
0810     /* Clear MCA_DESTAT if we logged the deferred error from MCA_STATUS. */
0811     if (defrd) {
0812         wrmsrl(MSR_AMD64_SMCA_MCx_DESTAT(bank), 0);
0813         return;
0814     }
0815 
0816     /*
0817      * Only deferred errors are logged in MCA_DE{STAT,ADDR} so just check
0818      * for a valid error.
0819      */
0820     _log_error_bank(bank, MSR_AMD64_SMCA_MCx_DESTAT(bank),
0821                   MSR_AMD64_SMCA_MCx_DEADDR(bank), 0);
0822 }
0823 
0824 /* APIC interrupt handler for deferred errors */
0825 static void amd_deferred_error_interrupt(void)
0826 {
0827     unsigned int bank;
0828 
0829     for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank)
0830         log_error_deferred(bank);
0831 }
0832 
0833 static void log_error_thresholding(unsigned int bank, u64 misc)
0834 {
0835     _log_error_bank(bank, mca_msr_reg(bank, MCA_STATUS), mca_msr_reg(bank, MCA_ADDR), misc);
0836 }
0837 
0838 static void log_and_reset_block(struct threshold_block *block)
0839 {
0840     struct thresh_restart tr;
0841     u32 low = 0, high = 0;
0842 
0843     if (!block)
0844         return;
0845 
0846     if (rdmsr_safe(block->address, &low, &high))
0847         return;
0848 
0849     if (!(high & MASK_OVERFLOW_HI))
0850         return;
0851 
0852     /* Log the MCE which caused the threshold event. */
0853     log_error_thresholding(block->bank, ((u64)high << 32) | low);
0854 
0855     /* Reset threshold block after logging error. */
0856     memset(&tr, 0, sizeof(tr));
0857     tr.b = block;
0858     threshold_restart_bank(&tr);
0859 }
0860 
0861 /*
0862  * Threshold interrupt handler will service THRESHOLD_APIC_VECTOR. The interrupt
0863  * goes off when error_count reaches threshold_limit.
0864  */
0865 static void amd_threshold_interrupt(void)
0866 {
0867     struct threshold_block *first_block = NULL, *block = NULL, *tmp = NULL;
0868     struct threshold_bank **bp = this_cpu_read(threshold_banks);
0869     unsigned int bank, cpu = smp_processor_id();
0870 
0871     /*
0872      * Validate that the threshold bank has been initialized already. The
0873      * handler is installed at boot time, but on a hotplug event the
0874      * interrupt might fire before the data has been initialized.
0875      */
0876     if (!bp)
0877         return;
0878 
0879     for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
0880         if (!(per_cpu(bank_map, cpu) & (1 << bank)))
0881             continue;
0882 
0883         first_block = bp[bank]->blocks;
0884         if (!first_block)
0885             continue;
0886 
0887         /*
0888          * The first block is also the head of the list. Check it first
0889          * before iterating over the rest.
0890          */
0891         log_and_reset_block(first_block);
0892         list_for_each_entry_safe(block, tmp, &first_block->miscj, miscj)
0893             log_and_reset_block(block);
0894     }
0895 }
0896 
0897 /*
0898  * Sysfs Interface
0899  */
0900 
0901 struct threshold_attr {
0902     struct attribute attr;
0903     ssize_t (*show) (struct threshold_block *, char *);
0904     ssize_t (*store) (struct threshold_block *, const char *, size_t count);
0905 };
0906 
0907 #define SHOW_FIELDS(name)                       \
0908 static ssize_t show_ ## name(struct threshold_block *b, char *buf)  \
0909 {                                   \
0910     return sprintf(buf, "%lu\n", (unsigned long) b->name);      \
0911 }
0912 SHOW_FIELDS(interrupt_enable)
0913 SHOW_FIELDS(threshold_limit)
0914 
0915 static ssize_t
0916 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
0917 {
0918     struct thresh_restart tr;
0919     unsigned long new;
0920 
0921     if (!b->interrupt_capable)
0922         return -EINVAL;
0923 
0924     if (kstrtoul(buf, 0, &new) < 0)
0925         return -EINVAL;
0926 
0927     b->interrupt_enable = !!new;
0928 
0929     memset(&tr, 0, sizeof(tr));
0930     tr.b        = b;
0931 
0932     if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1))
0933         return -ENODEV;
0934 
0935     return size;
0936 }
0937 
0938 static ssize_t
0939 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
0940 {
0941     struct thresh_restart tr;
0942     unsigned long new;
0943 
0944     if (kstrtoul(buf, 0, &new) < 0)
0945         return -EINVAL;
0946 
0947     if (new > THRESHOLD_MAX)
0948         new = THRESHOLD_MAX;
0949     if (new < 1)
0950         new = 1;
0951 
0952     memset(&tr, 0, sizeof(tr));
0953     tr.old_limit = b->threshold_limit;
0954     b->threshold_limit = new;
0955     tr.b = b;
0956 
0957     if (smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1))
0958         return -ENODEV;
0959 
0960     return size;
0961 }
0962 
0963 static ssize_t show_error_count(struct threshold_block *b, char *buf)
0964 {
0965     u32 lo, hi;
0966 
0967     /* CPU might be offline by now */
0968     if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi))
0969         return -ENODEV;
0970 
0971     return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) -
0972                      (THRESHOLD_MAX - b->threshold_limit)));
0973 }
0974 
0975 static struct threshold_attr error_count = {
0976     .attr = {.name = __stringify(error_count), .mode = 0444 },
0977     .show = show_error_count,
0978 };
0979 
0980 #define RW_ATTR(val)                            \
0981 static struct threshold_attr val = {                    \
0982     .attr   = {.name = __stringify(val), .mode = 0644 },        \
0983     .show   = show_## val,                      \
0984     .store  = store_## val,                     \
0985 };
0986 
0987 RW_ATTR(interrupt_enable);
0988 RW_ATTR(threshold_limit);
0989 
0990 static struct attribute *default_attrs[] = {
0991     &threshold_limit.attr,
0992     &error_count.attr,
0993     NULL,   /* possibly interrupt_enable if supported, see below */
0994     NULL,
0995 };
0996 ATTRIBUTE_GROUPS(default);
0997 
0998 #define to_block(k) container_of(k, struct threshold_block, kobj)
0999 #define to_attr(a)  container_of(a, struct threshold_attr, attr)
1000 
1001 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
1002 {
1003     struct threshold_block *b = to_block(kobj);
1004     struct threshold_attr *a = to_attr(attr);
1005     ssize_t ret;
1006 
1007     ret = a->show ? a->show(b, buf) : -EIO;
1008 
1009     return ret;
1010 }
1011 
1012 static ssize_t store(struct kobject *kobj, struct attribute *attr,
1013              const char *buf, size_t count)
1014 {
1015     struct threshold_block *b = to_block(kobj);
1016     struct threshold_attr *a = to_attr(attr);
1017     ssize_t ret;
1018 
1019     ret = a->store ? a->store(b, buf, count) : -EIO;
1020 
1021     return ret;
1022 }
1023 
1024 static const struct sysfs_ops threshold_ops = {
1025     .show           = show,
1026     .store          = store,
1027 };
1028 
1029 static void threshold_block_release(struct kobject *kobj);
1030 
1031 static struct kobj_type threshold_ktype = {
1032     .sysfs_ops      = &threshold_ops,
1033     .default_groups     = default_groups,
1034     .release        = threshold_block_release,
1035 };
1036 
1037 static const char *get_name(unsigned int cpu, unsigned int bank, struct threshold_block *b)
1038 {
1039     enum smca_bank_types bank_type;
1040 
1041     if (!mce_flags.smca) {
1042         if (b && bank == 4)
1043             return bank4_names(b);
1044 
1045         return th_names[bank];
1046     }
1047 
1048     bank_type = smca_get_bank_type(cpu, bank);
1049     if (bank_type >= N_SMCA_BANK_TYPES)
1050         return NULL;
1051 
1052     if (b && bank_type == SMCA_UMC) {
1053         if (b->block < ARRAY_SIZE(smca_umc_block_names))
1054             return smca_umc_block_names[b->block];
1055         return NULL;
1056     }
1057 
1058     if (per_cpu(smca_bank_counts, cpu)[bank_type] == 1)
1059         return smca_get_name(bank_type);
1060 
1061     snprintf(buf_mcatype, MAX_MCATYPE_NAME_LEN,
1062          "%s_%u", smca_get_name(bank_type),
1063               per_cpu(smca_banks, cpu)[bank].sysfs_id);
1064     return buf_mcatype;
1065 }
1066 
1067 static int allocate_threshold_blocks(unsigned int cpu, struct threshold_bank *tb,
1068                      unsigned int bank, unsigned int block,
1069                      u32 address)
1070 {
1071     struct threshold_block *b = NULL;
1072     u32 low, high;
1073     int err;
1074 
1075     if ((bank >= this_cpu_read(mce_num_banks)) || (block >= NR_BLOCKS))
1076         return 0;
1077 
1078     if (rdmsr_safe(address, &low, &high))
1079         return 0;
1080 
1081     if (!(high & MASK_VALID_HI)) {
1082         if (block)
1083             goto recurse;
1084         else
1085             return 0;
1086     }
1087 
1088     if (!(high & MASK_CNTP_HI)  ||
1089          (high & MASK_LOCKED_HI))
1090         goto recurse;
1091 
1092     b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
1093     if (!b)
1094         return -ENOMEM;
1095 
1096     b->block        = block;
1097     b->bank         = bank;
1098     b->cpu          = cpu;
1099     b->address      = address;
1100     b->interrupt_enable = 0;
1101     b->interrupt_capable    = lvt_interrupt_supported(bank, high);
1102     b->threshold_limit  = THRESHOLD_MAX;
1103 
1104     if (b->interrupt_capable) {
1105         default_attrs[2] = &interrupt_enable.attr;
1106         b->interrupt_enable = 1;
1107     } else {
1108         default_attrs[2] = NULL;
1109     }
1110 
1111     INIT_LIST_HEAD(&b->miscj);
1112 
1113     /* This is safe as @tb is not visible yet */
1114     if (tb->blocks)
1115         list_add(&b->miscj, &tb->blocks->miscj);
1116     else
1117         tb->blocks = b;
1118 
1119     err = kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_name(cpu, bank, b));
1120     if (err)
1121         goto out_free;
1122 recurse:
1123     address = get_block_address(address, low, high, bank, ++block, cpu);
1124     if (!address)
1125         return 0;
1126 
1127     err = allocate_threshold_blocks(cpu, tb, bank, block, address);
1128     if (err)
1129         goto out_free;
1130 
1131     if (b)
1132         kobject_uevent(&b->kobj, KOBJ_ADD);
1133 
1134     return 0;
1135 
1136 out_free:
1137     if (b) {
1138         list_del(&b->miscj);
1139         kobject_put(&b->kobj);
1140     }
1141     return err;
1142 }
1143 
1144 static int __threshold_add_blocks(struct threshold_bank *b)
1145 {
1146     struct list_head *head = &b->blocks->miscj;
1147     struct threshold_block *pos = NULL;
1148     struct threshold_block *tmp = NULL;
1149     int err = 0;
1150 
1151     err = kobject_add(&b->blocks->kobj, b->kobj, b->blocks->kobj.name);
1152     if (err)
1153         return err;
1154 
1155     list_for_each_entry_safe(pos, tmp, head, miscj) {
1156 
1157         err = kobject_add(&pos->kobj, b->kobj, pos->kobj.name);
1158         if (err) {
1159             list_for_each_entry_safe_reverse(pos, tmp, head, miscj)
1160                 kobject_del(&pos->kobj);
1161 
1162             return err;
1163         }
1164     }
1165     return err;
1166 }
1167 
1168 static int threshold_create_bank(struct threshold_bank **bp, unsigned int cpu,
1169                  unsigned int bank)
1170 {
1171     struct device *dev = this_cpu_read(mce_device);
1172     struct amd_northbridge *nb = NULL;
1173     struct threshold_bank *b = NULL;
1174     const char *name = get_name(cpu, bank, NULL);
1175     int err = 0;
1176 
1177     if (!dev)
1178         return -ENODEV;
1179 
1180     if (is_shared_bank(bank)) {
1181         nb = node_to_amd_nb(topology_die_id(cpu));
1182 
1183         /* threshold descriptor already initialized on this node? */
1184         if (nb && nb->bank4) {
1185             /* yes, use it */
1186             b = nb->bank4;
1187             err = kobject_add(b->kobj, &dev->kobj, name);
1188             if (err)
1189                 goto out;
1190 
1191             bp[bank] = b;
1192             refcount_inc(&b->cpus);
1193 
1194             err = __threshold_add_blocks(b);
1195 
1196             goto out;
1197         }
1198     }
1199 
1200     b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
1201     if (!b) {
1202         err = -ENOMEM;
1203         goto out;
1204     }
1205 
1206     /* Associate the bank with the per-CPU MCE device */
1207     b->kobj = kobject_create_and_add(name, &dev->kobj);
1208     if (!b->kobj) {
1209         err = -EINVAL;
1210         goto out_free;
1211     }
1212 
1213     if (is_shared_bank(bank)) {
1214         b->shared = 1;
1215         refcount_set(&b->cpus, 1);
1216 
1217         /* nb is already initialized, see above */
1218         if (nb) {
1219             WARN_ON(nb->bank4);
1220             nb->bank4 = b;
1221         }
1222     }
1223 
1224     err = allocate_threshold_blocks(cpu, b, bank, 0, mca_msr_reg(bank, MCA_MISC));
1225     if (err)
1226         goto out_kobj;
1227 
1228     bp[bank] = b;
1229     return 0;
1230 
1231 out_kobj:
1232     kobject_put(b->kobj);
1233 out_free:
1234     kfree(b);
1235 out:
1236     return err;
1237 }
1238 
1239 static void threshold_block_release(struct kobject *kobj)
1240 {
1241     kfree(to_block(kobj));
1242 }
1243 
1244 static void deallocate_threshold_blocks(struct threshold_bank *bank)
1245 {
1246     struct threshold_block *pos, *tmp;
1247 
1248     list_for_each_entry_safe(pos, tmp, &bank->blocks->miscj, miscj) {
1249         list_del(&pos->miscj);
1250         kobject_put(&pos->kobj);
1251     }
1252 
1253     kobject_put(&bank->blocks->kobj);
1254 }
1255 
1256 static void __threshold_remove_blocks(struct threshold_bank *b)
1257 {
1258     struct threshold_block *pos = NULL;
1259     struct threshold_block *tmp = NULL;
1260 
1261     kobject_del(b->kobj);
1262 
1263     list_for_each_entry_safe(pos, tmp, &b->blocks->miscj, miscj)
1264         kobject_del(&pos->kobj);
1265 }
1266 
1267 static void threshold_remove_bank(struct threshold_bank *bank)
1268 {
1269     struct amd_northbridge *nb;
1270 
1271     if (!bank->blocks)
1272         goto out_free;
1273 
1274     if (!bank->shared)
1275         goto out_dealloc;
1276 
1277     if (!refcount_dec_and_test(&bank->cpus)) {
1278         __threshold_remove_blocks(bank);
1279         return;
1280     } else {
1281         /*
1282          * The last CPU on this node using the shared bank is going
1283          * away, remove that bank now.
1284          */
1285         nb = node_to_amd_nb(topology_die_id(smp_processor_id()));
1286         nb->bank4 = NULL;
1287     }
1288 
1289 out_dealloc:
1290     deallocate_threshold_blocks(bank);
1291 
1292 out_free:
1293     kobject_put(bank->kobj);
1294     kfree(bank);
1295 }
1296 
1297 static void __threshold_remove_device(struct threshold_bank **bp)
1298 {
1299     unsigned int bank, numbanks = this_cpu_read(mce_num_banks);
1300 
1301     for (bank = 0; bank < numbanks; bank++) {
1302         if (!bp[bank])
1303             continue;
1304 
1305         threshold_remove_bank(bp[bank]);
1306         bp[bank] = NULL;
1307     }
1308     kfree(bp);
1309 }
1310 
1311 int mce_threshold_remove_device(unsigned int cpu)
1312 {
1313     struct threshold_bank **bp = this_cpu_read(threshold_banks);
1314 
1315     if (!bp)
1316         return 0;
1317 
1318     /*
1319      * Clear the pointer before cleaning up, so that the interrupt won't
1320      * touch anything of this.
1321      */
1322     this_cpu_write(threshold_banks, NULL);
1323 
1324     __threshold_remove_device(bp);
1325     return 0;
1326 }
1327 
1328 /**
1329  * mce_threshold_create_device - Create the per-CPU MCE threshold device
1330  * @cpu:    The plugged in CPU
1331  *
1332  * Create directories and files for all valid threshold banks.
1333  *
1334  * This is invoked from the CPU hotplug callback which was installed in
1335  * mcheck_init_device(). The invocation happens in context of the hotplug
1336  * thread running on @cpu.  The callback is invoked on all CPUs which are
1337  * online when the callback is installed or during a real hotplug event.
1338  */
1339 int mce_threshold_create_device(unsigned int cpu)
1340 {
1341     unsigned int numbanks, bank;
1342     struct threshold_bank **bp;
1343     int err;
1344 
1345     if (!mce_flags.amd_threshold)
1346         return 0;
1347 
1348     bp = this_cpu_read(threshold_banks);
1349     if (bp)
1350         return 0;
1351 
1352     numbanks = this_cpu_read(mce_num_banks);
1353     bp = kcalloc(numbanks, sizeof(*bp), GFP_KERNEL);
1354     if (!bp)
1355         return -ENOMEM;
1356 
1357     for (bank = 0; bank < numbanks; ++bank) {
1358         if (!(this_cpu_read(bank_map) & (1 << bank)))
1359             continue;
1360         err = threshold_create_bank(bp, cpu, bank);
1361         if (err) {
1362             __threshold_remove_device(bp);
1363             return err;
1364         }
1365     }
1366     this_cpu_write(threshold_banks, bp);
1367 
1368     if (thresholding_irq_en)
1369         mce_threshold_vector = amd_threshold_interrupt;
1370     return 0;
1371 }
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