0001
0002
0003
0004
0005
0006
0007 #define COMPILE_OFFSETS
0008
0009 #include <linux/crypto.h>
0010 #include <linux/sched.h>
0011 #include <linux/stddef.h>
0012 #include <linux/hardirq.h>
0013 #include <linux/suspend.h>
0014 #include <linux/kbuild.h>
0015 #include <asm/processor.h>
0016 #include <asm/thread_info.h>
0017 #include <asm/sigframe.h>
0018 #include <asm/bootparam.h>
0019 #include <asm/suspend.h>
0020 #include <asm/tlbflush.h>
0021 #include <asm/tdx.h>
0022 #include "../kvm/vmx/vmx.h"
0023
0024 #ifdef CONFIG_XEN
0025 #include <xen/interface/xen.h>
0026 #endif
0027
0028 #ifdef CONFIG_X86_32
0029 # include "asm-offsets_32.c"
0030 #else
0031 # include "asm-offsets_64.c"
0032 #endif
0033
0034 static void __used common(void)
0035 {
0036 BLANK();
0037 OFFSET(TASK_threadsp, task_struct, thread.sp);
0038 #ifdef CONFIG_STACKPROTECTOR
0039 OFFSET(TASK_stack_canary, task_struct, stack_canary);
0040 #endif
0041
0042 BLANK();
0043 OFFSET(pbe_address, pbe, address);
0044 OFFSET(pbe_orig_address, pbe, orig_address);
0045 OFFSET(pbe_next, pbe, next);
0046
0047 #if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
0048 BLANK();
0049 OFFSET(IA32_SIGCONTEXT_ax, sigcontext_32, ax);
0050 OFFSET(IA32_SIGCONTEXT_bx, sigcontext_32, bx);
0051 OFFSET(IA32_SIGCONTEXT_cx, sigcontext_32, cx);
0052 OFFSET(IA32_SIGCONTEXT_dx, sigcontext_32, dx);
0053 OFFSET(IA32_SIGCONTEXT_si, sigcontext_32, si);
0054 OFFSET(IA32_SIGCONTEXT_di, sigcontext_32, di);
0055 OFFSET(IA32_SIGCONTEXT_bp, sigcontext_32, bp);
0056 OFFSET(IA32_SIGCONTEXT_sp, sigcontext_32, sp);
0057 OFFSET(IA32_SIGCONTEXT_ip, sigcontext_32, ip);
0058
0059 BLANK();
0060 OFFSET(IA32_RT_SIGFRAME_sigcontext, rt_sigframe_ia32, uc.uc_mcontext);
0061 #endif
0062
0063 #ifdef CONFIG_XEN
0064 BLANK();
0065 OFFSET(XEN_vcpu_info_mask, vcpu_info, evtchn_upcall_mask);
0066 OFFSET(XEN_vcpu_info_pending, vcpu_info, evtchn_upcall_pending);
0067 OFFSET(XEN_vcpu_info_arch_cr2, vcpu_info, arch.cr2);
0068 #endif
0069
0070 BLANK();
0071 OFFSET(TDX_MODULE_rcx, tdx_module_output, rcx);
0072 OFFSET(TDX_MODULE_rdx, tdx_module_output, rdx);
0073 OFFSET(TDX_MODULE_r8, tdx_module_output, r8);
0074 OFFSET(TDX_MODULE_r9, tdx_module_output, r9);
0075 OFFSET(TDX_MODULE_r10, tdx_module_output, r10);
0076 OFFSET(TDX_MODULE_r11, tdx_module_output, r11);
0077
0078 BLANK();
0079 OFFSET(TDX_HYPERCALL_r10, tdx_hypercall_args, r10);
0080 OFFSET(TDX_HYPERCALL_r11, tdx_hypercall_args, r11);
0081 OFFSET(TDX_HYPERCALL_r12, tdx_hypercall_args, r12);
0082 OFFSET(TDX_HYPERCALL_r13, tdx_hypercall_args, r13);
0083 OFFSET(TDX_HYPERCALL_r14, tdx_hypercall_args, r14);
0084 OFFSET(TDX_HYPERCALL_r15, tdx_hypercall_args, r15);
0085
0086 BLANK();
0087 OFFSET(BP_scratch, boot_params, scratch);
0088 OFFSET(BP_secure_boot, boot_params, secure_boot);
0089 OFFSET(BP_loadflags, boot_params, hdr.loadflags);
0090 OFFSET(BP_hardware_subarch, boot_params, hdr.hardware_subarch);
0091 OFFSET(BP_version, boot_params, hdr.version);
0092 OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment);
0093 OFFSET(BP_init_size, boot_params, hdr.init_size);
0094 OFFSET(BP_pref_address, boot_params, hdr.pref_address);
0095
0096 BLANK();
0097 DEFINE(PTREGS_SIZE, sizeof(struct pt_regs));
0098
0099
0100 OFFSET(TLB_STATE_user_pcid_flush_mask, tlb_state, user_pcid_flush_mask);
0101
0102
0103 OFFSET(CPU_ENTRY_AREA_entry_stack, cpu_entry_area, entry_stack_page);
0104 DEFINE(SIZEOF_entry_stack, sizeof(struct entry_stack));
0105 DEFINE(MASK_entry_stack, (~(sizeof(struct entry_stack) - 1)));
0106
0107
0108 OFFSET(TSS_sp0, tss_struct, x86_tss.sp0);
0109 OFFSET(TSS_sp1, tss_struct, x86_tss.sp1);
0110 OFFSET(TSS_sp2, tss_struct, x86_tss.sp2);
0111
0112 if (IS_ENABLED(CONFIG_KVM_INTEL)) {
0113 BLANK();
0114 OFFSET(VMX_spec_ctrl, vcpu_vmx, spec_ctrl);
0115 }
0116 }