Back to home page

OSCL-LXR
 
 

     

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * SGI UV APIC functions (note: not an Intel compatible APIC)
0007  *
0008  * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
0009  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
0010  */
0011 #include <linux/crash_dump.h>
0012 #include <linux/cpuhotplug.h>
0013 #include <linux/cpumask.h>
0014 #include <linux/proc_fs.h>
0015 #include <linux/memory.h>
0016 #include <linux/export.h>
0017 #include <linux/pci.h>
0018 #include <linux/acpi.h>
0019 #include <linux/efi.h>
0020 
0021 #include <asm/e820/api.h>
0022 #include <asm/uv/uv_mmrs.h>
0023 #include <asm/uv/uv_hub.h>
0024 #include <asm/uv/bios.h>
0025 #include <asm/uv/uv.h>
0026 #include <asm/apic.h>
0027 
0028 static enum uv_system_type  uv_system_type;
0029 static int          uv_hubbed_system;
0030 static int          uv_hubless_system;
0031 static u64          gru_start_paddr, gru_end_paddr;
0032 static union uvh_apicid     uvh_apicid;
0033 static int          uv_node_id;
0034 
0035 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */
0036 static u8 uv_archtype[UV_AT_SIZE + 1];
0037 static u8 oem_id[ACPI_OEM_ID_SIZE + 1];
0038 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
0039 
0040 /* Information derived from CPUID and some UV MMRs */
0041 static struct {
0042     unsigned int apicid_shift;
0043     unsigned int apicid_mask;
0044     unsigned int socketid_shift;    /* aka pnode_shift for UV2/3 */
0045     unsigned int pnode_mask;
0046     unsigned int nasid_shift;
0047     unsigned int gpa_shift;
0048     unsigned int gnode_shift;
0049     unsigned int m_skt;
0050     unsigned int n_skt;
0051 } uv_cpuid;
0052 
0053 static int uv_min_hub_revision_id;
0054 
0055 static struct apic apic_x2apic_uv_x;
0056 static struct uv_hub_info_s uv_hub_info_node0;
0057 
0058 /* Set this to use hardware error handler instead of kernel panic: */
0059 static int disable_uv_undefined_panic = 1;
0060 
0061 unsigned long uv_undefined(char *str)
0062 {
0063     if (likely(!disable_uv_undefined_panic))
0064         panic("UV: error: undefined MMR: %s\n", str);
0065     else
0066         pr_crit("UV: error: undefined MMR: %s\n", str);
0067 
0068     /* Cause a machine fault: */
0069     return ~0ul;
0070 }
0071 EXPORT_SYMBOL(uv_undefined);
0072 
0073 static unsigned long __init uv_early_read_mmr(unsigned long addr)
0074 {
0075     unsigned long val, *mmr;
0076 
0077     mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
0078     val = *mmr;
0079     early_iounmap(mmr, sizeof(*mmr));
0080 
0081     return val;
0082 }
0083 
0084 static inline bool is_GRU_range(u64 start, u64 end)
0085 {
0086     if (!gru_start_paddr)
0087         return false;
0088 
0089     return start >= gru_start_paddr && end <= gru_end_paddr;
0090 }
0091 
0092 static bool uv_is_untracked_pat_range(u64 start, u64 end)
0093 {
0094     return is_ISA_range(start, end) || is_GRU_range(start, end);
0095 }
0096 
0097 static void __init early_get_pnodeid(void)
0098 {
0099     int pnode;
0100 
0101     uv_cpuid.m_skt = 0;
0102     if (UVH_RH10_GAM_ADDR_MAP_CONFIG) {
0103         union uvh_rh10_gam_addr_map_config_u  m_n_config;
0104 
0105         m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG);
0106         uv_cpuid.n_skt = m_n_config.s.n_skt;
0107         uv_cpuid.nasid_shift = 0;
0108     } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) {
0109         union uvh_rh_gam_addr_map_config_u  m_n_config;
0110 
0111     m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG);
0112         uv_cpuid.n_skt = m_n_config.s.n_skt;
0113         if (is_uv(UV3))
0114             uv_cpuid.m_skt = m_n_config.s3.m_skt;
0115         if (is_uv(UV2))
0116             uv_cpuid.m_skt = m_n_config.s2.m_skt;
0117         uv_cpuid.nasid_shift = 1;
0118     } else {
0119         unsigned long GAM_ADDR_MAP_CONFIG = 0;
0120 
0121         WARN(GAM_ADDR_MAP_CONFIG == 0,
0122             "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n");
0123         uv_cpuid.n_skt = 0;
0124         uv_cpuid.nasid_shift = 0;
0125     }
0126 
0127     if (is_uv(UV4|UVY))
0128         uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */
0129 
0130     uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1;
0131     pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask;
0132     uv_cpuid.gpa_shift = 46;    /* Default unless changed */
0133 
0134     pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n",
0135         uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode);
0136 }
0137 
0138 /* Running on a UV Hubbed system, determine which UV Hub Type it is */
0139 static int __init early_set_hub_type(void)
0140 {
0141     union uvh_node_id_u node_id;
0142 
0143     /*
0144      * The NODE_ID MMR is always at offset 0.
0145      * Contains the chip part # + revision.
0146      * Node_id field started with 15 bits,
0147      * ... now 7 but upper 8 are masked to 0.
0148      * All blades/nodes have the same part # and hub revision.
0149      */
0150     node_id.v = uv_early_read_mmr(UVH_NODE_ID);
0151     uv_node_id = node_id.sx.node_id;
0152 
0153     switch (node_id.s.part_number) {
0154 
0155     case UV5_HUB_PART_NUMBER:
0156         uv_min_hub_revision_id = node_id.s.revision
0157                      + UV5_HUB_REVISION_BASE;
0158         uv_hub_type_set(UV5);
0159         break;
0160 
0161     /* UV4/4A only have a revision difference */
0162     case UV4_HUB_PART_NUMBER:
0163         uv_min_hub_revision_id = node_id.s.revision
0164                      + UV4_HUB_REVISION_BASE - 1;
0165         uv_hub_type_set(UV4);
0166         if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE)
0167             uv_hub_type_set(UV4|UV4A);
0168         break;
0169 
0170     case UV3_HUB_PART_NUMBER:
0171     case UV3_HUB_PART_NUMBER_X:
0172         uv_min_hub_revision_id = node_id.s.revision
0173                      + UV3_HUB_REVISION_BASE;
0174         uv_hub_type_set(UV3);
0175         break;
0176 
0177     case UV2_HUB_PART_NUMBER:
0178     case UV2_HUB_PART_NUMBER_X:
0179         uv_min_hub_revision_id = node_id.s.revision
0180                      + UV2_HUB_REVISION_BASE - 1;
0181         uv_hub_type_set(UV2);
0182         break;
0183 
0184     default:
0185         return 0;
0186     }
0187 
0188     pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n",
0189         node_id.s.part_number, node_id.s.revision,
0190         uv_min_hub_revision_id, is_uv(~0));
0191 
0192     return 1;
0193 }
0194 
0195 static void __init uv_tsc_check_sync(void)
0196 {
0197     u64 mmr;
0198     int sync_state;
0199     int mmr_shift;
0200     char *state;
0201 
0202     /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */
0203     if (!is_uv(UV2|UV3|UV4)) {
0204         mark_tsc_async_resets("UV5+");
0205         return;
0206     }
0207 
0208     /* UV2,3,4, UV BIOS TSC sync state available */
0209     mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR);
0210     mmr_shift =
0211         is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT;
0212     sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK;
0213 
0214     /* Check if TSC is valid for all sockets */
0215     switch (sync_state) {
0216     case UVH_TSC_SYNC_VALID:
0217         state = "in sync";
0218         mark_tsc_async_resets("UV BIOS");
0219         break;
0220 
0221     /* If BIOS state unknown, don't do anything */
0222     case UVH_TSC_SYNC_UNKNOWN:
0223         state = "unknown";
0224         break;
0225 
0226     /* Otherwise, BIOS indicates problem with TSC */
0227     default:
0228         state = "unstable";
0229         mark_tsc_unstable("UV BIOS");
0230         break;
0231     }
0232     pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state);
0233 }
0234 
0235 /* Selector for (4|4A|5) structs */
0236 #define uvxy_field(sname, field, undef) (   \
0237     is_uv(UV4A) ? sname.s4a.field :     \
0238     is_uv(UV4) ? sname.s4.field :       \
0239     is_uv(UV3) ? sname.s3.field :       \
0240     undef)
0241 
0242 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
0243 
0244 #define SMT_LEVEL           0   /* Leaf 0xb SMT level */
0245 #define INVALID_TYPE            0   /* Leaf 0xb sub-leaf types */
0246 #define SMT_TYPE            1
0247 #define CORE_TYPE           2
0248 #define LEAFB_SUBTYPE(ecx)      (((ecx) >> 8) & 0xff)
0249 #define BITS_SHIFT_NEXT_LEVEL(eax)  ((eax) & 0x1f)
0250 
0251 static void set_x2apic_bits(void)
0252 {
0253     unsigned int eax, ebx, ecx, edx, sub_index;
0254     unsigned int sid_shift;
0255 
0256     cpuid(0, &eax, &ebx, &ecx, &edx);
0257     if (eax < 0xb) {
0258         pr_info("UV: CPU does not have CPUID.11\n");
0259         return;
0260     }
0261 
0262     cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
0263     if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
0264         pr_info("UV: CPUID.11 not implemented\n");
0265         return;
0266     }
0267 
0268     sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
0269     sub_index = 1;
0270     do {
0271         cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
0272         if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
0273             sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
0274             break;
0275         }
0276         sub_index++;
0277     } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
0278 
0279     uv_cpuid.apicid_shift   = 0;
0280     uv_cpuid.apicid_mask    = (~(-1 << sid_shift));
0281     uv_cpuid.socketid_shift = sid_shift;
0282 }
0283 
0284 static void __init early_get_apic_socketid_shift(void)
0285 {
0286     if (is_uv2_hub() || is_uv3_hub())
0287         uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
0288 
0289     set_x2apic_bits();
0290 
0291     pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
0292     pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
0293 }
0294 
0295 static void __init uv_stringify(int len, char *to, char *from)
0296 {
0297     /* Relies on 'to' being NULL chars so result will be NULL terminated */
0298     strncpy(to, from, len-1);
0299 
0300     /* Trim trailing spaces */
0301     (void)strim(to);
0302 }
0303 
0304 /* Find UV arch type entry in UVsystab */
0305 static unsigned long __init early_find_archtype(struct uv_systab *st)
0306 {
0307     int i;
0308 
0309     for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
0310         unsigned long ptr = st->entry[i].offset;
0311 
0312         if (!ptr)
0313             continue;
0314         ptr += (unsigned long)st;
0315         if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE)
0316             return ptr;
0317     }
0318     return 0;
0319 }
0320 
0321 /* Validate UV arch type field in UVsystab */
0322 static int __init decode_arch_type(unsigned long ptr)
0323 {
0324     struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr;
0325     int n = strlen(uv_ate->archtype);
0326 
0327     if (n > 0 && n < sizeof(uv_ate->archtype)) {
0328         pr_info("UV: UVarchtype received from BIOS\n");
0329         uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype);
0330         return 1;
0331     }
0332     return 0;
0333 }
0334 
0335 /* Determine if UV arch type entry might exist in UVsystab */
0336 static int __init early_get_arch_type(void)
0337 {
0338     unsigned long uvst_physaddr, uvst_size, ptr;
0339     struct uv_systab *st;
0340     u32 rev;
0341     int ret;
0342 
0343     uvst_physaddr = get_uv_systab_phys(0);
0344     if (!uvst_physaddr)
0345         return 0;
0346 
0347     st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab));
0348     if (!st) {
0349         pr_err("UV: Cannot access UVsystab, remap failed\n");
0350         return 0;
0351     }
0352 
0353     rev = st->revision;
0354     if (rev < UV_SYSTAB_VERSION_UV5) {
0355         early_memunmap(st, sizeof(struct uv_systab));
0356         return 0;
0357     }
0358 
0359     uvst_size = st->size;
0360     early_memunmap(st, sizeof(struct uv_systab));
0361     st = early_memremap_ro(uvst_physaddr, uvst_size);
0362     if (!st) {
0363         pr_err("UV: Cannot access UVarchtype, remap failed\n");
0364         return 0;
0365     }
0366 
0367     ptr = early_find_archtype(st);
0368     if (!ptr) {
0369         early_memunmap(st, uvst_size);
0370         return 0;
0371     }
0372 
0373     ret = decode_arch_type(ptr);
0374     early_memunmap(st, uvst_size);
0375     return ret;
0376 }
0377 
0378 /* UV system found, check which APIC MODE BIOS already selected */
0379 static void __init early_set_apic_mode(void)
0380 {
0381     if (x2apic_enabled())
0382         uv_system_type = UV_X2APIC;
0383     else
0384         uv_system_type = UV_LEGACY_APIC;
0385 }
0386 
0387 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id)
0388 {
0389     /* Save OEM_ID passed from ACPI MADT */
0390     uv_stringify(sizeof(oem_id), oem_id, _oem_id);
0391 
0392     /* Check if BIOS sent us a UVarchtype */
0393     if (!early_get_arch_type())
0394 
0395         /* If not use OEM ID for UVarchtype */
0396         uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id);
0397 
0398     /* Check if not hubbed */
0399     if (strncmp(uv_archtype, "SGI", 3) != 0) {
0400 
0401         /* (Not hubbed), check if not hubless */
0402         if (strncmp(uv_archtype, "NSGI", 4) != 0)
0403 
0404             /* (Not hubless), not a UV */
0405             return 0;
0406 
0407         /* Is UV hubless system */
0408         uv_hubless_system = 0x01;
0409 
0410         /* UV5 Hubless */
0411         if (strncmp(uv_archtype, "NSGI5", 5) == 0)
0412             uv_hubless_system |= 0x20;
0413 
0414         /* UV4 Hubless: CH */
0415         else if (strncmp(uv_archtype, "NSGI4", 5) == 0)
0416             uv_hubless_system |= 0x10;
0417 
0418         /* UV3 Hubless: UV300/MC990X w/o hub */
0419         else
0420             uv_hubless_system |= 0x8;
0421 
0422         /* Copy OEM Table ID */
0423         uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
0424 
0425         pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n",
0426             oem_id, oem_table_id, uv_system_type, uv_hubless_system);
0427 
0428         return 0;
0429     }
0430 
0431     if (numa_off) {
0432         pr_err("UV: NUMA is off, disabling UV support\n");
0433         return 0;
0434     }
0435 
0436     /* Set hubbed type if true */
0437     uv_hub_info->hub_revision =
0438         !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE :
0439         !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
0440         !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
0441         !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0;
0442 
0443     switch (uv_hub_info->hub_revision) {
0444     case UV5_HUB_REVISION_BASE:
0445         uv_hubbed_system = 0x21;
0446         uv_hub_type_set(UV5);
0447         break;
0448 
0449     case UV4_HUB_REVISION_BASE:
0450         uv_hubbed_system = 0x11;
0451         uv_hub_type_set(UV4);
0452         break;
0453 
0454     case UV3_HUB_REVISION_BASE:
0455         uv_hubbed_system = 0x9;
0456         uv_hub_type_set(UV3);
0457         break;
0458 
0459     case UV2_HUB_REVISION_BASE:
0460         uv_hubbed_system = 0x5;
0461         uv_hub_type_set(UV2);
0462         break;
0463 
0464     default:
0465         return 0;
0466     }
0467 
0468     /* Get UV hub chip part number & revision */
0469     early_set_hub_type();
0470 
0471     /* Other UV setup functions */
0472     early_set_apic_mode();
0473     early_get_pnodeid();
0474     early_get_apic_socketid_shift();
0475     x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
0476     x86_platform.nmi_init = uv_nmi_init;
0477     uv_tsc_check_sync();
0478 
0479     return 1;
0480 }
0481 
0482 /* Called early to probe for the correct APIC driver */
0483 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id)
0484 {
0485     /* Set up early hub info fields for Node 0 */
0486     uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
0487 
0488     /* If not UV, return. */
0489     if (uv_set_system_type(_oem_id, _oem_table_id) == 0)
0490         return 0;
0491 
0492     /* Save for display of the OEM Table ID */
0493     uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id);
0494 
0495     pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n",
0496         oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY),
0497         uv_min_hub_revision_id);
0498 
0499     return 0;
0500 }
0501 
0502 enum uv_system_type get_uv_system_type(void)
0503 {
0504     return uv_system_type;
0505 }
0506 
0507 int uv_get_hubless_system(void)
0508 {
0509     return uv_hubless_system;
0510 }
0511 EXPORT_SYMBOL_GPL(uv_get_hubless_system);
0512 
0513 ssize_t uv_get_archtype(char *buf, int len)
0514 {
0515     return scnprintf(buf, len, "%s/%s", uv_archtype, oem_table_id);
0516 }
0517 EXPORT_SYMBOL_GPL(uv_get_archtype);
0518 
0519 int is_uv_system(void)
0520 {
0521     return uv_system_type != UV_NONE;
0522 }
0523 EXPORT_SYMBOL_GPL(is_uv_system);
0524 
0525 int is_uv_hubbed(int uvtype)
0526 {
0527     return (uv_hubbed_system & uvtype);
0528 }
0529 EXPORT_SYMBOL_GPL(is_uv_hubbed);
0530 
0531 static int is_uv_hubless(int uvtype)
0532 {
0533     return (uv_hubless_system & uvtype);
0534 }
0535 
0536 void **__uv_hub_info_list;
0537 EXPORT_SYMBOL_GPL(__uv_hub_info_list);
0538 
0539 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
0540 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
0541 
0542 short uv_possible_blades;
0543 EXPORT_SYMBOL_GPL(uv_possible_blades);
0544 
0545 unsigned long sn_rtc_cycles_per_second;
0546 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
0547 
0548 /* The following values are used for the per node hub info struct */
0549 static __initdata unsigned short        *_node_to_pnode;
0550 static __initdata unsigned short        _min_socket, _max_socket;
0551 static __initdata unsigned short        _min_pnode, _max_pnode, _gr_table_len;
0552 static __initdata struct uv_gam_range_entry *uv_gre_table;
0553 static __initdata struct uv_gam_parameters  *uv_gp_table;
0554 static __initdata unsigned short        *_socket_to_node;
0555 static __initdata unsigned short        *_socket_to_pnode;
0556 static __initdata unsigned short        *_pnode_to_socket;
0557 
0558 static __initdata struct uv_gam_range_s     *_gr_table;
0559 
0560 #define SOCK_EMPTY  ((unsigned short)~0)
0561 
0562 /* Default UV memory block size is 2GB */
0563 static unsigned long mem_block_size __initdata = (2UL << 30);
0564 
0565 /* Kernel parameter to specify UV mem block size */
0566 static int __init parse_mem_block_size(char *ptr)
0567 {
0568     unsigned long size = memparse(ptr, NULL);
0569 
0570     /* Size will be rounded down by set_block_size() below */
0571     mem_block_size = size;
0572     return 0;
0573 }
0574 early_param("uv_memblksize", parse_mem_block_size);
0575 
0576 static __init int adj_blksize(u32 lgre)
0577 {
0578     unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT;
0579     unsigned long size;
0580 
0581     for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1)
0582         if (IS_ALIGNED(base, size))
0583             break;
0584 
0585     if (size >= mem_block_size)
0586         return 0;
0587 
0588     mem_block_size = size;
0589     return 1;
0590 }
0591 
0592 static __init void set_block_size(void)
0593 {
0594     unsigned int order = ffs(mem_block_size);
0595 
0596     if (order) {
0597         /* adjust for ffs return of 1..64 */
0598         set_memory_block_size_order(order - 1);
0599         pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size);
0600     } else {
0601         /* bad or zero value, default to 1UL << 31 (2GB) */
0602         pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size);
0603         set_memory_block_size_order(31);
0604     }
0605 }
0606 
0607 /* Build GAM range lookup table: */
0608 static __init void build_uv_gr_table(void)
0609 {
0610     struct uv_gam_range_entry *gre = uv_gre_table;
0611     struct uv_gam_range_s *grt;
0612     unsigned long last_limit = 0, ram_limit = 0;
0613     int bytes, i, sid, lsid = -1, indx = 0, lindx = -1;
0614 
0615     if (!gre)
0616         return;
0617 
0618     bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
0619     grt = kzalloc(bytes, GFP_KERNEL);
0620     BUG_ON(!grt);
0621     _gr_table = grt;
0622 
0623     for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
0624         if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
0625             if (!ram_limit) {
0626                 /* Mark hole between RAM/non-RAM: */
0627                 ram_limit = last_limit;
0628                 last_limit = gre->limit;
0629                 lsid++;
0630                 continue;
0631             }
0632             last_limit = gre->limit;
0633             pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table));
0634             continue;
0635         }
0636         if (_max_socket < gre->sockid) {
0637             pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table));
0638             continue;
0639         }
0640         sid = gre->sockid - _min_socket;
0641         if (lsid < sid) {
0642             /* New range: */
0643             grt = &_gr_table[indx];
0644             grt->base = lindx;
0645             grt->nasid = gre->nasid;
0646             grt->limit = last_limit = gre->limit;
0647             lsid = sid;
0648             lindx = indx++;
0649             continue;
0650         }
0651         /* Update range: */
0652         if (lsid == sid && !ram_limit) {
0653             /* .. if contiguous: */
0654             if (grt->limit == last_limit) {
0655                 grt->limit = last_limit = gre->limit;
0656                 continue;
0657             }
0658         }
0659         /* Non-contiguous RAM range: */
0660         if (!ram_limit) {
0661             grt++;
0662             grt->base = lindx;
0663             grt->nasid = gre->nasid;
0664             grt->limit = last_limit = gre->limit;
0665             continue;
0666         }
0667         /* Non-contiguous/non-RAM: */
0668         grt++;
0669         /* base is this entry */
0670         grt->base = grt - _gr_table;
0671         grt->nasid = gre->nasid;
0672         grt->limit = last_limit = gre->limit;
0673         lsid++;
0674     }
0675 
0676     /* Shorten table if possible */
0677     grt++;
0678     i = grt - _gr_table;
0679     if (i < _gr_table_len) {
0680         void *ret;
0681 
0682         bytes = i * sizeof(struct uv_gam_range_s);
0683         ret = krealloc(_gr_table, bytes, GFP_KERNEL);
0684         if (ret) {
0685             _gr_table = ret;
0686             _gr_table_len = i;
0687         }
0688     }
0689 
0690     /* Display resultant GAM range table: */
0691     for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
0692         unsigned long start, end;
0693         int gb = grt->base;
0694 
0695         start = gb < 0 ?  0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
0696         end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
0697 
0698         pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb);
0699     }
0700 }
0701 
0702 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
0703 {
0704     unsigned long val;
0705     int pnode;
0706 
0707     pnode = uv_apicid_to_pnode(phys_apicid);
0708 
0709     val = (1UL << UVH_IPI_INT_SEND_SHFT) |
0710         (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
0711         ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
0712         APIC_DM_INIT;
0713 
0714     uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
0715 
0716     val = (1UL << UVH_IPI_INT_SEND_SHFT) |
0717         (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
0718         ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
0719         APIC_DM_STARTUP;
0720 
0721     uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
0722 
0723     return 0;
0724 }
0725 
0726 static void uv_send_IPI_one(int cpu, int vector)
0727 {
0728     unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu);
0729     int pnode = uv_apicid_to_pnode(apicid);
0730     unsigned long dmode, val;
0731 
0732     if (vector == NMI_VECTOR)
0733         dmode = APIC_DELIVERY_MODE_NMI;
0734     else
0735         dmode = APIC_DELIVERY_MODE_FIXED;
0736 
0737     val = (1UL << UVH_IPI_INT_SEND_SHFT) |
0738         (apicid << UVH_IPI_INT_APIC_ID_SHFT) |
0739         (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) |
0740         (vector << UVH_IPI_INT_VECTOR_SHFT);
0741 
0742     uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
0743 }
0744 
0745 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
0746 {
0747     unsigned int cpu;
0748 
0749     for_each_cpu(cpu, mask)
0750         uv_send_IPI_one(cpu, vector);
0751 }
0752 
0753 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
0754 {
0755     unsigned int this_cpu = smp_processor_id();
0756     unsigned int cpu;
0757 
0758     for_each_cpu(cpu, mask) {
0759         if (cpu != this_cpu)
0760             uv_send_IPI_one(cpu, vector);
0761     }
0762 }
0763 
0764 static void uv_send_IPI_allbutself(int vector)
0765 {
0766     unsigned int this_cpu = smp_processor_id();
0767     unsigned int cpu;
0768 
0769     for_each_online_cpu(cpu) {
0770         if (cpu != this_cpu)
0771             uv_send_IPI_one(cpu, vector);
0772     }
0773 }
0774 
0775 static void uv_send_IPI_all(int vector)
0776 {
0777     uv_send_IPI_mask(cpu_online_mask, vector);
0778 }
0779 
0780 static int uv_apic_id_valid(u32 apicid)
0781 {
0782     return 1;
0783 }
0784 
0785 static int uv_apic_id_registered(void)
0786 {
0787     return 1;
0788 }
0789 
0790 static void uv_init_apic_ldr(void)
0791 {
0792 }
0793 
0794 static u32 apic_uv_calc_apicid(unsigned int cpu)
0795 {
0796     return apic_default_calc_apicid(cpu);
0797 }
0798 
0799 static unsigned int x2apic_get_apic_id(unsigned long id)
0800 {
0801     return id;
0802 }
0803 
0804 static u32 set_apic_id(unsigned int id)
0805 {
0806     return id;
0807 }
0808 
0809 static unsigned int uv_read_apic_id(void)
0810 {
0811     return x2apic_get_apic_id(apic_read(APIC_ID));
0812 }
0813 
0814 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
0815 {
0816     return uv_read_apic_id() >> index_msb;
0817 }
0818 
0819 static void uv_send_IPI_self(int vector)
0820 {
0821     apic_write(APIC_SELF_IPI, vector);
0822 }
0823 
0824 static int uv_probe(void)
0825 {
0826     return apic == &apic_x2apic_uv_x;
0827 }
0828 
0829 static struct apic apic_x2apic_uv_x __ro_after_init = {
0830 
0831     .name               = "UV large system",
0832     .probe              = uv_probe,
0833     .acpi_madt_oem_check        = uv_acpi_madt_oem_check,
0834     .apic_id_valid          = uv_apic_id_valid,
0835     .apic_id_registered     = uv_apic_id_registered,
0836 
0837     .delivery_mode          = APIC_DELIVERY_MODE_FIXED,
0838     .dest_mode_logical      = false,
0839 
0840     .disable_esr            = 0,
0841 
0842     .check_apicid_used      = NULL,
0843     .init_apic_ldr          = uv_init_apic_ldr,
0844     .ioapic_phys_id_map     = NULL,
0845     .setup_apic_routing     = NULL,
0846     .cpu_present_to_apicid      = default_cpu_present_to_apicid,
0847     .apicid_to_cpu_present      = NULL,
0848     .check_phys_apicid_present  = default_check_phys_apicid_present,
0849     .phys_pkg_id            = uv_phys_pkg_id,
0850 
0851     .get_apic_id            = x2apic_get_apic_id,
0852     .set_apic_id            = set_apic_id,
0853 
0854     .calc_dest_apicid       = apic_uv_calc_apicid,
0855 
0856     .send_IPI           = uv_send_IPI_one,
0857     .send_IPI_mask          = uv_send_IPI_mask,
0858     .send_IPI_mask_allbutself   = uv_send_IPI_mask_allbutself,
0859     .send_IPI_allbutself        = uv_send_IPI_allbutself,
0860     .send_IPI_all           = uv_send_IPI_all,
0861     .send_IPI_self          = uv_send_IPI_self,
0862 
0863     .wakeup_secondary_cpu       = uv_wakeup_secondary,
0864     .inquire_remote_apic        = NULL,
0865 
0866     .read               = native_apic_msr_read,
0867     .write              = native_apic_msr_write,
0868     .eoi_write          = native_apic_msr_eoi_write,
0869     .icr_read           = native_x2apic_icr_read,
0870     .icr_write          = native_x2apic_icr_write,
0871     .wait_icr_idle          = native_x2apic_wait_icr_idle,
0872     .safe_wait_icr_idle     = native_safe_x2apic_wait_icr_idle,
0873 };
0874 
0875 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH  3
0876 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT
0877 
0878 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
0879 {
0880     union uvh_rh_gam_alias_2_overlay_config_u alias;
0881     union uvh_rh_gam_alias_2_redirect_config_u redirect;
0882     unsigned long m_redirect;
0883     unsigned long m_overlay;
0884     int i;
0885 
0886     for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
0887         switch (i) {
0888         case 0:
0889             m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG;
0890             m_overlay  = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG;
0891             break;
0892         case 1:
0893             m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG;
0894             m_overlay  = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG;
0895             break;
0896         case 2:
0897             m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG;
0898             m_overlay  = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG;
0899             break;
0900         }
0901         alias.v = uv_read_local_mmr(m_overlay);
0902         if (alias.s.enable && alias.s.base == 0) {
0903             *size = (1UL << alias.s.m_alias);
0904             redirect.v = uv_read_local_mmr(m_redirect);
0905             *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
0906             return;
0907         }
0908     }
0909     *base = *size = 0;
0910 }
0911 
0912 enum map_type {map_wb, map_uc};
0913 static const char * const mt[] = { "WB", "UC" };
0914 
0915 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type)
0916 {
0917     unsigned long bytes, paddr;
0918 
0919     paddr = base << pshift;
0920     bytes = (1UL << bshift) * (max_pnode + 1);
0921     if (!paddr) {
0922         pr_info("UV: Map %s_HI base address NULL\n", id);
0923         return;
0924     }
0925     if (map_type == map_uc)
0926         init_extra_mapping_uc(paddr, bytes);
0927     else
0928         init_extra_mapping_wb(paddr, bytes);
0929 
0930     pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n",
0931         id, paddr, paddr + bytes, mt[map_type], max_pnode + 1);
0932 }
0933 
0934 static __init void map_gru_high(int max_pnode)
0935 {
0936     union uvh_rh_gam_gru_overlay_config_u gru;
0937     unsigned long mask, base;
0938     int shift;
0939 
0940     if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) {
0941         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG);
0942         shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
0943         mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
0944     } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) {
0945         gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG);
0946         shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT;
0947         mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK;
0948     } else {
0949         pr_err("UV: GRU unavailable (no MMR)\n");
0950         return;
0951     }
0952 
0953     if (!gru.s.enable) {
0954         pr_info("UV: GRU disabled (by BIOS)\n");
0955         return;
0956     }
0957 
0958     base = (gru.v & mask) >> shift;
0959     map_high("GRU", base, shift, shift, max_pnode, map_wb);
0960     gru_start_paddr = ((u64)base << shift);
0961     gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
0962 }
0963 
0964 static __init void map_mmr_high(int max_pnode)
0965 {
0966     unsigned long base;
0967     int shift;
0968     bool enable;
0969 
0970     if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) {
0971         union uvh_rh10_gam_mmr_overlay_config_u mmr;
0972 
0973         mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG);
0974         enable = mmr.s.enable;
0975         base = mmr.s.base;
0976         shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
0977     } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) {
0978         union uvh_rh_gam_mmr_overlay_config_u mmr;
0979 
0980         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG);
0981         enable = mmr.s.enable;
0982         base = mmr.s.base;
0983         shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT;
0984     } else {
0985         pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n",
0986             __func__);
0987         return;
0988     }
0989 
0990     if (enable)
0991         map_high("MMR", base, shift, shift, max_pnode, map_uc);
0992     else
0993         pr_info("UV: MMR disabled\n");
0994 }
0995 
0996 /* Arch specific ENUM cases */
0997 enum mmioh_arch {
0998     UV2_MMIOH = -1,
0999     UVY_MMIOH0, UVY_MMIOH1,
1000     UVX_MMIOH0, UVX_MMIOH1,
1001 };
1002 
1003 /* Calculate and Map MMIOH Regions */
1004 static void __init calc_mmioh_map(enum mmioh_arch index,
1005     int min_pnode, int max_pnode,
1006     int shift, unsigned long base, int m_io, int n_io)
1007 {
1008     unsigned long mmr, nasid_mask;
1009     int nasid, min_nasid, max_nasid, lnasid, mapped;
1010     int i, fi, li, n, max_io;
1011     char id[8];
1012 
1013     /* One (UV2) mapping */
1014     if (index == UV2_MMIOH) {
1015         strncpy(id, "MMIOH", sizeof(id));
1016         max_io = max_pnode;
1017         mapped = 0;
1018         goto map_exit;
1019     }
1020 
1021     /* small and large MMIOH mappings */
1022     switch (index) {
1023     case UVY_MMIOH0:
1024         mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0;
1025         nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1026         n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1027         min_nasid = min_pnode;
1028         max_nasid = max_pnode;
1029         mapped = 1;
1030         break;
1031     case UVY_MMIOH1:
1032         mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1;
1033         nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1034         n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1035         min_nasid = min_pnode;
1036         max_nasid = max_pnode;
1037         mapped = 1;
1038         break;
1039     case UVX_MMIOH0:
1040         mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0;
1041         nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK;
1042         n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH;
1043         min_nasid = min_pnode * 2;
1044         max_nasid = max_pnode * 2;
1045         mapped = 1;
1046         break;
1047     case UVX_MMIOH1:
1048         mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1;
1049         nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK;
1050         n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH;
1051         min_nasid = min_pnode * 2;
1052         max_nasid = max_pnode * 2;
1053         mapped = 1;
1054         break;
1055     default:
1056         pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index);
1057         return;
1058     }
1059 
1060     /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */
1061     snprintf(id, sizeof(id), "MMIOH%d", index%2);
1062 
1063     max_io = lnasid = fi = li = -1;
1064     for (i = 0; i < n; i++) {
1065         unsigned long m_redirect = mmr + i * 8;
1066         unsigned long redirect = uv_read_local_mmr(m_redirect);
1067 
1068         nasid = redirect & nasid_mask;
1069         if (i == 0)
1070             pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n",
1071                 id, redirect, m_redirect, nasid);
1072 
1073         /* Invalid NASID check */
1074         if (nasid < min_nasid || max_nasid < nasid) {
1075             pr_err("UV:%s:Invalid NASID:%x (range:%x..%x)\n",
1076                 __func__, index, min_nasid, max_nasid);
1077             nasid = -1;
1078         }
1079 
1080         if (nasid == lnasid) {
1081             li = i;
1082             /* Last entry check: */
1083             if (i != n-1)
1084                 continue;
1085         }
1086 
1087         /* Check if we have a cached (or last) redirect to print: */
1088         if (lnasid != -1 || (i == n-1 && nasid != -1))  {
1089             unsigned long addr1, addr2;
1090             int f, l;
1091 
1092             if (lnasid == -1) {
1093                 f = l = i;
1094                 lnasid = nasid;
1095             } else {
1096                 f = fi;
1097                 l = li;
1098             }
1099             addr1 = (base << shift) + f * (1ULL << m_io);
1100             addr2 = (base << shift) + (l + 1) * (1ULL << m_io);
1101             pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n",
1102                 id, fi, li, lnasid, addr1, addr2);
1103             if (max_io < l)
1104                 max_io = l;
1105         }
1106         fi = li = i;
1107         lnasid = nasid;
1108     }
1109 
1110 map_exit:
1111     pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n",
1112         id, base, shift, m_io, max_io, max_pnode);
1113 
1114     if (max_io >= 0 && !mapped)
1115         map_high(id, base, shift, m_io, max_io, map_uc);
1116 }
1117 
1118 static __init void map_mmioh_high(int min_pnode, int max_pnode)
1119 {
1120     /* UVY flavor */
1121     if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) {
1122         union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0;
1123         union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1;
1124 
1125         mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0);
1126         if (unlikely(mmioh0.s.enable == 0))
1127             pr_info("UV: MMIOH0 disabled\n");
1128         else
1129             calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode,
1130                 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1131                 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io);
1132 
1133         mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1);
1134         if (unlikely(mmioh1.s.enable == 0))
1135             pr_info("UV: MMIOH1 disabled\n");
1136         else
1137             calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode,
1138                 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1139                 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io);
1140         return;
1141     }
1142     /* UVX flavor */
1143     if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) {
1144         union uvh_rh_gam_mmioh_overlay_config0_u mmioh0;
1145         union uvh_rh_gam_mmioh_overlay_config1_u mmioh1;
1146 
1147         mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0);
1148         if (unlikely(mmioh0.s.enable == 0))
1149             pr_info("UV: MMIOH0 disabled\n");
1150         else {
1151             unsigned long base = uvxy_field(mmioh0, base, 0);
1152             int m_io = uvxy_field(mmioh0, m_io, 0);
1153             int n_io = uvxy_field(mmioh0, n_io, 0);
1154 
1155             calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode,
1156                 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT,
1157                 base, m_io, n_io);
1158         }
1159 
1160         mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1);
1161         if (unlikely(mmioh1.s.enable == 0))
1162             pr_info("UV: MMIOH1 disabled\n");
1163         else {
1164             unsigned long base = uvxy_field(mmioh1, base, 0);
1165             int m_io = uvxy_field(mmioh1, m_io, 0);
1166             int n_io = uvxy_field(mmioh1, n_io, 0);
1167 
1168             calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode,
1169                 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT,
1170                 base, m_io, n_io);
1171         }
1172         return;
1173     }
1174 
1175     /* UV2 flavor */
1176     if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) {
1177         union uvh_rh_gam_mmioh_overlay_config_u mmioh;
1178 
1179         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG);
1180         if (unlikely(mmioh.s2.enable == 0))
1181             pr_info("UV: MMIOH disabled\n");
1182         else
1183             calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode,
1184                 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT,
1185                 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io);
1186         return;
1187     }
1188 }
1189 
1190 static __init void map_low_mmrs(void)
1191 {
1192     if (UV_GLOBAL_MMR32_BASE)
1193         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
1194 
1195     if (UV_LOCAL_MMR_BASE)
1196         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
1197 }
1198 
1199 static __init void uv_rtc_init(void)
1200 {
1201     long status;
1202     u64 ticks_per_sec;
1203 
1204     status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec);
1205 
1206     if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
1207         pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n");
1208 
1209         /* BIOS gives wrong value for clock frequency, so guess: */
1210         sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
1211     } else {
1212         sn_rtc_cycles_per_second = ticks_per_sec;
1213     }
1214 }
1215 
1216 /* Direct Legacy VGA I/O traffic to designated IOH */
1217 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags)
1218 {
1219     int domain, bus, rc;
1220 
1221     if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
1222         return 0;
1223 
1224     if ((command_bits & PCI_COMMAND_IO) == 0)
1225         return 0;
1226 
1227     domain = pci_domain_nr(pdev->bus);
1228     bus = pdev->bus->number;
1229 
1230     rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
1231 
1232     return rc;
1233 }
1234 
1235 /*
1236  * Called on each CPU to initialize the per_cpu UV data area.
1237  * FIXME: hotplug not supported yet
1238  */
1239 void uv_cpu_init(void)
1240 {
1241     /* CPU 0 initialization will be done via uv_system_init. */
1242     if (smp_processor_id() == 0)
1243         return;
1244 
1245     uv_hub_info->nr_online_cpus++;
1246 }
1247 
1248 struct mn {
1249     unsigned char   m_val;
1250     unsigned char   n_val;
1251     unsigned char   m_shift;
1252     unsigned char   n_lshift;
1253 };
1254 
1255 /* Initialize caller's MN struct and fill in values */
1256 static void get_mn(struct mn *mnp)
1257 {
1258     memset(mnp, 0, sizeof(*mnp));
1259     mnp->n_val  = uv_cpuid.n_skt;
1260     if (is_uv(UV4|UVY)) {
1261         mnp->m_val  = 0;
1262         mnp->n_lshift   = 0;
1263     } else if (is_uv3_hub()) {
1264         union uvyh_gr0_gam_gr_config_u m_gr_config;
1265 
1266         mnp->m_val  = uv_cpuid.m_skt;
1267         m_gr_config.v   = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG);
1268         mnp->n_lshift   = m_gr_config.s3.m_skt;
1269     } else if (is_uv2_hub()) {
1270         mnp->m_val  = uv_cpuid.m_skt;
1271         mnp->n_lshift   = mnp->m_val == 40 ? 40 : 39;
1272     }
1273     mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1274 }
1275 
1276 static void __init uv_init_hub_info(struct uv_hub_info_s *hi)
1277 {
1278     struct mn mn;
1279 
1280     get_mn(&mn);
1281     hi->gpa_mask = mn.m_val ?
1282         (1UL << (mn.m_val + mn.n_val)) - 1 :
1283         (1UL << uv_cpuid.gpa_shift) - 1;
1284 
1285     hi->m_val       = mn.m_val;
1286     hi->n_val       = mn.n_val;
1287     hi->m_shift     = mn.m_shift;
1288     hi->n_lshift        = mn.n_lshift ? mn.n_lshift : 0;
1289     hi->hub_revision    = uv_hub_info->hub_revision;
1290     hi->hub_type        = uv_hub_info->hub_type;
1291     hi->pnode_mask      = uv_cpuid.pnode_mask;
1292     hi->nasid_shift     = uv_cpuid.nasid_shift;
1293     hi->min_pnode       = _min_pnode;
1294     hi->min_socket      = _min_socket;
1295     hi->pnode_to_socket = _pnode_to_socket;
1296     hi->socket_to_node  = _socket_to_node;
1297     hi->socket_to_pnode = _socket_to_pnode;
1298     hi->gr_table_len    = _gr_table_len;
1299     hi->gr_table        = _gr_table;
1300 
1301     uv_cpuid.gnode_shift    = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val);
1302     hi->gnode_extra     = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1;
1303     if (mn.m_val)
1304         hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val;
1305 
1306     if (uv_gp_table) {
1307         hi->global_mmr_base = uv_gp_table->mmr_base;
1308         hi->global_mmr_shift    = uv_gp_table->mmr_shift;
1309         hi->global_gru_base = uv_gp_table->gru_base;
1310         hi->global_gru_shift    = uv_gp_table->gru_shift;
1311         hi->gpa_shift       = uv_gp_table->gpa_shift;
1312         hi->gpa_mask        = (1UL << hi->gpa_shift) - 1;
1313     } else {
1314         hi->global_mmr_base =
1315             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) &
1316             ~UV_MMR_ENABLE;
1317         hi->global_mmr_shift    = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1318     }
1319 
1320     get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top);
1321 
1322     hi->apic_pnode_shift = uv_cpuid.socketid_shift;
1323 
1324     /* Show system specific info: */
1325     pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift);
1326     pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift);
1327     pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift);
1328     if (hi->global_gru_base)
1329         pr_info("UV: gru_base/shift:0x%lx/%ld\n",
1330             hi->global_gru_base, hi->global_gru_shift);
1331 
1332     pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra);
1333 }
1334 
1335 static void __init decode_gam_params(unsigned long ptr)
1336 {
1337     uv_gp_table = (struct uv_gam_parameters *)ptr;
1338 
1339     pr_info("UV: GAM Params...\n");
1340     pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1341         uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1342         uv_gp_table->gru_base, uv_gp_table->gru_shift,
1343         uv_gp_table->gpa_shift);
1344 }
1345 
1346 static void __init decode_gam_rng_tbl(unsigned long ptr)
1347 {
1348     struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1349     unsigned long lgre = 0, gend = 0;
1350     int index = 0;
1351     int sock_min = 999999, pnode_min = 99999;
1352     int sock_max = -1, pnode_max = -1;
1353 
1354     uv_gre_table = gre;
1355     for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1356         unsigned long size = ((unsigned long)(gre->limit - lgre)
1357                     << UV_GAM_RANGE_SHFT);
1358         int order = 0;
1359         char suffix[] = " KMGTPE";
1360         int flag = ' ';
1361 
1362         while (size > 9999 && order < sizeof(suffix)) {
1363             size /= 1024;
1364             order++;
1365         }
1366 
1367         /* adjust max block size to current range start */
1368         if (gre->type == 1 || gre->type == 2)
1369             if (adj_blksize(lgre))
1370                 flag = '*';
1371 
1372         if (!index) {
1373             pr_info("UV: GAM Range Table...\n");
1374             pr_info("UV:  # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN");
1375         }
1376         pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d   %04x  %02x %02x\n",
1377             index++,
1378             (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1379             (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1380             flag, size, suffix[order],
1381             gre->type, gre->nasid, gre->sockid, gre->pnode);
1382 
1383         if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1384             gend = (unsigned long)gre->limit << UV_GAM_RANGE_SHFT;
1385 
1386         /* update to next range start */
1387         lgre = gre->limit;
1388         if (sock_min > gre->sockid)
1389             sock_min = gre->sockid;
1390         if (sock_max < gre->sockid)
1391             sock_max = gre->sockid;
1392         if (pnode_min > gre->pnode)
1393             pnode_min = gre->pnode;
1394         if (pnode_max < gre->pnode)
1395             pnode_max = gre->pnode;
1396     }
1397     _min_socket = sock_min;
1398     _max_socket = sock_max;
1399     _min_pnode  = pnode_min;
1400     _max_pnode  = pnode_max;
1401     _gr_table_len   = index;
1402 
1403     pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x), pnodes(min:%x,max:%x), gap_end(%d)\n",
1404       index, _min_socket, _max_socket, _min_pnode, _max_pnode, fls64(gend));
1405 }
1406 
1407 /* Walk through UVsystab decoding the fields */
1408 static int __init decode_uv_systab(void)
1409 {
1410     struct uv_systab *st;
1411     int i;
1412 
1413     /* Get mapped UVsystab pointer */
1414     st = uv_systab;
1415 
1416     /* If UVsystab is version 1, there is no extended UVsystab */
1417     if (st && st->revision == UV_SYSTAB_VERSION_1)
1418         return 0;
1419 
1420     if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) {
1421         int rev = st ? st->revision : 0;
1422 
1423         pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n",
1424             rev, UV_SYSTAB_VERSION_UV4_LATEST);
1425         pr_err("UV: Does not support UV, switch to non-UV x86_64\n");
1426         uv_system_type = UV_NONE;
1427 
1428         return -EINVAL;
1429     }
1430 
1431     for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1432         unsigned long ptr = st->entry[i].offset;
1433 
1434         if (!ptr)
1435             continue;
1436 
1437         /* point to payload */
1438         ptr += (unsigned long)st;
1439 
1440         switch (st->entry[i].type) {
1441         case UV_SYSTAB_TYPE_GAM_PARAMS:
1442             decode_gam_params(ptr);
1443             break;
1444 
1445         case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1446             decode_gam_rng_tbl(ptr);
1447             break;
1448 
1449         case UV_SYSTAB_TYPE_ARCH_TYPE:
1450             /* already processed in early startup */
1451             break;
1452 
1453         default:
1454             pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n",
1455                 __func__, st->entry[i].type);
1456             break;
1457         }
1458     }
1459     return 0;
1460 }
1461 
1462 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */
1463 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1464 {
1465     unsigned long np;
1466     int i, uv_pb = 0;
1467 
1468     if (UVH_NODE_PRESENT_TABLE) {
1469         pr_info("UV: NODE_PRESENT_DEPTH = %d\n",
1470             UVH_NODE_PRESENT_TABLE_DEPTH);
1471         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
1472             np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
1473             pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
1474             uv_pb += hweight64(np);
1475         }
1476     }
1477     if (UVH_NODE_PRESENT_0) {
1478         np = uv_read_local_mmr(UVH_NODE_PRESENT_0);
1479         pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np);
1480         uv_pb += hweight64(np);
1481     }
1482     if (UVH_NODE_PRESENT_1) {
1483         np = uv_read_local_mmr(UVH_NODE_PRESENT_1);
1484         pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np);
1485         uv_pb += hweight64(np);
1486     }
1487     if (uv_possible_blades != uv_pb)
1488         uv_possible_blades = uv_pb;
1489 
1490     pr_info("UV: number nodes/possible blades %d\n", uv_pb);
1491 }
1492 
1493 static void __init build_socket_tables(void)
1494 {
1495     struct uv_gam_range_entry *gre = uv_gre_table;
1496     int num, nump;
1497     int cpu, i, lnid;
1498     int minsock = _min_socket;
1499     int maxsock = _max_socket;
1500     int minpnode = _min_pnode;
1501     int maxpnode = _max_pnode;
1502     size_t bytes;
1503 
1504     if (!gre) {
1505         if (is_uv2_hub() || is_uv3_hub()) {
1506             pr_info("UV: No UVsystab socket table, ignoring\n");
1507             return;
1508         }
1509         pr_err("UV: Error: UVsystab address translations not available!\n");
1510         BUG();
1511     }
1512 
1513     /* Build socket id -> node id, pnode */
1514     num = maxsock - minsock + 1;
1515     bytes = num * sizeof(_socket_to_node[0]);
1516     _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1517     _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1518 
1519     nump = maxpnode - minpnode + 1;
1520     bytes = nump * sizeof(_pnode_to_socket[0]);
1521     _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1522     BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1523 
1524     for (i = 0; i < num; i++)
1525         _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1526 
1527     for (i = 0; i < nump; i++)
1528         _pnode_to_socket[i] = SOCK_EMPTY;
1529 
1530     /* Fill in pnode/node/addr conversion list values: */
1531     pr_info("UV: GAM Building socket/pnode conversion tables\n");
1532     for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1533         if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1534             continue;
1535         i = gre->sockid - minsock;
1536         /* Duplicate: */
1537         if (_socket_to_pnode[i] != SOCK_EMPTY)
1538             continue;
1539         _socket_to_pnode[i] = gre->pnode;
1540 
1541         i = gre->pnode - minpnode;
1542         _pnode_to_socket[i] = gre->sockid;
1543 
1544         pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n",
1545             gre->sockid, gre->type, gre->nasid,
1546             _socket_to_pnode[gre->sockid - minsock],
1547             _pnode_to_socket[gre->pnode - minpnode]);
1548     }
1549 
1550     /* Set socket -> node values: */
1551     lnid = NUMA_NO_NODE;
1552     for_each_present_cpu(cpu) {
1553         int nid = cpu_to_node(cpu);
1554         int apicid, sockid;
1555 
1556         if (lnid == nid)
1557             continue;
1558         lnid = nid;
1559         apicid = per_cpu(x86_cpu_to_apicid, cpu);
1560         sockid = apicid >> uv_cpuid.socketid_shift;
1561         _socket_to_node[sockid - minsock] = nid;
1562         pr_info("UV: sid:%02x: apicid:%04x node:%2d\n",
1563             sockid, apicid, nid);
1564     }
1565 
1566     /* Set up physical blade to pnode translation from GAM Range Table: */
1567     bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1568     _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1569     BUG_ON(!_node_to_pnode);
1570 
1571     for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1572         unsigned short sockid;
1573 
1574         for (sockid = minsock; sockid <= maxsock; sockid++) {
1575             if (lnid == _socket_to_node[sockid - minsock]) {
1576                 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock];
1577                 break;
1578             }
1579         }
1580         if (sockid > maxsock) {
1581             pr_err("UV: socket for node %d not found!\n", lnid);
1582             BUG();
1583         }
1584     }
1585 
1586     /*
1587      * If socket id == pnode or socket id == node for all nodes,
1588      *   system runs faster by removing corresponding conversion table.
1589      */
1590     pr_info("UV: Checking socket->node/pnode for identity maps\n");
1591     if (minsock == 0) {
1592         for (i = 0; i < num; i++)
1593             if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i])
1594                 break;
1595         if (i >= num) {
1596             kfree(_socket_to_node);
1597             _socket_to_node = NULL;
1598             pr_info("UV: 1:1 socket_to_node table removed\n");
1599         }
1600     }
1601     if (minsock == minpnode) {
1602         for (i = 0; i < num; i++)
1603             if (_socket_to_pnode[i] != SOCK_EMPTY &&
1604                 _socket_to_pnode[i] != i + minpnode)
1605                 break;
1606         if (i >= num) {
1607             kfree(_socket_to_pnode);
1608             _socket_to_pnode = NULL;
1609             pr_info("UV: 1:1 socket_to_pnode table removed\n");
1610         }
1611     }
1612 }
1613 
1614 /* Check which reboot to use */
1615 static void check_efi_reboot(void)
1616 {
1617     /* If EFI reboot not available, use ACPI reboot */
1618     if (!efi_enabled(EFI_BOOT))
1619         reboot_type = BOOT_ACPI;
1620 }
1621 
1622 /*
1623  * User proc fs file handling now deprecated.
1624  * Recommend using /sys/firmware/sgi_uv/... instead.
1625  */
1626 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data)
1627 {
1628     pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n",
1629                current->comm);
1630     seq_printf(file, "0x%x\n", uv_hubbed_system);
1631     return 0;
1632 }
1633 
1634 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data)
1635 {
1636     pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n",
1637                current->comm);
1638     seq_printf(file, "0x%x\n", uv_hubless_system);
1639     return 0;
1640 }
1641 
1642 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data)
1643 {
1644     pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n",
1645                current->comm);
1646     seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id);
1647     return 0;
1648 }
1649 
1650 static __init void uv_setup_proc_files(int hubless)
1651 {
1652     struct proc_dir_entry *pde;
1653 
1654     pde = proc_mkdir(UV_PROC_NODE, NULL);
1655     proc_create_single("archtype", 0, pde, proc_archtype_show);
1656     if (hubless)
1657         proc_create_single("hubless", 0, pde, proc_hubless_show);
1658     else
1659         proc_create_single("hubbed", 0, pde, proc_hubbed_show);
1660 }
1661 
1662 /* Initialize UV hubless systems */
1663 static __init int uv_system_init_hubless(void)
1664 {
1665     int rc;
1666 
1667     /* Setup PCH NMI handler */
1668     uv_nmi_setup_hubless();
1669 
1670     /* Init kernel/BIOS interface */
1671     rc = uv_bios_init();
1672     if (rc < 0)
1673         return rc;
1674 
1675     /* Process UVsystab */
1676     rc = decode_uv_systab();
1677     if (rc < 0)
1678         return rc;
1679 
1680     /* Set section block size for current node memory */
1681     set_block_size();
1682 
1683     /* Create user access node */
1684     if (rc >= 0)
1685         uv_setup_proc_files(1);
1686 
1687     check_efi_reboot();
1688 
1689     return rc;
1690 }
1691 
1692 static void __init uv_system_init_hub(void)
1693 {
1694     struct uv_hub_info_s hub_info = {0};
1695     int bytes, cpu, nodeid;
1696     unsigned short min_pnode = 9999, max_pnode = 0;
1697     char *hub = is_uv5_hub() ? "UV500" :
1698             is_uv4_hub() ? "UV400" :
1699             is_uv3_hub() ? "UV300" :
1700             is_uv2_hub() ? "UV2000/3000" : NULL;
1701 
1702     if (!hub) {
1703         pr_err("UV: Unknown/unsupported UV hub\n");
1704         return;
1705     }
1706     pr_info("UV: Found %s hub\n", hub);
1707 
1708     map_low_mmrs();
1709 
1710     /* Get uv_systab for decoding, setup UV BIOS calls */
1711     uv_bios_init();
1712 
1713     /* If there's an UVsystab problem then abort UV init: */
1714     if (decode_uv_systab() < 0) {
1715         pr_err("UV: Mangled UVsystab format\n");
1716         return;
1717     }
1718 
1719     build_socket_tables();
1720     build_uv_gr_table();
1721     set_block_size();
1722     uv_init_hub_info(&hub_info);
1723     uv_possible_blades = num_possible_nodes();
1724     if (!_node_to_pnode)
1725         boot_init_possible_blades(&hub_info);
1726 
1727     /* uv_num_possible_blades() is really the hub count: */
1728     pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus());
1729 
1730     uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number);
1731     hub_info.coherency_domain_number = sn_coherency_id;
1732     uv_rtc_init();
1733 
1734     bytes = sizeof(void *) * uv_num_possible_blades();
1735     __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1736     BUG_ON(!__uv_hub_info_list);
1737 
1738     bytes = sizeof(struct uv_hub_info_s);
1739     for_each_node(nodeid) {
1740         struct uv_hub_info_s *new_hub;
1741 
1742         if (__uv_hub_info_list[nodeid]) {
1743             pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid);
1744             BUG();
1745         }
1746 
1747         /* Allocate new per hub info list */
1748         new_hub = (nodeid == 0) ?  &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid);
1749         BUG_ON(!new_hub);
1750         __uv_hub_info_list[nodeid] = new_hub;
1751         new_hub = uv_hub_info_list(nodeid);
1752         BUG_ON(!new_hub);
1753         *new_hub = hub_info;
1754 
1755         /* Use information from GAM table if available: */
1756         if (_node_to_pnode)
1757             new_hub->pnode = _node_to_pnode[nodeid];
1758         else /* Or fill in during CPU loop: */
1759             new_hub->pnode = 0xffff;
1760 
1761         new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1762         new_hub->memory_nid = NUMA_NO_NODE;
1763         new_hub->nr_possible_cpus = 0;
1764         new_hub->nr_online_cpus = 0;
1765     }
1766 
1767     /* Initialize per CPU info: */
1768     for_each_possible_cpu(cpu) {
1769         int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1770         int numa_node_id;
1771         unsigned short pnode;
1772 
1773         nodeid = cpu_to_node(cpu);
1774         numa_node_id = numa_cpu_node(cpu);
1775         pnode = uv_apicid_to_pnode(apicid);
1776 
1777         uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
1778         uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++;
1779         if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE)
1780             uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
1781 
1782         /* Init memoryless node: */
1783         if (nodeid != numa_node_id &&
1784             uv_hub_info_list(numa_node_id)->pnode == 0xffff)
1785             uv_hub_info_list(numa_node_id)->pnode = pnode;
1786         else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
1787             uv_cpu_hub_info(cpu)->pnode = pnode;
1788     }
1789 
1790     for_each_node(nodeid) {
1791         unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1792 
1793         /* Add pnode info for pre-GAM list nodes without CPUs: */
1794         if (pnode == 0xffff) {
1795             unsigned long paddr;
1796 
1797             paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1798             pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1799             uv_hub_info_list(nodeid)->pnode = pnode;
1800         }
1801         min_pnode = min(pnode, min_pnode);
1802         max_pnode = max(pnode, max_pnode);
1803         pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1804             nodeid,
1805             uv_hub_info_list(nodeid)->pnode,
1806             uv_hub_info_list(nodeid)->nr_possible_cpus);
1807     }
1808 
1809     pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1810     map_gru_high(max_pnode);
1811     map_mmr_high(max_pnode);
1812     map_mmioh_high(min_pnode, max_pnode);
1813 
1814     uv_nmi_setup();
1815     uv_cpu_init();
1816     uv_setup_proc_files(0);
1817 
1818     /* Register Legacy VGA I/O redirection handler: */
1819     pci_register_set_vga_state(uv_set_vga_state);
1820 
1821     check_efi_reboot();
1822 }
1823 
1824 /*
1825  * There is a different code path needed to initialize a UV system that does
1826  * not have a "UV HUB" (referred to as "hubless").
1827  */
1828 void __init uv_system_init(void)
1829 {
1830     if (likely(!is_uv_system() && !is_uv_hubless(1)))
1831         return;
1832 
1833     if (is_uv_system())
1834         uv_system_init_hub();
1835     else
1836         uv_system_init_hubless();
1837 }
1838 
1839 apic_driver(apic_x2apic_uv_x);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!