kernel/apic/apic_numachip.c

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Numascale NumaConnect-Specific APIC Code
0007  *
0008  * Copyright (C) 2011 Numascale AS. All rights reserved.
0009  *
0010  * Send feedback to <support@numascale.com>
0011  *
0012  */
0013 #include <linux/types.h>
0014 #include <linux/init.h>
0015 #include <linux/pgtable.h>
0016
0017 #include <asm/numachip/numachip.h>
0018 #include <asm/numachip/numachip_csr.h>
0019
0020
0021 #include "local.h"
0022
0023 u8 numachip_system __read_mostly;
0024 static const struct apic apic_numachip1;
0025 static const struct apic apic_numachip2;
0026 static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;
0027
0028 static unsigned int numachip1_get_apic_id(unsigned long x)
0029 {
0030     unsigned long value;
0031     unsigned int id = (x >> 24) & 0xff;
0032
0033     if (static_cpu_has(X86_FEATURE_NODEID_MSR)) {
0034         rdmsrl(MSR_FAM10H_NODE_ID, value);
0035         id |= (value << 2) & 0xff00;
0036     }
0037
0038     return id;
0039 }
0040
0041 static u32 numachip1_set_apic_id(unsigned int id)
0042 {
0043     return (id & 0xff) << 24;
0044 }
0045
0046 static unsigned int numachip2_get_apic_id(unsigned long x)
0047 {
0048     u64 mcfg;
0049
0050     rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg);
0051     return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);
0052 }
0053
0054 static u32 numachip2_set_apic_id(unsigned int id)
0055 {
0056     return id << 24;
0057 }
0058
0059 static int numachip_apic_id_valid(u32 apicid)
0060 {
0061     /* Trust what bootloader passes in MADT */
0062     return 1;
0063 }
0064
0065 static int numachip_apic_id_registered(void)
0066 {
0067     return 1;
0068 }
0069
0070 static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
0071 {
0072     return initial_apic_id >> index_msb;
0073 }
0074
0075 static void numachip1_apic_icr_write(int apicid, unsigned int val)
0076 {
0077     write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);
0078 }
0079
0080 static void numachip2_apic_icr_write(int apicid, unsigned int val)
0081 {
0082     numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);
0083 }
0084
0085 static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
0086 {
0087     numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
0088     numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |
0089         (start_rip >> 12));
0090
0091     return 0;
0092 }
0093
0094 static void numachip_send_IPI_one(int cpu, int vector)
0095 {
0096     int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu);
0097     unsigned int dmode;
0098
0099     preempt_disable();
0100     local_apicid = __this_cpu_read(x86_cpu_to_apicid);
0101
0102     /* Send via local APIC where non-local part matches */
0103     if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) {
0104         unsigned long flags;
0105
0106         local_irq_save(flags);
0107         __default_send_IPI_dest_field(apicid, vector,
0108             APIC_DEST_PHYSICAL);
0109         local_irq_restore(flags);
0110         preempt_enable();
0111         return;
0112     }
0113     preempt_enable();
0114
0115     dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED;
0116     numachip_apic_icr_write(apicid, dmode | vector);
0117 }
0118
0119 static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
0120 {
0121     unsigned int cpu;
0122
0123     for_each_cpu(cpu, mask)
0124         numachip_send_IPI_one(cpu, vector);
0125 }
0126
0127 static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
0128                         int vector)
0129 {
0130     unsigned int this_cpu = smp_processor_id();
0131     unsigned int cpu;
0132
0133     for_each_cpu(cpu, mask) {
0134         if (cpu != this_cpu)
0135             numachip_send_IPI_one(cpu, vector);
0136     }
0137 }
0138
0139 static void numachip_send_IPI_allbutself(int vector)
0140 {
0141     unsigned int this_cpu = smp_processor_id();
0142     unsigned int cpu;
0143
0144     for_each_online_cpu(cpu) {
0145         if (cpu != this_cpu)
0146             numachip_send_IPI_one(cpu, vector);
0147     }
0148 }
0149
0150 static void numachip_send_IPI_all(int vector)
0151 {
0152     numachip_send_IPI_mask(cpu_online_mask, vector);
0153 }
0154
0155 static void numachip_send_IPI_self(int vector)
0156 {
0157     apic_write(APIC_SELF_IPI, vector);
0158 }
0159
0160 static int __init numachip1_probe(void)
0161 {
0162     return apic == &apic_numachip1;
0163 }
0164
0165 static int __init numachip2_probe(void)
0166 {
0167     return apic == &apic_numachip2;
0168 }
0169
0170 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
0171 {
0172     u64 val;
0173     u32 nodes = 1;
0174
0175     this_cpu_write(cpu_llc_id, node);
0176
0177     /* Account for nodes per socket in multi-core-module processors */
0178     if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
0179         rdmsrl(MSR_FAM10H_NODE_ID, val);
0180         nodes = ((val >> 3) & 7) + 1;
0181     }
0182
0183     c->phys_proc_id = node / nodes;
0184 }
0185
0186 static int __init numachip_system_init(void)
0187 {
0188     /* Map the LCSR area and set up the apic_icr_write function */
0189     switch (numachip_system) {
0190     case 1:
0191         init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
0192         numachip_apic_icr_write = numachip1_apic_icr_write;
0193         break;
0194     case 2:
0195         init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE);
0196         numachip_apic_icr_write = numachip2_apic_icr_write;
0197         break;
0198     default:
0199         return 0;
0200     }
0201
0202     x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
0203     x86_init.pci.arch_init = pci_numachip_init;
0204
0205     return 0;
0206 }
0207 early_initcall(numachip_system_init);
0208
0209 static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
0210 {
0211     if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
0212         (strncmp(oem_table_id, "NCONNECT", 8) != 0))
0213         return 0;
0214
0215     numachip_system = 1;
0216
0217     return 1;
0218 }
0219
0220 static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
0221 {
0222     if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
0223         (strncmp(oem_table_id, "NCONECT2", 8) != 0))
0224         return 0;
0225
0226     numachip_system = 2;
0227
0228     return 1;
0229 }
0230
0231 /* APIC IPIs are queued */
0232 static void numachip_apic_wait_icr_idle(void)
0233 {
0234 }
0235
0236 /* APIC NMI IPIs are queued */
0237 static u32 numachip_safe_apic_wait_icr_idle(void)
0238 {
0239     return 0;
0240 }
0241
0242 static const struct apic apic_numachip1 __refconst = {
0243     .name               = "NumaConnect system",
0244     .probe              = numachip1_probe,
0245     .acpi_madt_oem_check        = numachip1_acpi_madt_oem_check,
0246     .apic_id_valid          = numachip_apic_id_valid,
0247     .apic_id_registered     = numachip_apic_id_registered,
0248
0249     .delivery_mode          = APIC_DELIVERY_MODE_FIXED,
0250     .dest_mode_logical      = false,
0251
0252     .disable_esr            = 0,
0253
0254     .check_apicid_used      = NULL,
0255     .init_apic_ldr          = flat_init_apic_ldr,
0256     .ioapic_phys_id_map     = NULL,
0257     .setup_apic_routing     = NULL,
0258     .cpu_present_to_apicid      = default_cpu_present_to_apicid,
0259     .apicid_to_cpu_present      = NULL,
0260     .check_phys_apicid_present  = default_check_phys_apicid_present,
0261     .phys_pkg_id            = numachip_phys_pkg_id,
0262
0263     .get_apic_id            = numachip1_get_apic_id,
0264     .set_apic_id            = numachip1_set_apic_id,
0265
0266     .calc_dest_apicid       = apic_default_calc_apicid,
0267
0268     .send_IPI           = numachip_send_IPI_one,
0269     .send_IPI_mask          = numachip_send_IPI_mask,
0270     .send_IPI_mask_allbutself   = numachip_send_IPI_mask_allbutself,
0271     .send_IPI_allbutself        = numachip_send_IPI_allbutself,
0272     .send_IPI_all           = numachip_send_IPI_all,
0273     .send_IPI_self          = numachip_send_IPI_self,
0274
0275     .wakeup_secondary_cpu       = numachip_wakeup_secondary,
0276     .inquire_remote_apic        = NULL, /* REMRD not supported */
0277
0278     .read               = native_apic_mem_read,
0279     .write              = native_apic_mem_write,
0280     .eoi_write          = native_apic_mem_write,
0281     .icr_read           = native_apic_icr_read,
0282     .icr_write          = native_apic_icr_write,
0283     .wait_icr_idle          = numachip_apic_wait_icr_idle,
0284     .safe_wait_icr_idle     = numachip_safe_apic_wait_icr_idle,
0285 };
0286
0287 apic_driver(apic_numachip1);
0288
0289 static const struct apic apic_numachip2 __refconst = {
0290     .name               = "NumaConnect2 system",
0291     .probe              = numachip2_probe,
0292     .acpi_madt_oem_check        = numachip2_acpi_madt_oem_check,
0293     .apic_id_valid          = numachip_apic_id_valid,
0294     .apic_id_registered     = numachip_apic_id_registered,
0295
0296     .delivery_mode          = APIC_DELIVERY_MODE_FIXED,
0297     .dest_mode_logical      = false,
0298
0299     .disable_esr            = 0,
0300
0301     .check_apicid_used      = NULL,
0302     .init_apic_ldr          = flat_init_apic_ldr,
0303     .ioapic_phys_id_map     = NULL,
0304     .setup_apic_routing     = NULL,
0305     .cpu_present_to_apicid      = default_cpu_present_to_apicid,
0306     .apicid_to_cpu_present      = NULL,
0307     .check_phys_apicid_present  = default_check_phys_apicid_present,
0308     .phys_pkg_id            = numachip_phys_pkg_id,
0309
0310     .get_apic_id            = numachip2_get_apic_id,
0311     .set_apic_id            = numachip2_set_apic_id,
0312
0313     .calc_dest_apicid       = apic_default_calc_apicid,
0314
0315     .send_IPI           = numachip_send_IPI_one,
0316     .send_IPI_mask          = numachip_send_IPI_mask,
0317     .send_IPI_mask_allbutself   = numachip_send_IPI_mask_allbutself,
0318     .send_IPI_allbutself        = numachip_send_IPI_allbutself,
0319     .send_IPI_all           = numachip_send_IPI_all,
0320     .send_IPI_self          = numachip_send_IPI_self,
0321
0322     .wakeup_secondary_cpu       = numachip_wakeup_secondary,
0323     .inquire_remote_apic        = NULL, /* REMRD not supported */
0324
0325     .read               = native_apic_mem_read,
0326     .write              = native_apic_mem_write,
0327     .eoi_write          = native_apic_mem_write,
0328     .icr_read           = native_apic_icr_read,
0329     .icr_write          = native_apic_icr_write,
0330     .wait_icr_idle          = numachip_apic_wait_icr_idle,
0331     .safe_wait_icr_idle     = numachip_safe_apic_wait_icr_idle,
0332 };
0333
0334 apic_driver(apic_numachip2);