x86/kernel/aperture_64.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Firmware replacement code.
0004  *
0005  * Work around broken BIOSes that don't set an aperture, only set the
0006  * aperture in the AGP bridge, or set too small aperture.
0007  *
0008  * If all fails map the aperture over some low memory.  This is cheaper than
0009  * doing bounce buffering. The memory is lost. This is done at early boot
0010  * because only the bootmem allocator can allocate 32+MB.
0011  *
0012  * Copyright 2002 Andi Kleen, SuSE Labs.
0013  */
0014 #define pr_fmt(fmt) "AGP: " fmt
0015
0016 #include <linux/kernel.h>
0017 #include <linux/kcore.h>
0018 #include <linux/types.h>
0019 #include <linux/init.h>
0020 #include <linux/memblock.h>
0021 #include <linux/mmzone.h>
0022 #include <linux/pci_ids.h>
0023 #include <linux/pci.h>
0024 #include <linux/bitops.h>
0025 #include <linux/suspend.h>
0026 #include <asm/e820/api.h>
0027 #include <asm/io.h>
0028 #include <asm/iommu.h>
0029 #include <asm/gart.h>
0030 #include <asm/pci-direct.h>
0031 #include <asm/dma.h>
0032 #include <asm/amd_nb.h>
0033 #include <asm/x86_init.h>
0034 #include <linux/crash_dump.h>
0035
0036 /*
0037  * Using 512M as goal, in case kexec will load kernel_big
0038  * that will do the on-position decompress, and could overlap with
0039  * with the gart aperture that is used.
0040  * Sequence:
0041  * kernel_small
0042  * ==> kexec (with kdump trigger path or gart still enabled)
0043  * ==> kernel_small (gart area become e820_reserved)
0044  * ==> kexec (with kdump trigger path or gart still enabled)
0045  * ==> kerne_big (uncompressed size will be big than 64M or 128M)
0046  * So don't use 512M below as gart iommu, leave the space for kernel
0047  * code for safe.
0048  */
0049 #define GART_MIN_ADDR   (512ULL << 20)
0050 #define GART_MAX_ADDR   (1ULL   << 32)
0051
0052 int gart_iommu_aperture;
0053 int gart_iommu_aperture_disabled __initdata;
0054 int gart_iommu_aperture_allowed __initdata;
0055
0056 int fallback_aper_order __initdata = 1; /* 64MB */
0057 int fallback_aper_force __initdata;
0058
0059 int fix_aperture __initdata = 1;
0060
0061 #if defined(CONFIG_PROC_VMCORE) || defined(CONFIG_PROC_KCORE)
0062 /*
0063  * If the first kernel maps the aperture over e820 RAM, the kdump kernel will
0064  * use the same range because it will remain configured in the northbridge.
0065  * Trying to dump this area via /proc/vmcore may crash the machine, so exclude
0066  * it from vmcore.
0067  */
0068 static unsigned long aperture_pfn_start, aperture_page_count;
0069
0070 static int gart_mem_pfn_is_ram(unsigned long pfn)
0071 {
0072     return likely((pfn < aperture_pfn_start) ||
0073               (pfn >= aperture_pfn_start + aperture_page_count));
0074 }
0075
0076 #ifdef CONFIG_PROC_VMCORE
0077 static bool gart_oldmem_pfn_is_ram(struct vmcore_cb *cb, unsigned long pfn)
0078 {
0079     return !!gart_mem_pfn_is_ram(pfn);
0080 }
0081
0082 static struct vmcore_cb gart_vmcore_cb = {
0083     .pfn_is_ram = gart_oldmem_pfn_is_ram,
0084 };
0085 #endif
0086
0087 static void __init exclude_from_core(u64 aper_base, u32 aper_order)
0088 {
0089     aperture_pfn_start = aper_base >> PAGE_SHIFT;
0090     aperture_page_count = (32 * 1024 * 1024) << aper_order >> PAGE_SHIFT;
0091 #ifdef CONFIG_PROC_VMCORE
0092     register_vmcore_cb(&gart_vmcore_cb);
0093 #endif
0094 #ifdef CONFIG_PROC_KCORE
0095     WARN_ON(register_mem_pfn_is_ram(&gart_mem_pfn_is_ram));
0096 #endif
0097 }
0098 #else
0099 static void exclude_from_core(u64 aper_base, u32 aper_order)
0100 {
0101 }
0102 #endif
0103
0104 /* This code runs before the PCI subsystem is initialized, so just
0105    access the northbridge directly. */
0106
0107 static u32 __init allocate_aperture(void)
0108 {
0109     u32 aper_size;
0110     unsigned long addr;
0111
0112     /* aper_size should <= 1G */
0113     if (fallback_aper_order > 5)
0114         fallback_aper_order = 5;
0115     aper_size = (32 * 1024 * 1024) << fallback_aper_order;
0116
0117     /*
0118      * Aperture has to be naturally aligned. This means a 2GB aperture
0119      * won't have much chance of finding a place in the lower 4GB of
0120      * memory. Unfortunately we cannot move it up because that would
0121      * make the IOMMU useless.
0122      */
0123     addr = memblock_phys_alloc_range(aper_size, aper_size,
0124                      GART_MIN_ADDR, GART_MAX_ADDR);
0125     if (!addr) {
0126         pr_err("Cannot allocate aperture memory hole [mem %#010lx-%#010lx] (%uKB)\n",
0127                addr, addr + aper_size - 1, aper_size >> 10);
0128         return 0;
0129     }
0130     pr_info("Mapping aperture over RAM [mem %#010lx-%#010lx] (%uKB)\n",
0131         addr, addr + aper_size - 1, aper_size >> 10);
0132     register_nosave_region(addr >> PAGE_SHIFT,
0133                    (addr+aper_size) >> PAGE_SHIFT);
0134
0135     return (u32)addr;
0136 }
0137
0138
0139 /* Find a PCI capability */
0140 static u32 __init find_cap(int bus, int slot, int func, int cap)
0141 {
0142     int bytes;
0143     u8 pos;
0144
0145     if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &
0146                         PCI_STATUS_CAP_LIST))
0147         return 0;
0148
0149     pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);
0150     for (bytes = 0; bytes < 48 && pos >= 0x40; bytes++) {
0151         u8 id;
0152
0153         pos &= ~3;
0154         id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);
0155         if (id == 0xff)
0156             break;
0157         if (id == cap)
0158             return pos;
0159         pos = read_pci_config_byte(bus, slot, func,
0160                         pos+PCI_CAP_LIST_NEXT);
0161     }
0162     return 0;
0163 }
0164
0165 /* Read a standard AGPv3 bridge header */
0166 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)
0167 {
0168     u32 apsize;
0169     u32 apsizereg;
0170     int nbits;
0171     u32 aper_low, aper_hi;
0172     u64 aper;
0173     u32 old_order;
0174
0175     pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func);
0176     apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);
0177     if (apsizereg == 0xffffffff) {
0178         pr_err("pci 0000:%02x:%02x.%d: APSIZE unreadable\n",
0179                bus, slot, func);
0180         return 0;
0181     }
0182
0183     /* old_order could be the value from NB gart setting */
0184     old_order = *order;
0185
0186     apsize = apsizereg & 0xfff;
0187     /* Some BIOS use weird encodings not in the AGPv3 table. */
0188     if (apsize & 0xff)
0189         apsize |= 0xf00;
0190     nbits = hweight16(apsize);
0191     *order = 7 - nbits;
0192     if ((int)*order < 0) /* < 32MB */
0193         *order = 0;
0194
0195     aper_low = read_pci_config(bus, slot, func, 0x10);
0196     aper_hi = read_pci_config(bus, slot, func, 0x14);
0197     aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
0198
0199     /*
0200      * On some sick chips, APSIZE is 0. It means it wants 4G
0201      * so let double check that order, and lets trust AMD NB settings:
0202      */
0203     pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (old size %uMB)\n",
0204         bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1,
0205         32 << old_order);
0206     if (aper + (32ULL<<(20 + *order)) > 0x100000000ULL) {
0207         pr_info("pci 0000:%02x:%02x.%d: AGP aperture size %uMB (APSIZE %#x) is not right, using settings from NB\n",
0208             bus, slot, func, 32 << *order, apsizereg);
0209         *order = old_order;
0210     }
0211
0212     pr_info("pci 0000:%02x:%02x.%d: AGP aperture [bus addr %#010Lx-%#010Lx] (%uMB, APSIZE %#x)\n",
0213         bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1,
0214         32 << *order, apsizereg);
0215
0216     if (!aperture_valid(aper, (32*1024*1024) << *order, 32<<20))
0217         return 0;
0218     return (u32)aper;
0219 }
0220
0221 /*
0222  * Look for an AGP bridge. Windows only expects the aperture in the
0223  * AGP bridge and some BIOS forget to initialize the Northbridge too.
0224  * Work around this here.
0225  *
0226  * Do an PCI bus scan by hand because we're running before the PCI
0227  * subsystem.
0228  *
0229  * All AMD AGP bridges are AGPv3 compliant, so we can do this scan
0230  * generically. It's probably overkill to always scan all slots because
0231  * the AGP bridges should be always an own bus on the HT hierarchy,
0232  * but do it here for future safety.
0233  */
0234 static u32 __init search_agp_bridge(u32 *order, int *valid_agp)
0235 {
0236     int bus, slot, func;
0237
0238     /* Poor man's PCI discovery */
0239     for (bus = 0; bus < 256; bus++) {
0240         for (slot = 0; slot < 32; slot++) {
0241             for (func = 0; func < 8; func++) {
0242                 u32 class, cap;
0243                 u8 type;
0244                 class = read_pci_config(bus, slot, func,
0245                             PCI_CLASS_REVISION);
0246                 if (class == 0xffffffff)
0247                     break;
0248
0249                 switch (class >> 16) {
0250                 case PCI_CLASS_BRIDGE_HOST:
0251                 case PCI_CLASS_BRIDGE_OTHER: /* needed? */
0252                     /* AGP bridge? */
0253                     cap = find_cap(bus, slot, func,
0254                             PCI_CAP_ID_AGP);
0255                     if (!cap)
0256                         break;
0257                     *valid_agp = 1;
0258                     return read_agp(bus, slot, func, cap,
0259                             order);
0260                 }
0261
0262                 /* No multi-function device? */
0263                 type = read_pci_config_byte(bus, slot, func,
0264                                    PCI_HEADER_TYPE);
0265                 if (!(type & 0x80))
0266                     break;
0267             }
0268         }
0269     }
0270     pr_info("No AGP bridge found\n");
0271
0272     return 0;
0273 }
0274
0275 static bool gart_fix_e820 __initdata = true;
0276
0277 static int __init parse_gart_mem(char *p)
0278 {
0279     return kstrtobool(p, &gart_fix_e820);
0280 }
0281 early_param("gart_fix_e820", parse_gart_mem);
0282
0283 /*
0284  * With kexec/kdump, if the first kernel doesn't shut down the GART and the
0285  * second kernel allocates a different GART region, there might be two
0286  * overlapping GART regions present:
0287  *
0288  * - the first still used by the GART initialized in the first kernel.
0289  * - (sub-)set of it used as normal RAM by the second kernel.
0290  *
0291  * which leads to memory corruptions and a kernel panic eventually.
0292  *
0293  * This can also happen if the BIOS has forgotten to mark the GART region
0294  * as reserved.
0295  *
0296  * Try to update the e820 map to mark that new region as reserved.
0297  */
0298 void __init early_gart_iommu_check(void)
0299 {
0300     u32 agp_aper_order = 0;
0301     int i, fix, slot, valid_agp = 0;
0302     u32 ctl;
0303     u32 aper_size = 0, aper_order = 0, last_aper_order = 0;
0304     u64 aper_base = 0, last_aper_base = 0;
0305     int aper_enabled = 0, last_aper_enabled = 0, last_valid = 0;
0306
0307     if (!amd_gart_present())
0308         return;
0309
0310     if (!early_pci_allowed())
0311         return;
0312
0313     /* This is mostly duplicate of iommu_hole_init */
0314     search_agp_bridge(&agp_aper_order, &valid_agp);
0315
0316     fix = 0;
0317     for (i = 0; amd_nb_bus_dev_ranges[i].dev_limit; i++) {
0318         int bus;
0319         int dev_base, dev_limit;
0320
0321         bus = amd_nb_bus_dev_ranges[i].bus;
0322         dev_base = amd_nb_bus_dev_ranges[i].dev_base;
0323         dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
0324
0325         for (slot = dev_base; slot < dev_limit; slot++) {
0326             if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
0327                 continue;
0328
0329             ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
0330             aper_enabled = ctl & GARTEN;
0331             aper_order = (ctl >> 1) & 7;
0332             aper_size = (32 * 1024 * 1024) << aper_order;
0333             aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
0334             aper_base <<= 25;
0335
0336             if (last_valid) {
0337                 if ((aper_order != last_aper_order) ||
0338                     (aper_base != last_aper_base) ||
0339                     (aper_enabled != last_aper_enabled)) {
0340                     fix = 1;
0341                     break;
0342                 }
0343             }
0344
0345             last_aper_order = aper_order;
0346             last_aper_base = aper_base;
0347             last_aper_enabled = aper_enabled;
0348             last_valid = 1;
0349         }
0350     }
0351
0352     if (!fix && !aper_enabled)
0353         return;
0354
0355     if (!aper_base || !aper_size || aper_base + aper_size > 0x100000000UL)
0356         fix = 1;
0357
0358     if (gart_fix_e820 && !fix && aper_enabled) {
0359         if (e820__mapped_any(aper_base, aper_base + aper_size,
0360                     E820_TYPE_RAM)) {
0361             /* reserve it, so we can reuse it in second kernel */
0362             pr_info("e820: reserve [mem %#010Lx-%#010Lx] for GART\n",
0363                 aper_base, aper_base + aper_size - 1);
0364             e820__range_add(aper_base, aper_size, E820_TYPE_RESERVED);
0365             e820__update_table_print();
0366         }
0367     }
0368
0369     if (valid_agp)
0370         return;
0371
0372     /* disable them all at first */
0373     for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
0374         int bus;
0375         int dev_base, dev_limit;
0376
0377         bus = amd_nb_bus_dev_ranges[i].bus;
0378         dev_base = amd_nb_bus_dev_ranges[i].dev_base;
0379         dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
0380
0381         for (slot = dev_base; slot < dev_limit; slot++) {
0382             if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
0383                 continue;
0384
0385             ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);
0386             ctl &= ~GARTEN;
0387             write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
0388         }
0389     }
0390
0391 }
0392
0393 static int __initdata printed_gart_size_msg;
0394
0395 void __init gart_iommu_hole_init(void)
0396 {
0397     u32 agp_aper_base = 0, agp_aper_order = 0;
0398     u32 aper_size, aper_alloc = 0, aper_order = 0, last_aper_order = 0;
0399     u64 aper_base, last_aper_base = 0;
0400     int fix, slot, valid_agp = 0;
0401     int i, node;
0402
0403     if (!amd_gart_present())
0404         return;
0405
0406     if (gart_iommu_aperture_disabled || !fix_aperture ||
0407         !early_pci_allowed())
0408         return;
0409
0410     pr_info("Checking aperture...\n");
0411
0412     if (!fallback_aper_force)
0413         agp_aper_base = search_agp_bridge(&agp_aper_order, &valid_agp);
0414
0415     fix = 0;
0416     node = 0;
0417     for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
0418         int bus;
0419         int dev_base, dev_limit;
0420         u32 ctl;
0421
0422         bus = amd_nb_bus_dev_ranges[i].bus;
0423         dev_base = amd_nb_bus_dev_ranges[i].dev_base;
0424         dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
0425
0426         for (slot = dev_base; slot < dev_limit; slot++) {
0427             if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
0428                 continue;
0429
0430             iommu_detected = 1;
0431             gart_iommu_aperture = 1;
0432             x86_init.iommu.iommu_init = gart_iommu_init;
0433
0434             ctl = read_pci_config(bus, slot, 3,
0435                           AMD64_GARTAPERTURECTL);
0436
0437             /*
0438              * Before we do anything else disable the GART. It may
0439              * still be enabled if we boot into a crash-kernel here.
0440              * Reconfiguring the GART while it is enabled could have
0441              * unknown side-effects.
0442              */
0443             ctl &= ~GARTEN;
0444             write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
0445
0446             aper_order = (ctl >> 1) & 7;
0447             aper_size = (32 * 1024 * 1024) << aper_order;
0448             aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;
0449             aper_base <<= 25;
0450
0451             pr_info("Node %d: aperture [bus addr %#010Lx-%#010Lx] (%uMB)\n",
0452                 node, aper_base, aper_base + aper_size - 1,
0453                 aper_size >> 20);
0454             node++;
0455
0456             if (!aperture_valid(aper_base, aper_size, 64<<20)) {
0457                 if (valid_agp && agp_aper_base &&
0458                     agp_aper_base == aper_base &&
0459                     agp_aper_order == aper_order) {
0460                     /* the same between two setting from NB and agp */
0461                     if (!no_iommu &&
0462                         max_pfn > MAX_DMA32_PFN &&
0463                         !printed_gart_size_msg) {
0464                         pr_err("you are using iommu with agp, but GART size is less than 64MB\n");
0465                         pr_err("please increase GART size in your BIOS setup\n");
0466                         pr_err("if BIOS doesn't have that option, contact your HW vendor!\n");
0467                         printed_gart_size_msg = 1;
0468                     }
0469                 } else {
0470                     fix = 1;
0471                     goto out;
0472                 }
0473             }
0474
0475             if ((last_aper_order && aper_order != last_aper_order) ||
0476                 (last_aper_base && aper_base != last_aper_base)) {
0477                 fix = 1;
0478                 goto out;
0479             }
0480             last_aper_order = aper_order;
0481             last_aper_base = aper_base;
0482         }
0483     }
0484
0485 out:
0486     if (!fix && !fallback_aper_force) {
0487         if (last_aper_base) {
0488             /*
0489              * If this is the kdump kernel, the first kernel
0490              * may have allocated the range over its e820 RAM
0491              * and fixed up the northbridge
0492              */
0493             exclude_from_core(last_aper_base, last_aper_order);
0494         }
0495         return;
0496     }
0497
0498     if (!fallback_aper_force) {
0499         aper_alloc = agp_aper_base;
0500         aper_order = agp_aper_order;
0501     }
0502
0503     if (aper_alloc) {
0504         /* Got the aperture from the AGP bridge */
0505     } else if ((!no_iommu && max_pfn > MAX_DMA32_PFN) ||
0506            force_iommu ||
0507            valid_agp ||
0508            fallback_aper_force) {
0509         pr_info("Your BIOS doesn't leave an aperture memory hole\n");
0510         pr_info("Please enable the IOMMU option in the BIOS setup\n");
0511         pr_info("This costs you %dMB of RAM\n",
0512             32 << fallback_aper_order);
0513
0514         aper_order = fallback_aper_order;
0515         aper_alloc = allocate_aperture();
0516         if (!aper_alloc) {
0517             /*
0518              * Could disable AGP and IOMMU here, but it's
0519              * probably not worth it. But the later users
0520              * cannot deal with bad apertures and turning
0521              * on the aperture over memory causes very
0522              * strange problems, so it's better to panic
0523              * early.
0524              */
0525             panic("Not enough memory for aperture");
0526         }
0527     } else {
0528         return;
0529     }
0530
0531     /*
0532      * If this is the kdump kernel _and_ the first kernel did not
0533      * configure the aperture in the northbridge, this range may
0534      * overlap with the first kernel's memory. We can't access the
0535      * range through vmcore even though it should be part of the dump.
0536      */
0537     exclude_from_core(aper_alloc, aper_order);
0538
0539     /* Fix up the north bridges */
0540     for (i = 0; i < amd_nb_bus_dev_ranges[i].dev_limit; i++) {
0541         int bus, dev_base, dev_limit;
0542
0543         /*
0544          * Don't enable translation yet but enable GART IO and CPU
0545          * accesses and set DISTLBWALKPRB since GART table memory is UC.
0546          */
0547         u32 ctl = aper_order << 1;
0548
0549         bus = amd_nb_bus_dev_ranges[i].bus;
0550         dev_base = amd_nb_bus_dev_ranges[i].dev_base;
0551         dev_limit = amd_nb_bus_dev_ranges[i].dev_limit;
0552         for (slot = dev_base; slot < dev_limit; slot++) {
0553             if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))
0554                 continue;
0555
0556             write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);
0557             write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);
0558         }
0559     }
0560
0561     set_up_gart_resume(aper_order, aper_alloc);
0562 }