uapi/asm/debugreg.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 #ifndef _UAPI_ASM_X86_DEBUGREG_H
0003 #define _UAPI_ASM_X86_DEBUGREG_H
0004
0005
0006 /* Indicate the register numbers for a number of the specific
0007    debug registers.  Registers 0-3 contain the addresses we wish to trap on */
0008 #define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
0009 #define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */
0010
0011 #define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
0012 #define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */
0013
0014 /* Define a few things for the status register.  We can use this to determine
0015    which debugging register was responsible for the trap.  The other bits
0016    are either reserved or not of interest to us. */
0017
0018 /* Define reserved bits in DR6 which are always set to 1 */
0019 #define DR6_RESERVED    (0xFFFF0FF0)
0020
0021 #define DR_TRAP0    (0x1)       /* db0 */
0022 #define DR_TRAP1    (0x2)       /* db1 */
0023 #define DR_TRAP2    (0x4)       /* db2 */
0024 #define DR_TRAP3    (0x8)       /* db3 */
0025 #define DR_TRAP_BITS    (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3)
0026
0027 #define DR_BUS_LOCK (0x800)     /* bus_lock */
0028 #define DR_STEP     (0x4000)    /* single-step */
0029 #define DR_SWITCH   (0x8000)    /* task switch */
0030
0031 /* Now define a bunch of things for manipulating the control register.
0032    The top two bytes of the control register consist of 4 fields of 4
0033    bits - each field corresponds to one of the four debug registers,
0034    and indicates what types of access we trap on, and how large the data
0035    field is that we are looking at */
0036
0037 #define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
0038 #define DR_CONTROL_SIZE 4   /* 4 control bits per register */
0039
0040 #define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
0041 #define DR_RW_WRITE (0x1)
0042 #define DR_RW_READ (0x3)
0043
0044 #define DR_LEN_1 (0x0) /* Settings for data length to trap on */
0045 #define DR_LEN_2 (0x4)
0046 #define DR_LEN_4 (0xC)
0047 #define DR_LEN_8 (0x8)
0048
0049 /* The low byte to the control register determine which registers are
0050    enabled.  There are 4 fields of two bits.  One bit is "local", meaning
0051    that the processor will reset the bit after a task switch and the other
0052    is global meaning that we have to explicitly reset the bit.  With linux,
0053    you can use either one, since we explicitly zero the register when we enter
0054    kernel mode. */
0055
0056 #define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
0057 #define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
0058 #define DR_LOCAL_ENABLE (0x1)      /* Local enable for reg 0 */
0059 #define DR_GLOBAL_ENABLE (0x2)     /* Global enable for reg 0 */
0060 #define DR_ENABLE_SIZE 2           /* 2 enable bits per register */
0061
0062 #define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
0063 #define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
0064
0065 /* The second byte to the control register has a few special things.
0066    We can slow the instruction pipeline for instructions coming via the
0067    gdt or the ldt if we want to.  I am not sure why this is an advantage */
0068
0069 #ifdef __i386__
0070 #define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
0071 #else
0072 #define DR_CONTROL_RESERVED (0xFFFFFFFF0000FC00UL) /* Reserved */
0073 #endif
0074
0075 #define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
0076 #define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
0077
0078 /*
0079  * HW breakpoint additions
0080  */
0081
0082 #endif /* _UAPI_ASM_X86_DEBUGREG_H */