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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_XOR_64_H
0003 #define _ASM_X86_XOR_64_H
0004 
0005 static struct xor_block_template xor_block_sse = {
0006     .name = "generic_sse",
0007     .do_2 = xor_sse_2,
0008     .do_3 = xor_sse_3,
0009     .do_4 = xor_sse_4,
0010     .do_5 = xor_sse_5,
0011 };
0012 
0013 
0014 /* Also try the AVX routines */
0015 #include <asm/xor_avx.h>
0016 
0017 /* We force the use of the SSE xor block because it can write around L2.
0018    We may also be able to load into the L1 only depending on how the cpu
0019    deals with a load to a line that is being prefetched.  */
0020 #undef XOR_TRY_TEMPLATES
0021 #define XOR_TRY_TEMPLATES           \
0022 do {                        \
0023     AVX_XOR_SPEED;              \
0024     xor_speed(&xor_block_sse_pf64);     \
0025     xor_speed(&xor_block_sse);      \
0026 } while (0)
0027 
0028 #endif /* _ASM_X86_XOR_64_H */