asm/xen/interface.h

0001 /******************************************************************************
0002  * arch-x86_32.h
0003  *
0004  * Guest OS interface to x86 Xen.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a copy
0007  * of this software and associated documentation files (the "Software"), to
0008  * deal in the Software without restriction, including without limitation the
0009  * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
0010  * sell copies of the Software, and to permit persons to whom the Software is
0011  * furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice shall be included in
0014  * all copies or substantial portions of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
0019  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0020  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0021  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0022  * DEALINGS IN THE SOFTWARE.
0023  *
0024  * Copyright (c) 2004-2006, K A Fraser
0025  */
0026
0027 #ifndef _ASM_X86_XEN_INTERFACE_H
0028 #define _ASM_X86_XEN_INTERFACE_H
0029
0030 /*
0031  * XEN_GUEST_HANDLE represents a guest pointer, when passed as a field
0032  * in a struct in memory.
0033  * XEN_GUEST_HANDLE_PARAM represent a guest pointer, when passed as an
0034  * hypercall argument.
0035  * XEN_GUEST_HANDLE_PARAM and XEN_GUEST_HANDLE are the same on X86 but
0036  * they might not be on other architectures.
0037  */
0038 #ifdef __XEN__
0039 #define __DEFINE_GUEST_HANDLE(name, type) \
0040     typedef struct { type *p; } __guest_handle_ ## name
0041 #else
0042 #define __DEFINE_GUEST_HANDLE(name, type) \
0043     typedef type * __guest_handle_ ## name
0044 #endif
0045
0046 #define DEFINE_GUEST_HANDLE_STRUCT(name) \
0047     __DEFINE_GUEST_HANDLE(name, struct name)
0048 #define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
0049 #define GUEST_HANDLE(name)        __guest_handle_ ## name
0050
0051 #ifdef __XEN__
0052 #if defined(__i386__)
0053 #define set_xen_guest_handle(hnd, val)          \
0054     do {                        \
0055         if (sizeof(hnd) == 8)           \
0056             *(uint64_t *)&(hnd) = 0;    \
0057         (hnd).p = val;              \
0058     } while (0)
0059 #elif defined(__x86_64__)
0060 #define set_xen_guest_handle(hnd, val)  do { (hnd).p = val; } while (0)
0061 #endif
0062 #else
0063 #if defined(__i386__)
0064 #define set_xen_guest_handle(hnd, val)          \
0065     do {                        \
0066         if (sizeof(hnd) == 8)           \
0067             *(uint64_t *)&(hnd) = 0;    \
0068         (hnd) = val;                \
0069     } while (0)
0070 #elif defined(__x86_64__)
0071 #define set_xen_guest_handle(hnd, val)  do { (hnd) = val; } while (0)
0072 #endif
0073 #endif
0074
0075 #ifndef __ASSEMBLY__
0076 /* Explicitly size integers that represent pfns in the public interface
0077  * with Xen so that on ARM we can have one ABI that works for 32 and 64
0078  * bit guests. */
0079 typedef unsigned long xen_pfn_t;
0080 #define PRI_xen_pfn "lx"
0081 typedef unsigned long xen_ulong_t;
0082 #define PRI_xen_ulong "lx"
0083 typedef long xen_long_t;
0084 #define PRI_xen_long "lx"
0085
0086 /* Guest handles for primitive C types. */
0087 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
0088 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
0089 DEFINE_GUEST_HANDLE(char);
0090 DEFINE_GUEST_HANDLE(int);
0091 DEFINE_GUEST_HANDLE(void);
0092 DEFINE_GUEST_HANDLE(uint64_t);
0093 DEFINE_GUEST_HANDLE(uint32_t);
0094 DEFINE_GUEST_HANDLE(xen_pfn_t);
0095 DEFINE_GUEST_HANDLE(xen_ulong_t);
0096 #endif
0097
0098 #ifndef HYPERVISOR_VIRT_START
0099 #define HYPERVISOR_VIRT_START mk_unsigned_long(__HYPERVISOR_VIRT_START)
0100 #endif
0101
0102 #define MACH2PHYS_VIRT_START  mk_unsigned_long(__MACH2PHYS_VIRT_START)
0103 #define MACH2PHYS_VIRT_END    mk_unsigned_long(__MACH2PHYS_VIRT_END)
0104 #define MACH2PHYS_NR_ENTRIES  ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>__MACH2PHYS_SHIFT)
0105
0106 /* Maximum number of virtual CPUs in multi-processor guests. */
0107 #define MAX_VIRT_CPUS 32
0108
0109 /*
0110  * SEGMENT DESCRIPTOR TABLES
0111  */
0112 /*
0113  * A number of GDT entries are reserved by Xen. These are not situated at the
0114  * start of the GDT because some stupid OSes export hard-coded selector values
0115  * in their ABI. These hard-coded values are always near the start of the GDT,
0116  * so Xen places itself out of the way, at the far end of the GDT.
0117  *
0118  * NB The LDT is set using the MMUEXT_SET_LDT op of HYPERVISOR_mmuext_op
0119  */
0120 #define FIRST_RESERVED_GDT_PAGE  14
0121 #define FIRST_RESERVED_GDT_BYTE  (FIRST_RESERVED_GDT_PAGE * 4096)
0122 #define FIRST_RESERVED_GDT_ENTRY (FIRST_RESERVED_GDT_BYTE / 8)
0123
0124 /*
0125  * Send an array of these to HYPERVISOR_set_trap_table().
0126  * Terminate the array with a sentinel entry, with traps[].address==0.
0127  * The privilege level specifies which modes may enter a trap via a software
0128  * interrupt. On x86/64, since rings 1 and 2 are unavailable, we allocate
0129  * privilege levels as follows:
0130  *  Level == 0: No one may enter
0131  *  Level == 1: Kernel may enter
0132  *  Level == 2: Kernel may enter
0133  *  Level == 3: Everyone may enter
0134  */
0135 #define TI_GET_DPL(_ti)     ((_ti)->flags & 3)
0136 #define TI_GET_IF(_ti)      ((_ti)->flags & 4)
0137 #define TI_SET_DPL(_ti, _dpl)   ((_ti)->flags |= (_dpl))
0138 #define TI_SET_IF(_ti, _if) ((_ti)->flags |= ((!!(_if))<<2))
0139
0140 #ifndef __ASSEMBLY__
0141 struct trap_info {
0142     uint8_t       vector;  /* exception vector                              */
0143     uint8_t       flags;   /* 0-3: privilege level; 4: clear event enable?  */
0144     uint16_t      cs;      /* code selector                                 */
0145     unsigned long address; /* code offset                                   */
0146 };
0147 DEFINE_GUEST_HANDLE_STRUCT(trap_info);
0148
0149 struct arch_shared_info {
0150     /*
0151      * Number of valid entries in the p2m table(s) anchored at
0152      * pfn_to_mfn_frame_list_list and/or p2m_vaddr.
0153      */
0154     unsigned long max_pfn;
0155     /*
0156      * Frame containing list of mfns containing list of mfns containing p2m.
0157      * A value of 0 indicates it has not yet been set up, ~0 indicates it
0158      * has been set to invalid e.g. due to the p2m being too large for the
0159      * 3-level p2m tree. In this case the linear mapper p2m list anchored
0160      * at p2m_vaddr is to be used.
0161      */
0162     xen_pfn_t pfn_to_mfn_frame_list_list;
0163     unsigned long nmi_reason;
0164     /*
0165      * Following three fields are valid if p2m_cr3 contains a value
0166      * different from 0.
0167      * p2m_cr3 is the root of the address space where p2m_vaddr is valid.
0168      * p2m_cr3 is in the same format as a cr3 value in the vcpu register
0169      * state and holds the folded machine frame number (via xen_pfn_to_cr3)
0170      * of a L3 or L4 page table.
0171      * p2m_vaddr holds the virtual address of the linear p2m list. All
0172      * entries in the range [0...max_pfn[ are accessible via this pointer.
0173      * p2m_generation will be incremented by the guest before and after each
0174      * change of the mappings of the p2m list. p2m_generation starts at 0
0175      * and a value with the least significant bit set indicates that a
0176      * mapping update is in progress. This allows guest external software
0177      * (e.g. in Dom0) to verify that read mappings are consistent and
0178      * whether they have changed since the last check.
0179      * Modifying a p2m element in the linear p2m list is allowed via an
0180      * atomic write only.
0181      */
0182     unsigned long p2m_cr3;      /* cr3 value of the p2m address space */
0183     unsigned long p2m_vaddr;    /* virtual address of the p2m list */
0184     unsigned long p2m_generation;   /* generation count of p2m mapping */
0185 #ifdef CONFIG_X86_32
0186     uint32_t wc_sec_hi;
0187 #endif
0188 };
0189 #endif  /* !__ASSEMBLY__ */
0190
0191 #ifdef CONFIG_X86_32
0192 #include <asm/xen/interface_32.h>
0193 #else
0194 #include <asm/xen/interface_64.h>
0195 #endif
0196
0197 #include <asm/pvclock-abi.h>
0198
0199 #ifndef __ASSEMBLY__
0200 /*
0201  * The following is all CPU context. Note that the fpu_ctxt block is filled
0202  * in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
0203  *
0204  * Also note that when calling DOMCTL_setvcpucontext and VCPU_initialise
0205  * for HVM and PVH guests, not all information in this structure is updated:
0206  *
0207  * - For HVM guests, the structures read include: fpu_ctxt (if
0208  * VGCT_I387_VALID is set), flags, user_regs, debugreg[*]
0209  *
0210  * - PVH guests are the same as HVM guests, but additionally use ctrlreg[3] to
0211  * set cr3. All other fields not used should be set to 0.
0212  */
0213 struct vcpu_guest_context {
0214     /* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */
0215     struct { char x[512]; } fpu_ctxt;       /* User-level FPU registers     */
0216 #define VGCF_I387_VALID                (1<<0)
0217 #define VGCF_IN_KERNEL                 (1<<2)
0218 #define _VGCF_i387_valid               0
0219 #define VGCF_i387_valid                (1<<_VGCF_i387_valid)
0220 #define _VGCF_in_kernel                2
0221 #define VGCF_in_kernel                 (1<<_VGCF_in_kernel)
0222 #define _VGCF_failsafe_disables_events 3
0223 #define VGCF_failsafe_disables_events  (1<<_VGCF_failsafe_disables_events)
0224 #define _VGCF_syscall_disables_events  4
0225 #define VGCF_syscall_disables_events   (1<<_VGCF_syscall_disables_events)
0226 #define _VGCF_online                   5
0227 #define VGCF_online                    (1<<_VGCF_online)
0228     unsigned long flags;                    /* VGCF_* flags                 */
0229     struct cpu_user_regs user_regs;         /* User-level CPU registers     */
0230     struct trap_info trap_ctxt[256];        /* Virtual IDT                  */
0231     unsigned long ldt_base, ldt_ents;       /* LDT (linear address, # ents) */
0232     unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
0233     unsigned long kernel_ss, kernel_sp;     /* Virtual TSS (only SS1/SP1)   */
0234     /* NB. User pagetable on x86/64 is placed in ctrlreg[1]. */
0235     unsigned long ctrlreg[8];               /* CR0-CR7 (control registers)  */
0236     unsigned long debugreg[8];              /* DB0-DB7 (debug registers)    */
0237 #ifdef __i386__
0238     unsigned long event_callback_cs;        /* CS:EIP of event callback     */
0239     unsigned long event_callback_eip;
0240     unsigned long failsafe_callback_cs;     /* CS:EIP of failsafe callback  */
0241     unsigned long failsafe_callback_eip;
0242 #else
0243     unsigned long event_callback_eip;
0244     unsigned long failsafe_callback_eip;
0245     unsigned long syscall_callback_eip;
0246 #endif
0247     unsigned long vm_assist;                /* VMASST_TYPE_* bitmap */
0248 #ifdef __x86_64__
0249     /* Segment base addresses. */
0250     uint64_t      fs_base;
0251     uint64_t      gs_base_kernel;
0252     uint64_t      gs_base_user;
0253 #endif
0254 };
0255 DEFINE_GUEST_HANDLE_STRUCT(vcpu_guest_context);
0256
0257 /* AMD PMU registers and structures */
0258 struct xen_pmu_amd_ctxt {
0259     /*
0260      * Offsets to counter and control MSRs (relative to xen_pmu_arch.c.amd).
0261      * For PV(H) guests these fields are RO.
0262      */
0263     uint32_t counters;
0264     uint32_t ctrls;
0265
0266     /* Counter MSRs */
0267 #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
0268     uint64_t regs[];
0269 #elif defined(__GNUC__)
0270     uint64_t regs[0];
0271 #endif
0272 };
0273
0274 /* Intel PMU registers and structures */
0275 struct xen_pmu_cntr_pair {
0276     uint64_t counter;
0277     uint64_t control;
0278 };
0279
0280 struct xen_pmu_intel_ctxt {
0281     /*
0282      * Offsets to fixed and architectural counter MSRs (relative to
0283      * xen_pmu_arch.c.intel).
0284      * For PV(H) guests these fields are RO.
0285      */
0286     uint32_t fixed_counters;
0287     uint32_t arch_counters;
0288
0289     /* PMU registers */
0290     uint64_t global_ctrl;
0291     uint64_t global_ovf_ctrl;
0292     uint64_t global_status;
0293     uint64_t fixed_ctrl;
0294     uint64_t ds_area;
0295     uint64_t pebs_enable;
0296     uint64_t debugctl;
0297
0298     /* Fixed and architectural counter MSRs */
0299 #if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
0300     uint64_t regs[];
0301 #elif defined(__GNUC__)
0302     uint64_t regs[0];
0303 #endif
0304 };
0305
0306 /* Sampled domain's registers */
0307 struct xen_pmu_regs {
0308     uint64_t ip;
0309     uint64_t sp;
0310     uint64_t flags;
0311     uint16_t cs;
0312     uint16_t ss;
0313     uint8_t cpl;
0314     uint8_t pad[3];
0315 };
0316
0317 /* PMU flags */
0318 #define PMU_CACHED     (1<<0) /* PMU MSRs are cached in the context */
0319 #define PMU_SAMPLE_USER    (1<<1) /* Sample is from user or kernel mode */
0320 #define PMU_SAMPLE_REAL    (1<<2) /* Sample is from realmode */
0321 #define PMU_SAMPLE_PV      (1<<3) /* Sample from a PV guest */
0322
0323 /*
0324  * Architecture-specific information describing state of the processor at
0325  * the time of PMU interrupt.
0326  * Fields of this structure marked as RW for guest should only be written by
0327  * the guest when PMU_CACHED bit in pmu_flags is set (which is done by the
0328  * hypervisor during PMU interrupt). Hypervisor will read updated data in
0329  * XENPMU_flush hypercall and clear PMU_CACHED bit.
0330  */
0331 struct xen_pmu_arch {
0332     union {
0333         /*
0334          * Processor's registers at the time of interrupt.
0335          * WO for hypervisor, RO for guests.
0336          */
0337         struct xen_pmu_regs regs;
0338         /*
0339          * Padding for adding new registers to xen_pmu_regs in
0340          * the future
0341          */
0342 #define XENPMU_REGS_PAD_SZ  64
0343         uint8_t pad[XENPMU_REGS_PAD_SZ];
0344     } r;
0345
0346     /* WO for hypervisor, RO for guest */
0347     uint64_t pmu_flags;
0348
0349     /*
0350      * APIC LVTPC register.
0351      * RW for both hypervisor and guest.
0352      * Only APIC_LVT_MASKED bit is loaded by the hypervisor into hardware
0353      * during XENPMU_flush or XENPMU_lvtpc_set.
0354      */
0355     union {
0356         uint32_t lapic_lvtpc;
0357         uint64_t pad;
0358     } l;
0359
0360     /*
0361      * Vendor-specific PMU registers.
0362      * RW for both hypervisor and guest (see exceptions above).
0363      * Guest's updates to this field are verified and then loaded by the
0364      * hypervisor into hardware during XENPMU_flush
0365      */
0366     union {
0367         struct xen_pmu_amd_ctxt amd;
0368         struct xen_pmu_intel_ctxt intel;
0369
0370         /*
0371          * Padding for contexts (fixed parts only, does not include
0372          * MSR banks that are specified by offsets)
0373          */
0374 #define XENPMU_CTXT_PAD_SZ  128
0375         uint8_t pad[XENPMU_CTXT_PAD_SZ];
0376     } c;
0377 };
0378
0379 #endif  /* !__ASSEMBLY__ */
0380
0381 /*
0382  * Prefix forces emulation of some non-trapping instructions.
0383  * Currently only CPUID.
0384  */
0385 #include <asm/emulate_prefix.h>
0386
0387 #define XEN_EMULATE_PREFIX __ASM_FORM(.byte __XEN_EMULATE_PREFIX ;)
0388 #define XEN_CPUID          XEN_EMULATE_PREFIX __ASM_FORM(cpuid)
0389
0390 #endif /* _ASM_X86_XEN_INTERFACE_H */