include/asm/vmx.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * vmx.h: VMX Architecture related definitions
0004  * Copyright (c) 2004, Intel Corporation.
0005  *
0006  * A few random additions are:
0007  * Copyright (C) 2006 Qumranet
0008  *    Avi Kivity <avi@qumranet.com>
0009  *    Yaniv Kamay <yaniv@qumranet.com>
0010  */
0011 #ifndef VMX_H
0012 #define VMX_H
0013
0014
0015 #include <linux/bitops.h>
0016 #include <linux/types.h>
0017 #include <uapi/asm/vmx.h>
0018 #include <asm/vmxfeatures.h>
0019
0020 #define VMCS_CONTROL_BIT(x) BIT(VMX_FEATURE_##x & 0x1f)
0021
0022 /*
0023  * Definitions of Primary Processor-Based VM-Execution Controls.
0024  */
0025 #define CPU_BASED_INTR_WINDOW_EXITING           VMCS_CONTROL_BIT(INTR_WINDOW_EXITING)
0026 #define CPU_BASED_USE_TSC_OFFSETTING            VMCS_CONTROL_BIT(USE_TSC_OFFSETTING)
0027 #define CPU_BASED_HLT_EXITING                   VMCS_CONTROL_BIT(HLT_EXITING)
0028 #define CPU_BASED_INVLPG_EXITING                VMCS_CONTROL_BIT(INVLPG_EXITING)
0029 #define CPU_BASED_MWAIT_EXITING                 VMCS_CONTROL_BIT(MWAIT_EXITING)
0030 #define CPU_BASED_RDPMC_EXITING                 VMCS_CONTROL_BIT(RDPMC_EXITING)
0031 #define CPU_BASED_RDTSC_EXITING                 VMCS_CONTROL_BIT(RDTSC_EXITING)
0032 #define CPU_BASED_CR3_LOAD_EXITING      VMCS_CONTROL_BIT(CR3_LOAD_EXITING)
0033 #define CPU_BASED_CR3_STORE_EXITING     VMCS_CONTROL_BIT(CR3_STORE_EXITING)
0034 #define CPU_BASED_ACTIVATE_TERTIARY_CONTROLS    VMCS_CONTROL_BIT(TERTIARY_CONTROLS)
0035 #define CPU_BASED_CR8_LOAD_EXITING              VMCS_CONTROL_BIT(CR8_LOAD_EXITING)
0036 #define CPU_BASED_CR8_STORE_EXITING             VMCS_CONTROL_BIT(CR8_STORE_EXITING)
0037 #define CPU_BASED_TPR_SHADOW                    VMCS_CONTROL_BIT(VIRTUAL_TPR)
0038 #define CPU_BASED_NMI_WINDOW_EXITING        VMCS_CONTROL_BIT(NMI_WINDOW_EXITING)
0039 #define CPU_BASED_MOV_DR_EXITING                VMCS_CONTROL_BIT(MOV_DR_EXITING)
0040 #define CPU_BASED_UNCOND_IO_EXITING             VMCS_CONTROL_BIT(UNCOND_IO_EXITING)
0041 #define CPU_BASED_USE_IO_BITMAPS                VMCS_CONTROL_BIT(USE_IO_BITMAPS)
0042 #define CPU_BASED_MONITOR_TRAP_FLAG             VMCS_CONTROL_BIT(MONITOR_TRAP_FLAG)
0043 #define CPU_BASED_USE_MSR_BITMAPS               VMCS_CONTROL_BIT(USE_MSR_BITMAPS)
0044 #define CPU_BASED_MONITOR_EXITING               VMCS_CONTROL_BIT(MONITOR_EXITING)
0045 #define CPU_BASED_PAUSE_EXITING                 VMCS_CONTROL_BIT(PAUSE_EXITING)
0046 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   VMCS_CONTROL_BIT(SEC_CONTROLS)
0047
0048 #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x0401e172
0049
0050 /*
0051  * Definitions of Secondary Processor-Based VM-Execution Controls.
0052  */
0053 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES VMCS_CONTROL_BIT(VIRT_APIC_ACCESSES)
0054 #define SECONDARY_EXEC_ENABLE_EPT               VMCS_CONTROL_BIT(EPT)
0055 #define SECONDARY_EXEC_DESC         VMCS_CONTROL_BIT(DESC_EXITING)
0056 #define SECONDARY_EXEC_ENABLE_RDTSCP        VMCS_CONTROL_BIT(RDTSCP)
0057 #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   VMCS_CONTROL_BIT(VIRTUAL_X2APIC)
0058 #define SECONDARY_EXEC_ENABLE_VPID              VMCS_CONTROL_BIT(VPID)
0059 #define SECONDARY_EXEC_WBINVD_EXITING       VMCS_CONTROL_BIT(WBINVD_EXITING)
0060 #define SECONDARY_EXEC_UNRESTRICTED_GUEST   VMCS_CONTROL_BIT(UNRESTRICTED_GUEST)
0061 #define SECONDARY_EXEC_APIC_REGISTER_VIRT       VMCS_CONTROL_BIT(APIC_REGISTER_VIRT)
0062 #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY    VMCS_CONTROL_BIT(VIRT_INTR_DELIVERY)
0063 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING   VMCS_CONTROL_BIT(PAUSE_LOOP_EXITING)
0064 #define SECONDARY_EXEC_RDRAND_EXITING       VMCS_CONTROL_BIT(RDRAND_EXITING)
0065 #define SECONDARY_EXEC_ENABLE_INVPCID       VMCS_CONTROL_BIT(INVPCID)
0066 #define SECONDARY_EXEC_ENABLE_VMFUNC            VMCS_CONTROL_BIT(VMFUNC)
0067 #define SECONDARY_EXEC_SHADOW_VMCS              VMCS_CONTROL_BIT(SHADOW_VMCS)
0068 #define SECONDARY_EXEC_ENCLS_EXITING        VMCS_CONTROL_BIT(ENCLS_EXITING)
0069 #define SECONDARY_EXEC_RDSEED_EXITING       VMCS_CONTROL_BIT(RDSEED_EXITING)
0070 #define SECONDARY_EXEC_ENABLE_PML               VMCS_CONTROL_BIT(PAGE_MOD_LOGGING)
0071 #define SECONDARY_EXEC_PT_CONCEAL_VMX       VMCS_CONTROL_BIT(PT_CONCEAL_VMX)
0072 #define SECONDARY_EXEC_XSAVES           VMCS_CONTROL_BIT(XSAVES)
0073 #define SECONDARY_EXEC_MODE_BASED_EPT_EXEC  VMCS_CONTROL_BIT(MODE_BASED_EPT_EXEC)
0074 #define SECONDARY_EXEC_PT_USE_GPA       VMCS_CONTROL_BIT(PT_USE_GPA)
0075 #define SECONDARY_EXEC_TSC_SCALING              VMCS_CONTROL_BIT(TSC_SCALING)
0076 #define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE    VMCS_CONTROL_BIT(USR_WAIT_PAUSE)
0077 #define SECONDARY_EXEC_BUS_LOCK_DETECTION   VMCS_CONTROL_BIT(BUS_LOCK_DETECTION)
0078 #define SECONDARY_EXEC_NOTIFY_VM_EXITING    VMCS_CONTROL_BIT(NOTIFY_VM_EXITING)
0079
0080 /*
0081  * Definitions of Tertiary Processor-Based VM-Execution Controls.
0082  */
0083 #define TERTIARY_EXEC_IPI_VIRT          VMCS_CONTROL_BIT(IPI_VIRT)
0084
0085 #define PIN_BASED_EXT_INTR_MASK                 VMCS_CONTROL_BIT(INTR_EXITING)
0086 #define PIN_BASED_NMI_EXITING                   VMCS_CONTROL_BIT(NMI_EXITING)
0087 #define PIN_BASED_VIRTUAL_NMIS                  VMCS_CONTROL_BIT(VIRTUAL_NMIS)
0088 #define PIN_BASED_VMX_PREEMPTION_TIMER          VMCS_CONTROL_BIT(PREEMPTION_TIMER)
0089 #define PIN_BASED_POSTED_INTR                   VMCS_CONTROL_BIT(POSTED_INTR)
0090
0091 #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR 0x00000016
0092
0093 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000004
0094 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
0095 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
0096 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
0097 #define VM_EXIT_SAVE_IA32_PAT           0x00040000
0098 #define VM_EXIT_LOAD_IA32_PAT           0x00080000
0099 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
0100 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
0101 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
0102 #define VM_EXIT_CLEAR_BNDCFGS                   0x00800000
0103 #define VM_EXIT_PT_CONCEAL_PIP          0x01000000
0104 #define VM_EXIT_CLEAR_IA32_RTIT_CTL     0x02000000
0105
0106 #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR   0x00036dff
0107
0108 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000004
0109 #define VM_ENTRY_IA32E_MODE                     0x00000200
0110 #define VM_ENTRY_SMM                            0x00000400
0111 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
0112 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
0113 #define VM_ENTRY_LOAD_IA32_PAT          0x00004000
0114 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
0115 #define VM_ENTRY_LOAD_BNDCFGS                   0x00010000
0116 #define VM_ENTRY_PT_CONCEAL_PIP         0x00020000
0117 #define VM_ENTRY_LOAD_IA32_RTIT_CTL     0x00040000
0118
0119 #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR  0x000011ff
0120
0121 #define VMX_MISC_PREEMPTION_TIMER_RATE_MASK 0x0000001f
0122 #define VMX_MISC_SAVE_EFER_LMA          0x00000020
0123 #define VMX_MISC_ACTIVITY_HLT           0x00000040
0124 #define VMX_MISC_ACTIVITY_WAIT_SIPI     0x00000100
0125 #define VMX_MISC_ZERO_LEN_INS           0x40000000
0126 #define VMX_MISC_MSR_LIST_MULTIPLIER        512
0127
0128 /* VMFUNC functions */
0129 #define VMFUNC_CONTROL_BIT(x)   BIT((VMX_FEATURE_##x & 0x1f) - 28)
0130
0131 #define VMX_VMFUNC_EPTP_SWITCHING               VMFUNC_CONTROL_BIT(EPTP_SWITCHING)
0132 #define VMFUNC_EPTP_ENTRIES  512
0133
0134 static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic)
0135 {
0136     return vmx_basic & GENMASK_ULL(30, 0);
0137 }
0138
0139 static inline u32 vmx_basic_vmcs_size(u64 vmx_basic)
0140 {
0141     return (vmx_basic & GENMASK_ULL(44, 32)) >> 32;
0142 }
0143
0144 static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc)
0145 {
0146     return vmx_misc & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
0147 }
0148
0149 static inline int vmx_misc_cr3_count(u64 vmx_misc)
0150 {
0151     return (vmx_misc & GENMASK_ULL(24, 16)) >> 16;
0152 }
0153
0154 static inline int vmx_misc_max_msr(u64 vmx_misc)
0155 {
0156     return (vmx_misc & GENMASK_ULL(27, 25)) >> 25;
0157 }
0158
0159 static inline int vmx_misc_mseg_revid(u64 vmx_misc)
0160 {
0161     return (vmx_misc & GENMASK_ULL(63, 32)) >> 32;
0162 }
0163
0164 /* VMCS Encodings */
0165 enum vmcs_field {
0166     VIRTUAL_PROCESSOR_ID            = 0x00000000,
0167     POSTED_INTR_NV                  = 0x00000002,
0168     LAST_PID_POINTER_INDEX      = 0x00000008,
0169     GUEST_ES_SELECTOR               = 0x00000800,
0170     GUEST_CS_SELECTOR               = 0x00000802,
0171     GUEST_SS_SELECTOR               = 0x00000804,
0172     GUEST_DS_SELECTOR               = 0x00000806,
0173     GUEST_FS_SELECTOR               = 0x00000808,
0174     GUEST_GS_SELECTOR               = 0x0000080a,
0175     GUEST_LDTR_SELECTOR             = 0x0000080c,
0176     GUEST_TR_SELECTOR               = 0x0000080e,
0177     GUEST_INTR_STATUS               = 0x00000810,
0178     GUEST_PML_INDEX         = 0x00000812,
0179     HOST_ES_SELECTOR                = 0x00000c00,
0180     HOST_CS_SELECTOR                = 0x00000c02,
0181     HOST_SS_SELECTOR                = 0x00000c04,
0182     HOST_DS_SELECTOR                = 0x00000c06,
0183     HOST_FS_SELECTOR                = 0x00000c08,
0184     HOST_GS_SELECTOR                = 0x00000c0a,
0185     HOST_TR_SELECTOR                = 0x00000c0c,
0186     IO_BITMAP_A                     = 0x00002000,
0187     IO_BITMAP_A_HIGH                = 0x00002001,
0188     IO_BITMAP_B                     = 0x00002002,
0189     IO_BITMAP_B_HIGH                = 0x00002003,
0190     MSR_BITMAP                      = 0x00002004,
0191     MSR_BITMAP_HIGH                 = 0x00002005,
0192     VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
0193     VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
0194     VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
0195     VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
0196     VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
0197     VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
0198     PML_ADDRESS         = 0x0000200e,
0199     PML_ADDRESS_HIGH        = 0x0000200f,
0200     TSC_OFFSET                      = 0x00002010,
0201     TSC_OFFSET_HIGH                 = 0x00002011,
0202     VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
0203     VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
0204     APIC_ACCESS_ADDR        = 0x00002014,
0205     APIC_ACCESS_ADDR_HIGH       = 0x00002015,
0206     POSTED_INTR_DESC_ADDR           = 0x00002016,
0207     POSTED_INTR_DESC_ADDR_HIGH      = 0x00002017,
0208     VM_FUNCTION_CONTROL             = 0x00002018,
0209     VM_FUNCTION_CONTROL_HIGH        = 0x00002019,
0210     EPT_POINTER                     = 0x0000201a,
0211     EPT_POINTER_HIGH                = 0x0000201b,
0212     EOI_EXIT_BITMAP0                = 0x0000201c,
0213     EOI_EXIT_BITMAP0_HIGH           = 0x0000201d,
0214     EOI_EXIT_BITMAP1                = 0x0000201e,
0215     EOI_EXIT_BITMAP1_HIGH           = 0x0000201f,
0216     EOI_EXIT_BITMAP2                = 0x00002020,
0217     EOI_EXIT_BITMAP2_HIGH           = 0x00002021,
0218     EOI_EXIT_BITMAP3                = 0x00002022,
0219     EOI_EXIT_BITMAP3_HIGH           = 0x00002023,
0220     EPTP_LIST_ADDRESS               = 0x00002024,
0221     EPTP_LIST_ADDRESS_HIGH          = 0x00002025,
0222     VMREAD_BITMAP                   = 0x00002026,
0223     VMREAD_BITMAP_HIGH              = 0x00002027,
0224     VMWRITE_BITMAP                  = 0x00002028,
0225     VMWRITE_BITMAP_HIGH             = 0x00002029,
0226     XSS_EXIT_BITMAP                 = 0x0000202C,
0227     XSS_EXIT_BITMAP_HIGH            = 0x0000202D,
0228     ENCLS_EXITING_BITMAP        = 0x0000202E,
0229     ENCLS_EXITING_BITMAP_HIGH   = 0x0000202F,
0230     TSC_MULTIPLIER                  = 0x00002032,
0231     TSC_MULTIPLIER_HIGH             = 0x00002033,
0232     TERTIARY_VM_EXEC_CONTROL    = 0x00002034,
0233     TERTIARY_VM_EXEC_CONTROL_HIGH   = 0x00002035,
0234     PID_POINTER_TABLE       = 0x00002042,
0235     PID_POINTER_TABLE_HIGH      = 0x00002043,
0236     GUEST_PHYSICAL_ADDRESS          = 0x00002400,
0237     GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
0238     VMCS_LINK_POINTER               = 0x00002800,
0239     VMCS_LINK_POINTER_HIGH          = 0x00002801,
0240     GUEST_IA32_DEBUGCTL             = 0x00002802,
0241     GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
0242     GUEST_IA32_PAT          = 0x00002804,
0243     GUEST_IA32_PAT_HIGH     = 0x00002805,
0244     GUEST_IA32_EFER         = 0x00002806,
0245     GUEST_IA32_EFER_HIGH        = 0x00002807,
0246     GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
0247     GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
0248     GUEST_PDPTR0                    = 0x0000280a,
0249     GUEST_PDPTR0_HIGH               = 0x0000280b,
0250     GUEST_PDPTR1                    = 0x0000280c,
0251     GUEST_PDPTR1_HIGH               = 0x0000280d,
0252     GUEST_PDPTR2                    = 0x0000280e,
0253     GUEST_PDPTR2_HIGH               = 0x0000280f,
0254     GUEST_PDPTR3                    = 0x00002810,
0255     GUEST_PDPTR3_HIGH               = 0x00002811,
0256     GUEST_BNDCFGS                   = 0x00002812,
0257     GUEST_BNDCFGS_HIGH              = 0x00002813,
0258     GUEST_IA32_RTIT_CTL     = 0x00002814,
0259     GUEST_IA32_RTIT_CTL_HIGH    = 0x00002815,
0260     HOST_IA32_PAT           = 0x00002c00,
0261     HOST_IA32_PAT_HIGH      = 0x00002c01,
0262     HOST_IA32_EFER          = 0x00002c02,
0263     HOST_IA32_EFER_HIGH     = 0x00002c03,
0264     HOST_IA32_PERF_GLOBAL_CTRL  = 0x00002c04,
0265     HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
0266     PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
0267     CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
0268     EXCEPTION_BITMAP                = 0x00004004,
0269     PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
0270     PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
0271     CR3_TARGET_COUNT                = 0x0000400a,
0272     VM_EXIT_CONTROLS                = 0x0000400c,
0273     VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
0274     VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
0275     VM_ENTRY_CONTROLS               = 0x00004012,
0276     VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
0277     VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
0278     VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
0279     VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
0280     TPR_THRESHOLD                   = 0x0000401c,
0281     SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
0282     PLE_GAP                         = 0x00004020,
0283     PLE_WINDOW                      = 0x00004022,
0284     NOTIFY_WINDOW                   = 0x00004024,
0285     VM_INSTRUCTION_ERROR            = 0x00004400,
0286     VM_EXIT_REASON                  = 0x00004402,
0287     VM_EXIT_INTR_INFO               = 0x00004404,
0288     VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
0289     IDT_VECTORING_INFO_FIELD        = 0x00004408,
0290     IDT_VECTORING_ERROR_CODE        = 0x0000440a,
0291     VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
0292     VMX_INSTRUCTION_INFO            = 0x0000440e,
0293     GUEST_ES_LIMIT                  = 0x00004800,
0294     GUEST_CS_LIMIT                  = 0x00004802,
0295     GUEST_SS_LIMIT                  = 0x00004804,
0296     GUEST_DS_LIMIT                  = 0x00004806,
0297     GUEST_FS_LIMIT                  = 0x00004808,
0298     GUEST_GS_LIMIT                  = 0x0000480a,
0299     GUEST_LDTR_LIMIT                = 0x0000480c,
0300     GUEST_TR_LIMIT                  = 0x0000480e,
0301     GUEST_GDTR_LIMIT                = 0x00004810,
0302     GUEST_IDTR_LIMIT                = 0x00004812,
0303     GUEST_ES_AR_BYTES               = 0x00004814,
0304     GUEST_CS_AR_BYTES               = 0x00004816,
0305     GUEST_SS_AR_BYTES               = 0x00004818,
0306     GUEST_DS_AR_BYTES               = 0x0000481a,
0307     GUEST_FS_AR_BYTES               = 0x0000481c,
0308     GUEST_GS_AR_BYTES               = 0x0000481e,
0309     GUEST_LDTR_AR_BYTES             = 0x00004820,
0310     GUEST_TR_AR_BYTES               = 0x00004822,
0311     GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
0312     GUEST_ACTIVITY_STATE            = 0X00004826,
0313     GUEST_SYSENTER_CS               = 0x0000482A,
0314     VMX_PREEMPTION_TIMER_VALUE      = 0x0000482E,
0315     HOST_IA32_SYSENTER_CS           = 0x00004c00,
0316     CR0_GUEST_HOST_MASK             = 0x00006000,
0317     CR4_GUEST_HOST_MASK             = 0x00006002,
0318     CR0_READ_SHADOW                 = 0x00006004,
0319     CR4_READ_SHADOW                 = 0x00006006,
0320     CR3_TARGET_VALUE0               = 0x00006008,
0321     CR3_TARGET_VALUE1               = 0x0000600a,
0322     CR3_TARGET_VALUE2               = 0x0000600c,
0323     CR3_TARGET_VALUE3               = 0x0000600e,
0324     EXIT_QUALIFICATION              = 0x00006400,
0325     GUEST_LINEAR_ADDRESS            = 0x0000640a,
0326     GUEST_CR0                       = 0x00006800,
0327     GUEST_CR3                       = 0x00006802,
0328     GUEST_CR4                       = 0x00006804,
0329     GUEST_ES_BASE                   = 0x00006806,
0330     GUEST_CS_BASE                   = 0x00006808,
0331     GUEST_SS_BASE                   = 0x0000680a,
0332     GUEST_DS_BASE                   = 0x0000680c,
0333     GUEST_FS_BASE                   = 0x0000680e,
0334     GUEST_GS_BASE                   = 0x00006810,
0335     GUEST_LDTR_BASE                 = 0x00006812,
0336     GUEST_TR_BASE                   = 0x00006814,
0337     GUEST_GDTR_BASE                 = 0x00006816,
0338     GUEST_IDTR_BASE                 = 0x00006818,
0339     GUEST_DR7                       = 0x0000681a,
0340     GUEST_RSP                       = 0x0000681c,
0341     GUEST_RIP                       = 0x0000681e,
0342     GUEST_RFLAGS                    = 0x00006820,
0343     GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
0344     GUEST_SYSENTER_ESP              = 0x00006824,
0345     GUEST_SYSENTER_EIP              = 0x00006826,
0346     HOST_CR0                        = 0x00006c00,
0347     HOST_CR3                        = 0x00006c02,
0348     HOST_CR4                        = 0x00006c04,
0349     HOST_FS_BASE                    = 0x00006c06,
0350     HOST_GS_BASE                    = 0x00006c08,
0351     HOST_TR_BASE                    = 0x00006c0a,
0352     HOST_GDTR_BASE                  = 0x00006c0c,
0353     HOST_IDTR_BASE                  = 0x00006c0e,
0354     HOST_IA32_SYSENTER_ESP          = 0x00006c10,
0355     HOST_IA32_SYSENTER_EIP          = 0x00006c12,
0356     HOST_RSP                        = 0x00006c14,
0357     HOST_RIP                        = 0x00006c16,
0358 };
0359
0360 /*
0361  * Interruption-information format
0362  */
0363 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
0364 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
0365 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
0366 #define INTR_INFO_UNBLOCK_NMI       0x1000      /* 12 */
0367 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
0368 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
0369
0370 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
0371 #define VECTORING_INFO_TYPE_MASK            INTR_INFO_INTR_TYPE_MASK
0372 #define VECTORING_INFO_DELIVER_CODE_MASK        INTR_INFO_DELIVER_CODE_MASK
0373 #define VECTORING_INFO_VALID_MASK           INTR_INFO_VALID_MASK
0374
0375 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
0376 #define INTR_TYPE_RESERVED              (1 << 8) /* reserved */
0377 #define INTR_TYPE_NMI_INTR      (2 << 8) /* NMI */
0378 #define INTR_TYPE_HARD_EXCEPTION    (3 << 8) /* processor exception */
0379 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
0380 #define INTR_TYPE_PRIV_SW_EXCEPTION (5 << 8) /* ICE breakpoint - undocumented */
0381 #define INTR_TYPE_SOFT_EXCEPTION    (6 << 8) /* software exception */
0382 #define INTR_TYPE_OTHER_EVENT           (7 << 8) /* other event */
0383
0384 /* GUEST_INTERRUPTIBILITY_INFO flags. */
0385 #define GUEST_INTR_STATE_STI        0x00000001
0386 #define GUEST_INTR_STATE_MOV_SS     0x00000002
0387 #define GUEST_INTR_STATE_SMI        0x00000004
0388 #define GUEST_INTR_STATE_NMI        0x00000008
0389 #define GUEST_INTR_STATE_ENCLAVE_INTR   0x00000010
0390
0391 /* GUEST_ACTIVITY_STATE flags */
0392 #define GUEST_ACTIVITY_ACTIVE       0
0393 #define GUEST_ACTIVITY_HLT      1
0394 #define GUEST_ACTIVITY_SHUTDOWN     2
0395 #define GUEST_ACTIVITY_WAIT_SIPI    3
0396
0397 /*
0398  * Exit Qualifications for MOV for Control Register Access
0399  */
0400 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
0401 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
0402 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
0403 #define LMSW_SOURCE_DATA_SHIFT 16
0404 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
0405 #define REG_EAX                         (0 << 8)
0406 #define REG_ECX                         (1 << 8)
0407 #define REG_EDX                         (2 << 8)
0408 #define REG_EBX                         (3 << 8)
0409 #define REG_ESP                         (4 << 8)
0410 #define REG_EBP                         (5 << 8)
0411 #define REG_ESI                         (6 << 8)
0412 #define REG_EDI                         (7 << 8)
0413 #define REG_R8                         (8 << 8)
0414 #define REG_R9                         (9 << 8)
0415 #define REG_R10                        (10 << 8)
0416 #define REG_R11                        (11 << 8)
0417 #define REG_R12                        (12 << 8)
0418 #define REG_R13                        (13 << 8)
0419 #define REG_R14                        (14 << 8)
0420 #define REG_R15                        (15 << 8)
0421
0422 /*
0423  * Exit Qualifications for MOV for Debug Register Access
0424  */
0425 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
0426 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
0427 #define TYPE_MOV_TO_DR                  (0 << 4)
0428 #define TYPE_MOV_FROM_DR                (1 << 4)
0429 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
0430
0431
0432 /*
0433  * Exit Qualifications for APIC-Access
0434  */
0435 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
0436 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
0437 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
0438 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
0439 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
0440 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
0441 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
0442 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
0443
0444 /* segment AR in VMCS -- these are different from what LAR reports */
0445 #define VMX_SEGMENT_AR_L_MASK (1 << 13)
0446
0447 #define VMX_AR_TYPE_ACCESSES_MASK 1
0448 #define VMX_AR_TYPE_READABLE_MASK (1 << 1)
0449 #define VMX_AR_TYPE_WRITEABLE_MASK (1 << 2)
0450 #define VMX_AR_TYPE_CODE_MASK (1 << 3)
0451 #define VMX_AR_TYPE_MASK 0x0f
0452 #define VMX_AR_TYPE_BUSY_64_TSS 11
0453 #define VMX_AR_TYPE_BUSY_32_TSS 11
0454 #define VMX_AR_TYPE_BUSY_16_TSS 3
0455 #define VMX_AR_TYPE_LDT 2
0456
0457 #define VMX_AR_UNUSABLE_MASK (1 << 16)
0458 #define VMX_AR_S_MASK (1 << 4)
0459 #define VMX_AR_P_MASK (1 << 7)
0460 #define VMX_AR_L_MASK (1 << 13)
0461 #define VMX_AR_DB_MASK (1 << 14)
0462 #define VMX_AR_G_MASK (1 << 15)
0463 #define VMX_AR_DPL_SHIFT 5
0464 #define VMX_AR_DPL(ar) (((ar) >> VMX_AR_DPL_SHIFT) & 3)
0465
0466 #define VMX_AR_RESERVD_MASK 0xfffe0f00
0467
0468 #define TSS_PRIVATE_MEMSLOT         (KVM_USER_MEM_SLOTS + 0)
0469 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT    (KVM_USER_MEM_SLOTS + 1)
0470 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT  (KVM_USER_MEM_SLOTS + 2)
0471
0472 #define VMX_NR_VPIDS                (1 << 16)
0473 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR     0
0474 #define VMX_VPID_EXTENT_SINGLE_CONTEXT      1
0475 #define VMX_VPID_EXTENT_ALL_CONTEXT     2
0476 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL   3
0477
0478 #define VMX_EPT_EXTENT_CONTEXT          1
0479 #define VMX_EPT_EXTENT_GLOBAL           2
0480 #define VMX_EPT_EXTENT_SHIFT            24
0481
0482 #define VMX_EPT_EXECUTE_ONLY_BIT        (1ull)
0483 #define VMX_EPT_PAGE_WALK_4_BIT         (1ull << 6)
0484 #define VMX_EPT_PAGE_WALK_5_BIT         (1ull << 7)
0485 #define VMX_EPTP_UC_BIT             (1ull << 8)
0486 #define VMX_EPTP_WB_BIT             (1ull << 14)
0487 #define VMX_EPT_2MB_PAGE_BIT            (1ull << 16)
0488 #define VMX_EPT_1GB_PAGE_BIT            (1ull << 17)
0489 #define VMX_EPT_INVEPT_BIT          (1ull << 20)
0490 #define VMX_EPT_AD_BIT                  (1ull << 21)
0491 #define VMX_EPT_EXTENT_CONTEXT_BIT      (1ull << 25)
0492 #define VMX_EPT_EXTENT_GLOBAL_BIT       (1ull << 26)
0493
0494 #define VMX_VPID_INVVPID_BIT                    (1ull << 0) /* (32 - 32) */
0495 #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT     (1ull << 8) /* (40 - 32) */
0496 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
0497 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
0498 #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT   (1ull << 11) /* (43 - 32) */
0499
0500 #define VMX_EPT_MT_EPTE_SHIFT           3
0501 #define VMX_EPTP_PWL_MASK           0x38ull
0502 #define VMX_EPTP_PWL_4              0x18ull
0503 #define VMX_EPTP_PWL_5              0x20ull
0504 #define VMX_EPTP_AD_ENABLE_BIT          (1ull << 6)
0505 #define VMX_EPTP_MT_MASK            0x7ull
0506 #define VMX_EPTP_MT_WB              0x6ull
0507 #define VMX_EPTP_MT_UC              0x0ull
0508 #define VMX_EPT_READABLE_MASK           0x1ull
0509 #define VMX_EPT_WRITABLE_MASK           0x2ull
0510 #define VMX_EPT_EXECUTABLE_MASK         0x4ull
0511 #define VMX_EPT_IPAT_BIT                (1ull << 6)
0512 #define VMX_EPT_ACCESS_BIT          (1ull << 8)
0513 #define VMX_EPT_DIRTY_BIT           (1ull << 9)
0514 #define VMX_EPT_RWX_MASK                        (VMX_EPT_READABLE_MASK |       \
0515                          VMX_EPT_WRITABLE_MASK |       \
0516                          VMX_EPT_EXECUTABLE_MASK)
0517 #define VMX_EPT_MT_MASK             (7ull << VMX_EPT_MT_EPTE_SHIFT)
0518
0519 static inline u8 vmx_eptp_page_walk_level(u64 eptp)
0520 {
0521     u64 encoded_level = eptp & VMX_EPTP_PWL_MASK;
0522
0523     if (encoded_level == VMX_EPTP_PWL_5)
0524         return 5;
0525
0526     /* @eptp must be pre-validated by the caller. */
0527     WARN_ON_ONCE(encoded_level != VMX_EPTP_PWL_4);
0528     return 4;
0529 }
0530
0531 /* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */
0532 #define VMX_EPT_MISCONFIG_WX_VALUE      (VMX_EPT_WRITABLE_MASK |       \
0533                          VMX_EPT_EXECUTABLE_MASK)
0534
0535 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR     0xfffbc000ul
0536
0537 struct vmx_msr_entry {
0538     u32 index;
0539     u32 reserved;
0540     u64 value;
0541 } __aligned(16);
0542
0543 /*
0544  * Exit Qualifications for entry failure during or after loading guest state
0545  */
0546 enum vm_entry_failure_code {
0547     ENTRY_FAIL_DEFAULT      = 0,
0548     ENTRY_FAIL_PDPTE        = 2,
0549     ENTRY_FAIL_NMI          = 3,
0550     ENTRY_FAIL_VMCS_LINK_PTR    = 4,
0551 };
0552
0553 /*
0554  * Exit Qualifications for EPT Violations
0555  */
0556 #define EPT_VIOLATION_ACC_READ_BIT  0
0557 #define EPT_VIOLATION_ACC_WRITE_BIT 1
0558 #define EPT_VIOLATION_ACC_INSTR_BIT 2
0559 #define EPT_VIOLATION_RWX_SHIFT     3
0560 #define EPT_VIOLATION_GVA_IS_VALID_BIT  7
0561 #define EPT_VIOLATION_GVA_TRANSLATED_BIT 8
0562 #define EPT_VIOLATION_ACC_READ      (1 << EPT_VIOLATION_ACC_READ_BIT)
0563 #define EPT_VIOLATION_ACC_WRITE     (1 << EPT_VIOLATION_ACC_WRITE_BIT)
0564 #define EPT_VIOLATION_ACC_INSTR     (1 << EPT_VIOLATION_ACC_INSTR_BIT)
0565 #define EPT_VIOLATION_RWX_MASK      (VMX_EPT_RWX_MASK << EPT_VIOLATION_RWX_SHIFT)
0566 #define EPT_VIOLATION_GVA_IS_VALID  (1 << EPT_VIOLATION_GVA_IS_VALID_BIT)
0567 #define EPT_VIOLATION_GVA_TRANSLATED    (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT)
0568
0569 /*
0570  * Exit Qualifications for NOTIFY VM EXIT
0571  */
0572 #define NOTIFY_VM_CONTEXT_INVALID     BIT(0)
0573
0574 /*
0575  * VM-instruction error numbers
0576  */
0577 enum vm_instruction_error_number {
0578     VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
0579     VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
0580     VMXERR_VMCLEAR_VMXON_POINTER = 3,
0581     VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
0582     VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
0583     VMXERR_VMRESUME_AFTER_VMXOFF = 6,
0584     VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
0585     VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
0586     VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
0587     VMXERR_VMPTRLD_VMXON_POINTER = 10,
0588     VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
0589     VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
0590     VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
0591     VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
0592     VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
0593     VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
0594     VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
0595     VMXERR_VMCALL_NONCLEAR_VMCS = 19,
0596     VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
0597     VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
0598     VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
0599     VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
0600     VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
0601     VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
0602     VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
0603 };
0604
0605 /*
0606  * VM-instruction errors that can be encountered on VM-Enter, used to trace
0607  * nested VM-Enter failures reported by hardware.  Errors unique to VM-Enter
0608  * from a SMI Transfer Monitor are not included as things have gone seriously
0609  * sideways if we get one of those...
0610  */
0611 #define VMX_VMENTER_INSTRUCTION_ERRORS \
0612     { VMXERR_VMLAUNCH_NONCLEAR_VMCS,        "VMLAUNCH_NONCLEAR_VMCS" }, \
0613     { VMXERR_VMRESUME_NONLAUNCHED_VMCS,     "VMRESUME_NONLAUNCHED_VMCS" }, \
0614     { VMXERR_VMRESUME_AFTER_VMXOFF,         "VMRESUME_AFTER_VMXOFF" }, \
0615     { VMXERR_ENTRY_INVALID_CONTROL_FIELD,       "VMENTRY_INVALID_CONTROL_FIELD" }, \
0616     { VMXERR_ENTRY_INVALID_HOST_STATE_FIELD,    "VMENTRY_INVALID_HOST_STATE_FIELD" }, \
0617     { VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS,    "VMENTRY_EVENTS_BLOCKED_BY_MOV_SS" }
0618
0619 enum vmx_l1d_flush_state {
0620     VMENTER_L1D_FLUSH_AUTO,
0621     VMENTER_L1D_FLUSH_NEVER,
0622     VMENTER_L1D_FLUSH_COND,
0623     VMENTER_L1D_FLUSH_ALWAYS,
0624     VMENTER_L1D_FLUSH_EPT_DISABLED,
0625     VMENTER_L1D_FLUSH_NOT_REQUIRED,
0626 };
0627
0628 extern enum vmx_l1d_flush_state l1tf_vmx_mitigation;
0629
0630 #endif