asm/uv/uv_hub.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * SGI UV architectural definitions
0007  *
0008  * (C) Copyright 2020 Hewlett Packard Enterprise Development LP
0009  * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved.
0010  */
0011
0012 #ifndef _ASM_X86_UV_UV_HUB_H
0013 #define _ASM_X86_UV_UV_HUB_H
0014
0015 #ifdef CONFIG_X86_64
0016 #include <linux/numa.h>
0017 #include <linux/percpu.h>
0018 #include <linux/timer.h>
0019 #include <linux/io.h>
0020 #include <linux/topology.h>
0021 #include <asm/types.h>
0022 #include <asm/percpu.h>
0023 #include <asm/uv/uv.h>
0024 #include <asm/uv/uv_mmrs.h>
0025 #include <asm/uv/bios.h>
0026 #include <asm/irq_vectors.h>
0027 #include <asm/io_apic.h>
0028
0029
0030 /*
0031  * Addressing Terminology
0032  *
0033  *  M       - The low M bits of a physical address represent the offset
0034  *        into the blade local memory. RAM memory on a blade is physically
0035  *        contiguous (although various IO spaces may punch holes in
0036  *        it)..
0037  *
0038  *  N   - Number of bits in the node portion of a socket physical
0039  *        address.
0040  *
0041  *  NASID   - network ID of a router, Mbrick or Cbrick. Nasid values of
0042  *        routers always have low bit of 1, C/MBricks have low bit
0043  *        equal to 0. Most addressing macros that target UV hub chips
0044  *        right shift the NASID by 1 to exclude the always-zero bit.
0045  *        NASIDs contain up to 15 bits.
0046  *
0047  *  GNODE   - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
0048  *        of nasids.
0049  *
0050  *  PNODE   - the low N bits of the GNODE. The PNODE is the most useful variant
0051  *        of the nasid for socket usage.
0052  *
0053  *  GPA - (global physical address) a socket physical address converted
0054  *        so that it can be used by the GRU as a global address. Socket
0055  *        physical addresses 1) need additional NASID (node) bits added
0056  *        to the high end of the address, and 2) unaliased if the
0057  *        partition does not have a physical address 0. In addition, on
0058  *        UV2 rev 1, GPAs need the gnode left shifted to bits 39 or 40.
0059  *
0060  *
0061  *  NumaLink Global Physical Address Format:
0062  *  +--------------------------------+---------------------+
0063  *  |00..000|      GNODE             |      NodeOffset     |
0064  *  +--------------------------------+---------------------+
0065  *          |<-------53 - M bits --->|<--------M bits ----->
0066  *
0067  *  M - number of node offset bits (35 .. 40)
0068  *
0069  *
0070  *  Memory/UV-HUB Processor Socket Address Format:
0071  *  +----------------+---------------+---------------------+
0072  *  |00..000000000000|   PNODE       |      NodeOffset     |
0073  *  +----------------+---------------+---------------------+
0074  *                   <--- N bits --->|<--------M bits ----->
0075  *
0076  *  M - number of node offset bits (35 .. 40)
0077  *  N - number of PNODE bits (0 .. 10)
0078  *
0079  *      Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
0080  *      The actual values are configuration dependent and are set at
0081  *      boot time. M & N values are set by the hardware/BIOS at boot.
0082  *
0083  *
0084  * APICID format
0085  *  NOTE!!!!!! This is the current format of the APICID. However, code
0086  *  should assume that this will change in the future. Use functions
0087  *  in this file for all APICID bit manipulations and conversion.
0088  *
0089  *      1111110000000000
0090  *      5432109876543210
0091  *      pppppppppplc0cch    Nehalem-EX (12 bits in hdw reg)
0092  *      ppppppppplcc0cch    Westmere-EX (12 bits in hdw reg)
0093  *      pppppppppppcccch    SandyBridge (15 bits in hdw reg)
0094  *      sssssssssss
0095  *
0096  *          p  = pnode bits
0097  *          l =  socket number on board
0098  *          c  = core
0099  *          h  = hyperthread
0100  *          s  = bits that are in the SOCKET_ID CSR
0101  *
0102  *  Note: Processor may support fewer bits in the APICID register. The ACPI
0103  *        tables hold all 16 bits. Software needs to be aware of this.
0104  *
0105  *        Unless otherwise specified, all references to APICID refer to
0106  *        the FULL value contained in ACPI tables, not the subset in the
0107  *        processor APICID register.
0108  */
0109
0110 /*
0111  * Maximum number of bricks in all partitions and in all coherency domains.
0112  * This is the total number of bricks accessible in the numalink fabric. It
0113  * includes all C & M bricks. Routers are NOT included.
0114  *
0115  * This value is also the value of the maximum number of non-router NASIDs
0116  * in the numalink fabric.
0117  *
0118  * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
0119  */
0120 #define UV_MAX_NUMALINK_BLADES  16384
0121
0122 /*
0123  * Maximum number of C/Mbricks within a software SSI (hardware may support
0124  * more).
0125  */
0126 #define UV_MAX_SSI_BLADES   256
0127
0128 /*
0129  * The largest possible NASID of a C or M brick (+ 2)
0130  */
0131 #define UV_MAX_NASID_VALUE  (UV_MAX_NUMALINK_BLADES * 2)
0132
0133 /* GAM (globally addressed memory) range table */
0134 struct uv_gam_range_s {
0135     u32 limit;      /* PA bits 56:26 (GAM_RANGE_SHFT) */
0136     u16 nasid;      /* node's global physical address */
0137     s8  base;       /* entry index of node's base addr */
0138     u8  reserved;
0139 };
0140
0141 /*
0142  * The following defines attributes of the HUB chip. These attributes are
0143  * frequently referenced and are kept in a common per hub struct.
0144  * After setup, the struct is read only, so it should be readily
0145  * available in the L3 cache on the cpu socket for the node.
0146  */
0147 struct uv_hub_info_s {
0148     unsigned int        hub_type;
0149     unsigned char       hub_revision;
0150     unsigned long       global_mmr_base;
0151     unsigned long       global_mmr_shift;
0152     unsigned long       gpa_mask;
0153     unsigned short      *socket_to_node;
0154     unsigned short      *socket_to_pnode;
0155     unsigned short      *pnode_to_socket;
0156     struct uv_gam_range_s   *gr_table;
0157     unsigned short      min_socket;
0158     unsigned short      min_pnode;
0159     unsigned char       m_val;
0160     unsigned char       n_val;
0161     unsigned char       gr_table_len;
0162     unsigned char       apic_pnode_shift;
0163     unsigned char       gpa_shift;
0164     unsigned char       nasid_shift;
0165     unsigned char       m_shift;
0166     unsigned char       n_lshift;
0167     unsigned int        gnode_extra;
0168     unsigned long       gnode_upper;
0169     unsigned long       lowmem_remap_top;
0170     unsigned long       lowmem_remap_base;
0171     unsigned long       global_gru_base;
0172     unsigned long       global_gru_shift;
0173     unsigned short      pnode;
0174     unsigned short      pnode_mask;
0175     unsigned short      coherency_domain_number;
0176     unsigned short      numa_blade_id;
0177     unsigned short      nr_possible_cpus;
0178     unsigned short      nr_online_cpus;
0179     short           memory_nid;
0180 };
0181
0182 /* CPU specific info with a pointer to the hub common info struct */
0183 struct uv_cpu_info_s {
0184     void            *p_uv_hub_info;
0185     unsigned char       blade_cpu_id;
0186     void            *reserved;
0187 };
0188 DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
0189
0190 #define uv_cpu_info     this_cpu_ptr(&__uv_cpu_info)
0191 #define uv_cpu_info_per(cpu)    (&per_cpu(__uv_cpu_info, cpu))
0192
0193 /* Node specific hub common info struct */
0194 extern void **__uv_hub_info_list;
0195 static inline struct uv_hub_info_s *uv_hub_info_list(int node)
0196 {
0197     return (struct uv_hub_info_s *)__uv_hub_info_list[node];
0198 }
0199
0200 static inline struct uv_hub_info_s *_uv_hub_info(void)
0201 {
0202     return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info;
0203 }
0204 #define uv_hub_info _uv_hub_info()
0205
0206 static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu)
0207 {
0208     return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info;
0209 }
0210
0211 static inline int uv_hub_type(void)
0212 {
0213     return uv_hub_info->hub_type;
0214 }
0215
0216 static inline __init void uv_hub_type_set(int uvmask)
0217 {
0218     uv_hub_info->hub_type = uvmask;
0219 }
0220
0221
0222 /*
0223  * HUB revision ranges for each UV HUB architecture.
0224  * This is a software convention - NOT the hardware revision numbers in
0225  * the hub chip.
0226  */
0227 #define UV2_HUB_REVISION_BASE       3
0228 #define UV3_HUB_REVISION_BASE       5
0229 #define UV4_HUB_REVISION_BASE       7
0230 #define UV4A_HUB_REVISION_BASE      8   /* UV4 (fixed) rev 2 */
0231 #define UV5_HUB_REVISION_BASE       9
0232
0233 static inline int is_uv(int uvmask) { return uv_hub_type() & uvmask; }
0234 static inline int is_uv1_hub(void) { return 0; }
0235 static inline int is_uv2_hub(void) { return is_uv(UV2); }
0236 static inline int is_uv3_hub(void) { return is_uv(UV3); }
0237 static inline int is_uv4a_hub(void) { return is_uv(UV4A); }
0238 static inline int is_uv4_hub(void) { return is_uv(UV4); }
0239 static inline int is_uv5_hub(void) { return is_uv(UV5); }
0240
0241 /*
0242  * UV4A is a revision of UV4.  So on UV4A, both is_uv4_hub() and
0243  * is_uv4a_hub() return true, While on UV4, only is_uv4_hub()
0244  * returns true.  So to get true results, first test if is UV4A,
0245  * then test if is UV4.
0246  */
0247
0248 /* UVX class: UV2,3,4 */
0249 static inline int is_uvx_hub(void) { return is_uv(UVX); }
0250
0251 /* UVY class: UV5,..? */
0252 static inline int is_uvy_hub(void) { return is_uv(UVY); }
0253
0254 /* Any UV Hubbed System */
0255 static inline int is_uv_hub(void) { return is_uv(UV_ANY); }
0256
0257 union uvh_apicid {
0258     unsigned long       v;
0259     struct uvh_apicid_s {
0260         unsigned long   local_apic_mask  : 24;
0261         unsigned long   local_apic_shift :  5;
0262         unsigned long   unused1          :  3;
0263         unsigned long   pnode_mask       : 24;
0264         unsigned long   pnode_shift      :  5;
0265         unsigned long   unused2          :  3;
0266     } s;
0267 };
0268
0269 /*
0270  * Local & Global MMR space macros.
0271  *  Note: macros are intended to be used ONLY by inline functions
0272  *  in this file - not by other kernel code.
0273  *      n -  NASID (full 15-bit global nasid)
0274  *      g -  GNODE (full 15-bit global nasid, right shifted 1)
0275  *      p -  PNODE (local part of nsids, right shifted 1)
0276  */
0277 #define UV_NASID_TO_PNODE(n)        \
0278         (((n) >> uv_hub_info->nasid_shift) & uv_hub_info->pnode_mask)
0279 #define UV_PNODE_TO_GNODE(p)        ((p) |uv_hub_info->gnode_extra)
0280 #define UV_PNODE_TO_NASID(p)        \
0281         (UV_PNODE_TO_GNODE(p) << uv_hub_info->nasid_shift)
0282
0283 #define UV2_LOCAL_MMR_BASE      0xfa000000UL
0284 #define UV2_GLOBAL_MMR32_BASE       0xfc000000UL
0285 #define UV2_LOCAL_MMR_SIZE      (32UL * 1024 * 1024)
0286 #define UV2_GLOBAL_MMR32_SIZE       (32UL * 1024 * 1024)
0287
0288 #define UV3_LOCAL_MMR_BASE      0xfa000000UL
0289 #define UV3_GLOBAL_MMR32_BASE       0xfc000000UL
0290 #define UV3_LOCAL_MMR_SIZE      (32UL * 1024 * 1024)
0291 #define UV3_GLOBAL_MMR32_SIZE       (32UL * 1024 * 1024)
0292
0293 #define UV4_LOCAL_MMR_BASE      0xfa000000UL
0294 #define UV4_GLOBAL_MMR32_BASE       0
0295 #define UV4_LOCAL_MMR_SIZE      (32UL * 1024 * 1024)
0296 #define UV4_GLOBAL_MMR32_SIZE       0
0297
0298 #define UV5_LOCAL_MMR_BASE      0xfa000000UL
0299 #define UV5_GLOBAL_MMR32_BASE       0
0300 #define UV5_LOCAL_MMR_SIZE      (32UL * 1024 * 1024)
0301 #define UV5_GLOBAL_MMR32_SIZE       0
0302
0303 #define UV_LOCAL_MMR_BASE       (               \
0304                     is_uv(UV2) ? UV2_LOCAL_MMR_BASE : \
0305                     is_uv(UV3) ? UV3_LOCAL_MMR_BASE : \
0306                     is_uv(UV4) ? UV4_LOCAL_MMR_BASE : \
0307                     is_uv(UV5) ? UV5_LOCAL_MMR_BASE : \
0308                     0)
0309
0310 #define UV_GLOBAL_MMR32_BASE        (               \
0311                     is_uv(UV2) ? UV2_GLOBAL_MMR32_BASE : \
0312                     is_uv(UV3) ? UV3_GLOBAL_MMR32_BASE : \
0313                     is_uv(UV4) ? UV4_GLOBAL_MMR32_BASE : \
0314                     is_uv(UV5) ? UV5_GLOBAL_MMR32_BASE : \
0315                     0)
0316
0317 #define UV_LOCAL_MMR_SIZE       (               \
0318                     is_uv(UV2) ? UV2_LOCAL_MMR_SIZE : \
0319                     is_uv(UV3) ? UV3_LOCAL_MMR_SIZE : \
0320                     is_uv(UV4) ? UV4_LOCAL_MMR_SIZE : \
0321                     is_uv(UV5) ? UV5_LOCAL_MMR_SIZE : \
0322                     0)
0323
0324 #define UV_GLOBAL_MMR32_SIZE        (               \
0325                     is_uv(UV2) ? UV2_GLOBAL_MMR32_SIZE : \
0326                     is_uv(UV3) ? UV3_GLOBAL_MMR32_SIZE : \
0327                     is_uv(UV4) ? UV4_GLOBAL_MMR32_SIZE : \
0328                     is_uv(UV5) ? UV5_GLOBAL_MMR32_SIZE : \
0329                     0)
0330
0331 #define UV_GLOBAL_MMR64_BASE        (uv_hub_info->global_mmr_base)
0332
0333 #define UV_GLOBAL_GRU_MMR_BASE      0x4000000
0334
0335 #define UV_GLOBAL_MMR32_PNODE_SHIFT 15
0336 #define _UV_GLOBAL_MMR64_PNODE_SHIFT    26
0337 #define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift)
0338
0339 #define UV_GLOBAL_MMR32_PNODE_BITS(p)   ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
0340
0341 #define UV_GLOBAL_MMR64_PNODE_BITS(p)                   \
0342     (((unsigned long)(p)) << UV_GLOBAL_MMR64_PNODE_SHIFT)
0343
0344 #define UVH_APICID      0x002D0E00L
0345 #define UV_APIC_PNODE_SHIFT 6
0346
0347 /* Local Bus from cpu's perspective */
0348 #define LOCAL_BUS_BASE      0x1c00000
0349 #define LOCAL_BUS_SIZE      (4 * 1024 * 1024)
0350
0351 /*
0352  * System Controller Interface Reg
0353  *
0354  * Note there are NO leds on a UV system.  This register is only
0355  * used by the system controller to monitor system-wide operation.
0356  * There are 64 regs per node.  With Nehalem cpus (2 cores per node,
0357  * 8 cpus per core, 2 threads per cpu) there are 32 cpu threads on
0358  * a node.
0359  *
0360  * The window is located at top of ACPI MMR space
0361  */
0362 #define SCIR_WINDOW_COUNT   64
0363 #define SCIR_LOCAL_MMR_BASE (LOCAL_BUS_BASE + \
0364                  LOCAL_BUS_SIZE - \
0365                  SCIR_WINDOW_COUNT)
0366
0367 #define SCIR_CPU_HEARTBEAT  0x01    /* timer interrupt */
0368 #define SCIR_CPU_ACTIVITY   0x02    /* not idle */
0369 #define SCIR_CPU_HB_INTERVAL    (HZ)    /* once per second */
0370
0371 /* Loop through all installed blades */
0372 #define for_each_possible_blade(bid)        \
0373     for ((bid) = 0; (bid) < uv_num_possible_blades(); (bid)++)
0374
0375 /*
0376  * Macros for converting between kernel virtual addresses, socket local physical
0377  * addresses, and UV global physical addresses.
0378  *  Note: use the standard __pa() & __va() macros for converting
0379  *        between socket virtual and socket physical addresses.
0380  */
0381
0382 /* global bits offset - number of local address bits in gpa for this UV arch */
0383 static inline unsigned int uv_gpa_shift(void)
0384 {
0385     return uv_hub_info->gpa_shift;
0386 }
0387 #define _uv_gpa_shift
0388
0389 /* Find node that has the address range that contains global address  */
0390 static inline struct uv_gam_range_s *uv_gam_range(unsigned long pa)
0391 {
0392     struct uv_gam_range_s *gr = uv_hub_info->gr_table;
0393     unsigned long pal = (pa & uv_hub_info->gpa_mask) >> UV_GAM_RANGE_SHFT;
0394     int i, num = uv_hub_info->gr_table_len;
0395
0396     if (gr) {
0397         for (i = 0; i < num; i++, gr++) {
0398             if (pal < gr->limit)
0399                 return gr;
0400         }
0401     }
0402     pr_crit("UV: GAM Range for 0x%lx not found at %p!\n", pa, gr);
0403     BUG();
0404 }
0405
0406 /* Return base address of node that contains global address  */
0407 static inline unsigned long uv_gam_range_base(unsigned long pa)
0408 {
0409     struct uv_gam_range_s *gr = uv_gam_range(pa);
0410     int base = gr->base;
0411
0412     if (base < 0)
0413         return 0UL;
0414
0415     return uv_hub_info->gr_table[base].limit;
0416 }
0417
0418 /* socket phys RAM --> UV global NASID (UV4+) */
0419 static inline unsigned long uv_soc_phys_ram_to_nasid(unsigned long paddr)
0420 {
0421     return uv_gam_range(paddr)->nasid;
0422 }
0423 #define _uv_soc_phys_ram_to_nasid
0424
0425 /* socket virtual --> UV global NASID (UV4+) */
0426 static inline unsigned long uv_gpa_nasid(void *v)
0427 {
0428     return uv_soc_phys_ram_to_nasid(__pa(v));
0429 }
0430
0431 /* socket phys RAM --> UV global physical address */
0432 static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
0433 {
0434     unsigned int m_val = uv_hub_info->m_val;
0435
0436     if (paddr < uv_hub_info->lowmem_remap_top)
0437         paddr |= uv_hub_info->lowmem_remap_base;
0438
0439     if (m_val) {
0440         paddr |= uv_hub_info->gnode_upper;
0441         paddr = ((paddr << uv_hub_info->m_shift)
0442                         >> uv_hub_info->m_shift) |
0443             ((paddr >> uv_hub_info->m_val)
0444                         << uv_hub_info->n_lshift);
0445     } else {
0446         paddr |= uv_soc_phys_ram_to_nasid(paddr)
0447                         << uv_hub_info->gpa_shift;
0448     }
0449     return paddr;
0450 }
0451
0452 /* socket virtual --> UV global physical address */
0453 static inline unsigned long uv_gpa(void *v)
0454 {
0455     return uv_soc_phys_ram_to_gpa(__pa(v));
0456 }
0457
0458 /* Top two bits indicate the requested address is in MMR space.  */
0459 static inline int
0460 uv_gpa_in_mmr_space(unsigned long gpa)
0461 {
0462     return (gpa >> 62) == 0x3UL;
0463 }
0464
0465 /* UV global physical address --> socket phys RAM */
0466 static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
0467 {
0468     unsigned long paddr;
0469     unsigned long remap_base = uv_hub_info->lowmem_remap_base;
0470     unsigned long remap_top =  uv_hub_info->lowmem_remap_top;
0471     unsigned int m_val = uv_hub_info->m_val;
0472
0473     if (m_val)
0474         gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
0475             ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
0476
0477     paddr = gpa & uv_hub_info->gpa_mask;
0478     if (paddr >= remap_base && paddr < remap_base + remap_top)
0479         paddr -= remap_base;
0480     return paddr;
0481 }
0482
0483 /* gpa -> gnode */
0484 static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
0485 {
0486     unsigned int n_lshift = uv_hub_info->n_lshift;
0487
0488     if (n_lshift)
0489         return gpa >> n_lshift;
0490
0491     return uv_gam_range(gpa)->nasid >> 1;
0492 }
0493
0494 /* gpa -> pnode */
0495 static inline int uv_gpa_to_pnode(unsigned long gpa)
0496 {
0497     return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask;
0498 }
0499
0500 /* gpa -> node offset */
0501 static inline unsigned long uv_gpa_to_offset(unsigned long gpa)
0502 {
0503     unsigned int m_shift = uv_hub_info->m_shift;
0504
0505     if (m_shift)
0506         return (gpa << m_shift) >> m_shift;
0507
0508     return (gpa & uv_hub_info->gpa_mask) - uv_gam_range_base(gpa);
0509 }
0510
0511 /* Convert socket to node */
0512 static inline int _uv_socket_to_node(int socket, unsigned short *s2nid)
0513 {
0514     return s2nid ? s2nid[socket - uv_hub_info->min_socket] : socket;
0515 }
0516
0517 static inline int uv_socket_to_node(int socket)
0518 {
0519     return _uv_socket_to_node(socket, uv_hub_info->socket_to_node);
0520 }
0521
0522 /* pnode, offset --> socket virtual */
0523 static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
0524 {
0525     unsigned int m_val = uv_hub_info->m_val;
0526     unsigned long base;
0527     unsigned short sockid, node, *p2s;
0528
0529     if (m_val)
0530         return __va(((unsigned long)pnode << m_val) | offset);
0531
0532     p2s = uv_hub_info->pnode_to_socket;
0533     sockid = p2s ? p2s[pnode - uv_hub_info->min_pnode] : pnode;
0534     node = uv_socket_to_node(sockid);
0535
0536     /* limit address of previous socket is our base, except node 0 is 0 */
0537     if (!node)
0538         return __va((unsigned long)offset);
0539
0540     base = (unsigned long)(uv_hub_info->gr_table[node - 1].limit);
0541     return __va(base << UV_GAM_RANGE_SHFT | offset);
0542 }
0543
0544 /* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */
0545 static inline int uv_apicid_to_pnode(int apicid)
0546 {
0547     int pnode = apicid >> uv_hub_info->apic_pnode_shift;
0548     unsigned short *s2pn = uv_hub_info->socket_to_pnode;
0549
0550     return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode;
0551 }
0552
0553 /*
0554  * Access global MMRs using the low memory MMR32 space. This region supports
0555  * faster MMR access but not all MMRs are accessible in this space.
0556  */
0557 static inline unsigned long *uv_global_mmr32_address(int pnode, unsigned long offset)
0558 {
0559     return __va(UV_GLOBAL_MMR32_BASE |
0560                UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
0561 }
0562
0563 static inline void uv_write_global_mmr32(int pnode, unsigned long offset, unsigned long val)
0564 {
0565     writeq(val, uv_global_mmr32_address(pnode, offset));
0566 }
0567
0568 static inline unsigned long uv_read_global_mmr32(int pnode, unsigned long offset)
0569 {
0570     return readq(uv_global_mmr32_address(pnode, offset));
0571 }
0572
0573 /*
0574  * Access Global MMR space using the MMR space located at the top of physical
0575  * memory.
0576  */
0577 static inline volatile void __iomem *uv_global_mmr64_address(int pnode, unsigned long offset)
0578 {
0579     return __va(UV_GLOBAL_MMR64_BASE |
0580             UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
0581 }
0582
0583 static inline void uv_write_global_mmr64(int pnode, unsigned long offset, unsigned long val)
0584 {
0585     writeq(val, uv_global_mmr64_address(pnode, offset));
0586 }
0587
0588 static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset)
0589 {
0590     return readq(uv_global_mmr64_address(pnode, offset));
0591 }
0592
0593 static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
0594 {
0595     writeb(val, uv_global_mmr64_address(pnode, offset));
0596 }
0597
0598 static inline unsigned char uv_read_global_mmr8(int pnode, unsigned long offset)
0599 {
0600     return readb(uv_global_mmr64_address(pnode, offset));
0601 }
0602
0603 /*
0604  * Access hub local MMRs. Faster than using global space but only local MMRs
0605  * are accessible.
0606  */
0607 static inline unsigned long *uv_local_mmr_address(unsigned long offset)
0608 {
0609     return __va(UV_LOCAL_MMR_BASE | offset);
0610 }
0611
0612 static inline unsigned long uv_read_local_mmr(unsigned long offset)
0613 {
0614     return readq(uv_local_mmr_address(offset));
0615 }
0616
0617 static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
0618 {
0619     writeq(val, uv_local_mmr_address(offset));
0620 }
0621
0622 static inline unsigned char uv_read_local_mmr8(unsigned long offset)
0623 {
0624     return readb(uv_local_mmr_address(offset));
0625 }
0626
0627 static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
0628 {
0629     writeb(val, uv_local_mmr_address(offset));
0630 }
0631
0632 /* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
0633 static inline int uv_blade_processor_id(void)
0634 {
0635     return uv_cpu_info->blade_cpu_id;
0636 }
0637
0638 /* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */
0639 static inline int uv_cpu_blade_processor_id(int cpu)
0640 {
0641     return uv_cpu_info_per(cpu)->blade_cpu_id;
0642 }
0643
0644 /* Blade number to Node number (UV2..UV4 is 1:1) */
0645 static inline int uv_blade_to_node(int blade)
0646 {
0647     return blade;
0648 }
0649
0650 /* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
0651 static inline int uv_numa_blade_id(void)
0652 {
0653     return uv_hub_info->numa_blade_id;
0654 }
0655
0656 /*
0657  * Convert linux node number to the UV blade number.
0658  * .. Currently for UV2 thru UV4 the node and the blade are identical.
0659  * .. If this changes then you MUST check references to this function!
0660  */
0661 static inline int uv_node_to_blade_id(int nid)
0662 {
0663     return nid;
0664 }
0665
0666 /* Convert a CPU number to the UV blade number */
0667 static inline int uv_cpu_to_blade_id(int cpu)
0668 {
0669     return uv_node_to_blade_id(cpu_to_node(cpu));
0670 }
0671
0672 /* Convert a blade id to the PNODE of the blade */
0673 static inline int uv_blade_to_pnode(int bid)
0674 {
0675     return uv_hub_info_list(uv_blade_to_node(bid))->pnode;
0676 }
0677
0678 /* Nid of memory node on blade. -1 if no blade-local memory */
0679 static inline int uv_blade_to_memory_nid(int bid)
0680 {
0681     return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid;
0682 }
0683
0684 /* Determine the number of possible cpus on a blade */
0685 static inline int uv_blade_nr_possible_cpus(int bid)
0686 {
0687     return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus;
0688 }
0689
0690 /* Determine the number of online cpus on a blade */
0691 static inline int uv_blade_nr_online_cpus(int bid)
0692 {
0693     return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus;
0694 }
0695
0696 /* Convert a cpu id to the PNODE of the blade containing the cpu */
0697 static inline int uv_cpu_to_pnode(int cpu)
0698 {
0699     return uv_cpu_hub_info(cpu)->pnode;
0700 }
0701
0702 /* Convert a linux node number to the PNODE of the blade */
0703 static inline int uv_node_to_pnode(int nid)
0704 {
0705     return uv_hub_info_list(nid)->pnode;
0706 }
0707
0708 /* Maximum possible number of blades */
0709 extern short uv_possible_blades;
0710 static inline int uv_num_possible_blades(void)
0711 {
0712     return uv_possible_blades;
0713 }
0714
0715 /* Per Hub NMI support */
0716 extern void uv_nmi_setup(void);
0717 extern void uv_nmi_setup_hubless(void);
0718
0719 /* BIOS/Kernel flags exchange MMR */
0720 #define UVH_BIOS_KERNEL_MMR     UVH_SCRATCH5
0721 #define UVH_BIOS_KERNEL_MMR_ALIAS   UVH_SCRATCH5_ALIAS
0722 #define UVH_BIOS_KERNEL_MMR_ALIAS_2 UVH_SCRATCH5_ALIAS_2
0723
0724 /* TSC sync valid, set by BIOS */
0725 #define UVH_TSC_SYNC_MMR    UVH_BIOS_KERNEL_MMR
0726 #define UVH_TSC_SYNC_SHIFT  10
0727 #define UVH_TSC_SYNC_SHIFT_UV2K 16  /* UV2/3k have different bits */
0728 #define UVH_TSC_SYNC_MASK   3   /* 0011 */
0729 #define UVH_TSC_SYNC_VALID  3   /* 0011 */
0730 #define UVH_TSC_SYNC_UNKNOWN    0   /* 0000 */
0731
0732 /* BMC sets a bit this MMR non-zero before sending an NMI */
0733 #define UVH_NMI_MMR     UVH_BIOS_KERNEL_MMR
0734 #define UVH_NMI_MMR_CLEAR   UVH_BIOS_KERNEL_MMR_ALIAS
0735 #define UVH_NMI_MMR_SHIFT   63
0736 #define UVH_NMI_MMR_TYPE    "SCRATCH5"
0737
0738 struct uv_hub_nmi_s {
0739     raw_spinlock_t  nmi_lock;
0740     atomic_t    in_nmi;     /* flag this node in UV NMI IRQ */
0741     atomic_t    cpu_owner;  /* last locker of this struct */
0742     atomic_t    read_mmr_count; /* count of MMR reads */
0743     atomic_t    nmi_count;  /* count of true UV NMIs */
0744     unsigned long   nmi_value;  /* last value read from NMI MMR */
0745     bool        hub_present;    /* false means UV hubless system */
0746     bool        pch_owner;  /* indicates this hub owns PCH */
0747 };
0748
0749 struct uv_cpu_nmi_s {
0750     struct uv_hub_nmi_s *hub;
0751     int         state;
0752     int         pinging;
0753     int         queries;
0754     int         pings;
0755 };
0756
0757 DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
0758
0759 #define uv_hub_nmi          this_cpu_read(uv_cpu_nmi.hub)
0760 #define uv_cpu_nmi_per(cpu)     (per_cpu(uv_cpu_nmi, cpu))
0761 #define uv_hub_nmi_per(cpu)     (uv_cpu_nmi_per(cpu).hub)
0762
0763 /* uv_cpu_nmi_states */
0764 #define UV_NMI_STATE_OUT        0
0765 #define UV_NMI_STATE_IN         1
0766 #define UV_NMI_STATE_DUMP       2
0767 #define UV_NMI_STATE_DUMP_DONE      3
0768
0769 /*
0770  * Get the minimum revision number of the hub chips within the partition.
0771  * (See UVx_HUB_REVISION_BASE above for specific values.)
0772  */
0773 static inline int uv_get_min_hub_revision_id(void)
0774 {
0775     return uv_hub_info->hub_revision;
0776 }
0777
0778 #endif /* CONFIG_X86_64 */
0779 #endif /* _ASM_X86_UV_UV_HUB_H */