include/asm/tlb.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_TLB_H
0003 #define _ASM_X86_TLB_H
0004
0005 #define tlb_flush tlb_flush
0006 static inline void tlb_flush(struct mmu_gather *tlb);
0007
0008 #include <asm-generic/tlb.h>
0009
0010 static inline void tlb_flush(struct mmu_gather *tlb)
0011 {
0012     unsigned long start = 0UL, end = TLB_FLUSH_ALL;
0013     unsigned int stride_shift = tlb_get_unmap_shift(tlb);
0014
0015     if (!tlb->fullmm && !tlb->need_flush_all) {
0016         start = tlb->start;
0017         end = tlb->end;
0018     }
0019
0020     flush_tlb_mm_range(tlb->mm, start, end, stride_shift, tlb->freed_tables);
0021 }
0022
0023 /*
0024  * While x86 architecture in general requires an IPI to perform TLB
0025  * shootdown, enablement code for several hypervisors overrides
0026  * .flush_tlb_others hook in pv_mmu_ops and implements it by issuing
0027  * a hypercall. To keep software pagetable walkers safe in this case we
0028  * switch to RCU based table free (MMU_GATHER_RCU_TABLE_FREE). See the comment
0029  * below 'ifdef CONFIG_MMU_GATHER_RCU_TABLE_FREE' in include/asm-generic/tlb.h
0030  * for more details.
0031  */
0032 static inline void __tlb_remove_table(void *table)
0033 {
0034     free_page_and_swap_cache(table);
0035 }
0036
0037 #endif /* _ASM_X86_TLB_H */