include/asm/svm.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __SVM_H
0003 #define __SVM_H
0004
0005 #include <uapi/asm/svm.h>
0006 #include <uapi/asm/kvm.h>
0007
0008 /*
0009  * 32-bit intercept words in the VMCB Control Area, starting
0010  * at Byte offset 000h.
0011  */
0012
0013 enum intercept_words {
0014     INTERCEPT_CR = 0,
0015     INTERCEPT_DR,
0016     INTERCEPT_EXCEPTION,
0017     INTERCEPT_WORD3,
0018     INTERCEPT_WORD4,
0019     INTERCEPT_WORD5,
0020     MAX_INTERCEPT,
0021 };
0022
0023 enum {
0024     /* Byte offset 000h (word 0) */
0025     INTERCEPT_CR0_READ = 0,
0026     INTERCEPT_CR3_READ = 3,
0027     INTERCEPT_CR4_READ = 4,
0028     INTERCEPT_CR8_READ = 8,
0029     INTERCEPT_CR0_WRITE = 16,
0030     INTERCEPT_CR3_WRITE = 16 + 3,
0031     INTERCEPT_CR4_WRITE = 16 + 4,
0032     INTERCEPT_CR8_WRITE = 16 + 8,
0033     /* Byte offset 004h (word 1) */
0034     INTERCEPT_DR0_READ = 32,
0035     INTERCEPT_DR1_READ,
0036     INTERCEPT_DR2_READ,
0037     INTERCEPT_DR3_READ,
0038     INTERCEPT_DR4_READ,
0039     INTERCEPT_DR5_READ,
0040     INTERCEPT_DR6_READ,
0041     INTERCEPT_DR7_READ,
0042     INTERCEPT_DR0_WRITE = 48,
0043     INTERCEPT_DR1_WRITE,
0044     INTERCEPT_DR2_WRITE,
0045     INTERCEPT_DR3_WRITE,
0046     INTERCEPT_DR4_WRITE,
0047     INTERCEPT_DR5_WRITE,
0048     INTERCEPT_DR6_WRITE,
0049     INTERCEPT_DR7_WRITE,
0050     /* Byte offset 008h (word 2) */
0051     INTERCEPT_EXCEPTION_OFFSET = 64,
0052     /* Byte offset 00Ch (word 3) */
0053     INTERCEPT_INTR = 96,
0054     INTERCEPT_NMI,
0055     INTERCEPT_SMI,
0056     INTERCEPT_INIT,
0057     INTERCEPT_VINTR,
0058     INTERCEPT_SELECTIVE_CR0,
0059     INTERCEPT_STORE_IDTR,
0060     INTERCEPT_STORE_GDTR,
0061     INTERCEPT_STORE_LDTR,
0062     INTERCEPT_STORE_TR,
0063     INTERCEPT_LOAD_IDTR,
0064     INTERCEPT_LOAD_GDTR,
0065     INTERCEPT_LOAD_LDTR,
0066     INTERCEPT_LOAD_TR,
0067     INTERCEPT_RDTSC,
0068     INTERCEPT_RDPMC,
0069     INTERCEPT_PUSHF,
0070     INTERCEPT_POPF,
0071     INTERCEPT_CPUID,
0072     INTERCEPT_RSM,
0073     INTERCEPT_IRET,
0074     INTERCEPT_INTn,
0075     INTERCEPT_INVD,
0076     INTERCEPT_PAUSE,
0077     INTERCEPT_HLT,
0078     INTERCEPT_INVLPG,
0079     INTERCEPT_INVLPGA,
0080     INTERCEPT_IOIO_PROT,
0081     INTERCEPT_MSR_PROT,
0082     INTERCEPT_TASK_SWITCH,
0083     INTERCEPT_FERR_FREEZE,
0084     INTERCEPT_SHUTDOWN,
0085     /* Byte offset 010h (word 4) */
0086     INTERCEPT_VMRUN = 128,
0087     INTERCEPT_VMMCALL,
0088     INTERCEPT_VMLOAD,
0089     INTERCEPT_VMSAVE,
0090     INTERCEPT_STGI,
0091     INTERCEPT_CLGI,
0092     INTERCEPT_SKINIT,
0093     INTERCEPT_RDTSCP,
0094     INTERCEPT_ICEBP,
0095     INTERCEPT_WBINVD,
0096     INTERCEPT_MONITOR,
0097     INTERCEPT_MWAIT,
0098     INTERCEPT_MWAIT_COND,
0099     INTERCEPT_XSETBV,
0100     INTERCEPT_RDPRU,
0101     TRAP_EFER_WRITE,
0102     TRAP_CR0_WRITE,
0103     TRAP_CR1_WRITE,
0104     TRAP_CR2_WRITE,
0105     TRAP_CR3_WRITE,
0106     TRAP_CR4_WRITE,
0107     TRAP_CR5_WRITE,
0108     TRAP_CR6_WRITE,
0109     TRAP_CR7_WRITE,
0110     TRAP_CR8_WRITE,
0111     /* Byte offset 014h (word 5) */
0112     INTERCEPT_INVLPGB = 160,
0113     INTERCEPT_INVLPGB_ILLEGAL,
0114     INTERCEPT_INVPCID,
0115     INTERCEPT_MCOMMIT,
0116     INTERCEPT_TLBSYNC,
0117 };
0118
0119
0120 struct __attribute__ ((__packed__)) vmcb_control_area {
0121     u32 intercepts[MAX_INTERCEPT];
0122     u32 reserved_1[15 - MAX_INTERCEPT];
0123     u16 pause_filter_thresh;
0124     u16 pause_filter_count;
0125     u64 iopm_base_pa;
0126     u64 msrpm_base_pa;
0127     u64 tsc_offset;
0128     u32 asid;
0129     u8 tlb_ctl;
0130     u8 reserved_2[3];
0131     u32 int_ctl;
0132     u32 int_vector;
0133     u32 int_state;
0134     u8 reserved_3[4];
0135     u32 exit_code;
0136     u32 exit_code_hi;
0137     u64 exit_info_1;
0138     u64 exit_info_2;
0139     u32 exit_int_info;
0140     u32 exit_int_info_err;
0141     u64 nested_ctl;
0142     u64 avic_vapic_bar;
0143     u64 ghcb_gpa;
0144     u32 event_inj;
0145     u32 event_inj_err;
0146     u64 nested_cr3;
0147     u64 virt_ext;
0148     u32 clean;
0149     u32 reserved_5;
0150     u64 next_rip;
0151     u8 insn_len;
0152     u8 insn_bytes[15];
0153     u64 avic_backing_page;  /* Offset 0xe0 */
0154     u8 reserved_6[8];   /* Offset 0xe8 */
0155     u64 avic_logical_id;    /* Offset 0xf0 */
0156     u64 avic_physical_id;   /* Offset 0xf8 */
0157     u8 reserved_7[8];
0158     u64 vmsa_pa;        /* Used for an SEV-ES guest */
0159     u8 reserved_8[720];
0160     /*
0161      * Offset 0x3e0, 32 bytes reserved
0162      * for use by hypervisor/software.
0163      */
0164     u8 reserved_sw[32];
0165 };
0166
0167
0168 #define TLB_CONTROL_DO_NOTHING 0
0169 #define TLB_CONTROL_FLUSH_ALL_ASID 1
0170 #define TLB_CONTROL_FLUSH_ASID 3
0171 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
0172
0173 #define V_TPR_MASK 0x0f
0174
0175 #define V_IRQ_SHIFT 8
0176 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
0177
0178 #define V_GIF_SHIFT 9
0179 #define V_GIF_MASK (1 << V_GIF_SHIFT)
0180
0181 #define V_INTR_PRIO_SHIFT 16
0182 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
0183
0184 #define V_IGN_TPR_SHIFT 20
0185 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
0186
0187 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
0188
0189 #define V_INTR_MASKING_SHIFT 24
0190 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
0191
0192 #define V_GIF_ENABLE_SHIFT 25
0193 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
0194
0195 #define AVIC_ENABLE_SHIFT 31
0196 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
0197
0198 #define X2APIC_MODE_SHIFT 30
0199 #define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT)
0200
0201 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
0202 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
0203
0204 #define SVM_INTERRUPT_SHADOW_MASK   BIT_ULL(0)
0205 #define SVM_GUEST_INTERRUPT_MASK    BIT_ULL(1)
0206
0207 #define SVM_IOIO_STR_SHIFT 2
0208 #define SVM_IOIO_REP_SHIFT 3
0209 #define SVM_IOIO_SIZE_SHIFT 4
0210 #define SVM_IOIO_ASIZE_SHIFT 7
0211
0212 #define SVM_IOIO_TYPE_MASK 1
0213 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
0214 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
0215 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
0216 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
0217
0218 #define SVM_VM_CR_VALID_MASK    0x001fULL
0219 #define SVM_VM_CR_SVM_LOCK_MASK 0x0008ULL
0220 #define SVM_VM_CR_SVM_DIS_MASK  0x0010ULL
0221
0222 #define SVM_NESTED_CTL_NP_ENABLE    BIT(0)
0223 #define SVM_NESTED_CTL_SEV_ENABLE   BIT(1)
0224 #define SVM_NESTED_CTL_SEV_ES_ENABLE    BIT(2)
0225
0226
0227 #define SVM_TSC_RATIO_RSVD  0xffffff0000000000ULL
0228 #define SVM_TSC_RATIO_MIN   0x0000000000000001ULL
0229 #define SVM_TSC_RATIO_MAX   0x000000ffffffffffULL
0230 #define SVM_TSC_RATIO_DEFAULT   0x0100000000ULL
0231
0232
0233 /* AVIC */
0234 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK    (0xFFULL)
0235 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT         31
0236 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK        (1 << 31)
0237
0238 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK    GENMASK_ULL(11, 0)
0239 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK    (0xFFFFFFFFFFULL << 12)
0240 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK      (1ULL << 62)
0241 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK       (1ULL << 63)
0242 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK        (0xFFULL)
0243
0244 #define AVIC_DOORBELL_PHYSICAL_ID_MASK          GENMASK_ULL(11, 0)
0245
0246 #define VMCB_AVIC_APIC_BAR_MASK             0xFFFFFFFFFF000ULL
0247
0248 #define AVIC_UNACCEL_ACCESS_WRITE_MASK      1
0249 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK     0xFF0
0250 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK     0xFFFFFFFF
0251
0252 enum avic_ipi_failure_cause {
0253     AVIC_IPI_FAILURE_INVALID_INT_TYPE,
0254     AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
0255     AVIC_IPI_FAILURE_INVALID_TARGET,
0256     AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
0257 };
0258
0259 #define AVIC_PHYSICAL_MAX_INDEX_MASK    GENMASK_ULL(9, 0)
0260
0261 /*
0262  * For AVIC, the max index allowed for physical APIC ID
0263  * table is 0xff (255).
0264  */
0265 #define AVIC_MAX_PHYSICAL_ID        0XFEULL
0266
0267 /*
0268  * For x2AVIC, the max index allowed for physical APIC ID
0269  * table is 0x1ff (511).
0270  */
0271 #define X2AVIC_MAX_PHYSICAL_ID      0x1FFUL
0272
0273 #define AVIC_HPA_MASK   ~((0xFFFULL << 52) | 0xFFF)
0274 #define VMCB_AVIC_APIC_BAR_MASK     0xFFFFFFFFFF000ULL
0275
0276
0277 struct vmcb_seg {
0278     u16 selector;
0279     u16 attrib;
0280     u32 limit;
0281     u64 base;
0282 } __packed;
0283
0284 /* Save area definition for legacy and SEV-MEM guests */
0285 struct vmcb_save_area {
0286     struct vmcb_seg es;
0287     struct vmcb_seg cs;
0288     struct vmcb_seg ss;
0289     struct vmcb_seg ds;
0290     struct vmcb_seg fs;
0291     struct vmcb_seg gs;
0292     struct vmcb_seg gdtr;
0293     struct vmcb_seg ldtr;
0294     struct vmcb_seg idtr;
0295     struct vmcb_seg tr;
0296     u8 reserved_1[42];
0297     u8 vmpl;
0298     u8 cpl;
0299     u8 reserved_2[4];
0300     u64 efer;
0301     u8 reserved_3[112];
0302     u64 cr4;
0303     u64 cr3;
0304     u64 cr0;
0305     u64 dr7;
0306     u64 dr6;
0307     u64 rflags;
0308     u64 rip;
0309     u8 reserved_4[88];
0310     u64 rsp;
0311     u64 s_cet;
0312     u64 ssp;
0313     u64 isst_addr;
0314     u64 rax;
0315     u64 star;
0316     u64 lstar;
0317     u64 cstar;
0318     u64 sfmask;
0319     u64 kernel_gs_base;
0320     u64 sysenter_cs;
0321     u64 sysenter_esp;
0322     u64 sysenter_eip;
0323     u64 cr2;
0324     u8 reserved_5[32];
0325     u64 g_pat;
0326     u64 dbgctl;
0327     u64 br_from;
0328     u64 br_to;
0329     u64 last_excp_from;
0330     u64 last_excp_to;
0331     u8 reserved_6[72];
0332     u32 spec_ctrl;      /* Guest version of SPEC_CTRL at 0x2E0 */
0333 } __packed;
0334
0335 /* Save area definition for SEV-ES and SEV-SNP guests */
0336 struct sev_es_save_area {
0337     struct vmcb_seg es;
0338     struct vmcb_seg cs;
0339     struct vmcb_seg ss;
0340     struct vmcb_seg ds;
0341     struct vmcb_seg fs;
0342     struct vmcb_seg gs;
0343     struct vmcb_seg gdtr;
0344     struct vmcb_seg ldtr;
0345     struct vmcb_seg idtr;
0346     struct vmcb_seg tr;
0347     u64 vmpl0_ssp;
0348     u64 vmpl1_ssp;
0349     u64 vmpl2_ssp;
0350     u64 vmpl3_ssp;
0351     u64 u_cet;
0352     u8 reserved_1[2];
0353     u8 vmpl;
0354     u8 cpl;
0355     u8 reserved_2[4];
0356     u64 efer;
0357     u8 reserved_3[104];
0358     u64 xss;
0359     u64 cr4;
0360     u64 cr3;
0361     u64 cr0;
0362     u64 dr7;
0363     u64 dr6;
0364     u64 rflags;
0365     u64 rip;
0366     u64 dr0;
0367     u64 dr1;
0368     u64 dr2;
0369     u64 dr3;
0370     u64 dr0_addr_mask;
0371     u64 dr1_addr_mask;
0372     u64 dr2_addr_mask;
0373     u64 dr3_addr_mask;
0374     u8 reserved_4[24];
0375     u64 rsp;
0376     u64 s_cet;
0377     u64 ssp;
0378     u64 isst_addr;
0379     u64 rax;
0380     u64 star;
0381     u64 lstar;
0382     u64 cstar;
0383     u64 sfmask;
0384     u64 kernel_gs_base;
0385     u64 sysenter_cs;
0386     u64 sysenter_esp;
0387     u64 sysenter_eip;
0388     u64 cr2;
0389     u8 reserved_5[32];
0390     u64 g_pat;
0391     u64 dbgctl;
0392     u64 br_from;
0393     u64 br_to;
0394     u64 last_excp_from;
0395     u64 last_excp_to;
0396     u8 reserved_7[80];
0397     u32 pkru;
0398     u8 reserved_8[20];
0399     u64 reserved_9;     /* rax already available at 0x01f8 */
0400     u64 rcx;
0401     u64 rdx;
0402     u64 rbx;
0403     u64 reserved_10;    /* rsp already available at 0x01d8 */
0404     u64 rbp;
0405     u64 rsi;
0406     u64 rdi;
0407     u64 r8;
0408     u64 r9;
0409     u64 r10;
0410     u64 r11;
0411     u64 r12;
0412     u64 r13;
0413     u64 r14;
0414     u64 r15;
0415     u8 reserved_11[16];
0416     u64 guest_exit_info_1;
0417     u64 guest_exit_info_2;
0418     u64 guest_exit_int_info;
0419     u64 guest_nrip;
0420     u64 sev_features;
0421     u64 vintr_ctrl;
0422     u64 guest_exit_code;
0423     u64 virtual_tom;
0424     u64 tlb_id;
0425     u64 pcpu_id;
0426     u64 event_inj;
0427     u64 xcr0;
0428     u8 reserved_12[16];
0429
0430     /* Floating point area */
0431     u64 x87_dp;
0432     u32 mxcsr;
0433     u16 x87_ftw;
0434     u16 x87_fsw;
0435     u16 x87_fcw;
0436     u16 x87_fop;
0437     u16 x87_ds;
0438     u16 x87_cs;
0439     u64 x87_rip;
0440     u8 fpreg_x87[80];
0441     u8 fpreg_xmm[256];
0442     u8 fpreg_ymm[256];
0443 } __packed;
0444
0445 struct ghcb_save_area {
0446     u8 reserved_1[203];
0447     u8 cpl;
0448     u8 reserved_2[116];
0449     u64 xss;
0450     u8 reserved_3[24];
0451     u64 dr7;
0452     u8 reserved_4[16];
0453     u64 rip;
0454     u8 reserved_5[88];
0455     u64 rsp;
0456     u8 reserved_6[24];
0457     u64 rax;
0458     u8 reserved_7[264];
0459     u64 rcx;
0460     u64 rdx;
0461     u64 rbx;
0462     u8 reserved_8[8];
0463     u64 rbp;
0464     u64 rsi;
0465     u64 rdi;
0466     u64 r8;
0467     u64 r9;
0468     u64 r10;
0469     u64 r11;
0470     u64 r12;
0471     u64 r13;
0472     u64 r14;
0473     u64 r15;
0474     u8 reserved_9[16];
0475     u64 sw_exit_code;
0476     u64 sw_exit_info_1;
0477     u64 sw_exit_info_2;
0478     u64 sw_scratch;
0479     u8 reserved_10[56];
0480     u64 xcr0;
0481     u8 valid_bitmap[16];
0482     u64 x87_state_gpa;
0483 } __packed;
0484
0485 #define GHCB_SHARED_BUF_SIZE    2032
0486
0487 struct ghcb {
0488     struct ghcb_save_area save;
0489     u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];
0490
0491     u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
0492
0493     u8 reserved_1[10];
0494     u16 protocol_version;   /* negotiated SEV-ES/GHCB protocol version */
0495     u32 ghcb_usage;
0496 } __packed;
0497
0498
0499 #define EXPECTED_VMCB_SAVE_AREA_SIZE        740
0500 #define EXPECTED_GHCB_SAVE_AREA_SIZE        1032
0501 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE      1648
0502 #define EXPECTED_VMCB_CONTROL_AREA_SIZE     1024
0503 #define EXPECTED_GHCB_SIZE          PAGE_SIZE
0504
0505 static inline void __unused_size_checks(void)
0506 {
0507     BUILD_BUG_ON(sizeof(struct vmcb_save_area)  != EXPECTED_VMCB_SAVE_AREA_SIZE);
0508     BUILD_BUG_ON(sizeof(struct ghcb_save_area)  != EXPECTED_GHCB_SAVE_AREA_SIZE);
0509     BUILD_BUG_ON(sizeof(struct sev_es_save_area)    != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
0510     BUILD_BUG_ON(sizeof(struct vmcb_control_area)   != EXPECTED_VMCB_CONTROL_AREA_SIZE);
0511     BUILD_BUG_ON(sizeof(struct ghcb)        != EXPECTED_GHCB_SIZE);
0512 }
0513
0514 struct vmcb {
0515     struct vmcb_control_area control;
0516     struct vmcb_save_area save;
0517 } __packed;
0518
0519 #define SVM_CPUID_FUNC 0x8000000a
0520
0521 #define SVM_VM_CR_SVM_DISABLE 4
0522
0523 #define SVM_SELECTOR_S_SHIFT 4
0524 #define SVM_SELECTOR_DPL_SHIFT 5
0525 #define SVM_SELECTOR_P_SHIFT 7
0526 #define SVM_SELECTOR_AVL_SHIFT 8
0527 #define SVM_SELECTOR_L_SHIFT 9
0528 #define SVM_SELECTOR_DB_SHIFT 10
0529 #define SVM_SELECTOR_G_SHIFT 11
0530
0531 #define SVM_SELECTOR_TYPE_MASK (0xf)
0532 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
0533 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
0534 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
0535 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
0536 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
0537 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
0538 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
0539
0540 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
0541 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
0542 #define SVM_SELECTOR_CODE_MASK (1 << 3)
0543
0544 #define SVM_EVTINJ_VEC_MASK 0xff
0545
0546 #define SVM_EVTINJ_TYPE_SHIFT 8
0547 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
0548
0549 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
0550 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
0551 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
0552 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
0553
0554 #define SVM_EVTINJ_VALID (1 << 31)
0555 #define SVM_EVTINJ_VALID_ERR (1 << 11)
0556
0557 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
0558 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
0559
0560 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
0561 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
0562 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
0563 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
0564
0565 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
0566 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
0567
0568 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
0569 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
0570 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
0571
0572 #define SVM_EXITINFO_REG_MASK 0x0F
0573
0574 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
0575
0576 /* GHCB Accessor functions */
0577
0578 #define GHCB_BITMAP_IDX(field)                          \
0579     (offsetof(struct ghcb_save_area, field) / sizeof(u64))
0580
0581 #define DEFINE_GHCB_ACCESSORS(field)                        \
0582     static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
0583     {                                   \
0584         return test_bit(GHCB_BITMAP_IDX(field),             \
0585                 (unsigned long *)&ghcb->save.valid_bitmap); \
0586     }                                   \
0587                                         \
0588     static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb)      \
0589     {                                   \
0590         return ghcb->save.field;                    \
0591     }                                   \
0592                                         \
0593     static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
0594     {                                   \
0595         return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0;    \
0596     }                                   \
0597                                         \
0598     static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
0599     {                                   \
0600         __set_bit(GHCB_BITMAP_IDX(field),               \
0601               (unsigned long *)&ghcb->save.valid_bitmap);       \
0602         ghcb->save.field = value;                   \
0603     }
0604
0605 DEFINE_GHCB_ACCESSORS(cpl)
0606 DEFINE_GHCB_ACCESSORS(rip)
0607 DEFINE_GHCB_ACCESSORS(rsp)
0608 DEFINE_GHCB_ACCESSORS(rax)
0609 DEFINE_GHCB_ACCESSORS(rcx)
0610 DEFINE_GHCB_ACCESSORS(rdx)
0611 DEFINE_GHCB_ACCESSORS(rbx)
0612 DEFINE_GHCB_ACCESSORS(rbp)
0613 DEFINE_GHCB_ACCESSORS(rsi)
0614 DEFINE_GHCB_ACCESSORS(rdi)
0615 DEFINE_GHCB_ACCESSORS(r8)
0616 DEFINE_GHCB_ACCESSORS(r9)
0617 DEFINE_GHCB_ACCESSORS(r10)
0618 DEFINE_GHCB_ACCESSORS(r11)
0619 DEFINE_GHCB_ACCESSORS(r12)
0620 DEFINE_GHCB_ACCESSORS(r13)
0621 DEFINE_GHCB_ACCESSORS(r14)
0622 DEFINE_GHCB_ACCESSORS(r15)
0623 DEFINE_GHCB_ACCESSORS(sw_exit_code)
0624 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
0625 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
0626 DEFINE_GHCB_ACCESSORS(sw_scratch)
0627 DEFINE_GHCB_ACCESSORS(xcr0)
0628
0629 #endif