include/asm/sev-common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * AMD SEV header common between the guest and the hypervisor.
0004  *
0005  * Author: Brijesh Singh <brijesh.singh@amd.com>
0006  */
0007
0008 #ifndef __ASM_X86_SEV_COMMON_H
0009 #define __ASM_X86_SEV_COMMON_H
0010
0011 #define GHCB_MSR_INFO_POS       0
0012 #define GHCB_DATA_LOW           12
0013 #define GHCB_MSR_INFO_MASK      (BIT_ULL(GHCB_DATA_LOW) - 1)
0014
0015 #define GHCB_DATA(v)            \
0016     (((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)
0017
0018 /* SEV Information Request/Response */
0019 #define GHCB_MSR_SEV_INFO_RESP      0x001
0020 #define GHCB_MSR_SEV_INFO_REQ       0x002
0021
0022 #define GHCB_MSR_SEV_INFO(_max, _min, _cbit)    \
0023     /* GHCBData[63:48] */           \
0024     ((((_max) & 0xffff) << 48) |        \
0025      /* GHCBData[47:32] */          \
0026      (((_min) & 0xffff) << 32) |        \
0027      /* GHCBData[31:24] */          \
0028      (((_cbit) & 0xff)  << 24) |        \
0029      GHCB_MSR_SEV_INFO_RESP)
0030
0031 #define GHCB_MSR_INFO(v)        ((v) & 0xfffUL)
0032 #define GHCB_MSR_PROTO_MAX(v)       (((v) >> 48) & 0xffff)
0033 #define GHCB_MSR_PROTO_MIN(v)       (((v) >> 32) & 0xffff)
0034
0035 /* CPUID Request/Response */
0036 #define GHCB_MSR_CPUID_REQ      0x004
0037 #define GHCB_MSR_CPUID_RESP     0x005
0038 #define GHCB_MSR_CPUID_FUNC_POS     32
0039 #define GHCB_MSR_CPUID_FUNC_MASK    0xffffffff
0040 #define GHCB_MSR_CPUID_VALUE_POS    32
0041 #define GHCB_MSR_CPUID_VALUE_MASK   0xffffffff
0042 #define GHCB_MSR_CPUID_REG_POS      30
0043 #define GHCB_MSR_CPUID_REG_MASK     0x3
0044 #define GHCB_CPUID_REQ_EAX      0
0045 #define GHCB_CPUID_REQ_EBX      1
0046 #define GHCB_CPUID_REQ_ECX      2
0047 #define GHCB_CPUID_REQ_EDX      3
0048 #define GHCB_CPUID_REQ(fn, reg)             \
0049     /* GHCBData[11:0] */                \
0050     (GHCB_MSR_CPUID_REQ |               \
0051     /* GHCBData[31:12] */               \
0052     (((unsigned long)(reg) & 0x3) << 30) |      \
0053     /* GHCBData[63:32] */               \
0054     (((unsigned long)fn) << 32))
0055
0056 /* AP Reset Hold */
0057 #define GHCB_MSR_AP_RESET_HOLD_REQ  0x006
0058 #define GHCB_MSR_AP_RESET_HOLD_RESP 0x007
0059
0060 /* GHCB GPA Register */
0061 #define GHCB_MSR_REG_GPA_REQ        0x012
0062 #define GHCB_MSR_REG_GPA_REQ_VAL(v)         \
0063     /* GHCBData[63:12] */               \
0064     (((u64)((v) & GENMASK_ULL(51, 0)) << 12) |  \
0065     /* GHCBData[11:0] */                \
0066     GHCB_MSR_REG_GPA_REQ)
0067
0068 #define GHCB_MSR_REG_GPA_RESP       0x013
0069 #define GHCB_MSR_REG_GPA_RESP_VAL(v)            \
0070     /* GHCBData[63:12] */               \
0071     (((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
0072
0073 /*
0074  * SNP Page State Change Operation
0075  *
0076  * GHCBData[55:52] - Page operation:
0077  *   0x0001 Page assignment, Private
0078  *   0x0002 Page assignment, Shared
0079  */
0080 enum psc_op {
0081     SNP_PAGE_STATE_PRIVATE = 1,
0082     SNP_PAGE_STATE_SHARED,
0083 };
0084
0085 #define GHCB_MSR_PSC_REQ        0x014
0086 #define GHCB_MSR_PSC_REQ_GFN(gfn, op)           \
0087     /* GHCBData[55:52] */               \
0088     (((u64)((op) & 0xf) << 52) |            \
0089     /* GHCBData[51:12] */               \
0090     ((u64)((gfn) & GENMASK_ULL(39, 0)) << 12) | \
0091     /* GHCBData[11:0] */                \
0092     GHCB_MSR_PSC_REQ)
0093
0094 #define GHCB_MSR_PSC_RESP       0x015
0095 #define GHCB_MSR_PSC_RESP_VAL(val)          \
0096     /* GHCBData[63:32] */               \
0097     (((u64)(val) & GENMASK_ULL(63, 32)) >> 32)
0098
0099 /* GHCB Hypervisor Feature Request/Response */
0100 #define GHCB_MSR_HV_FT_REQ      0x080
0101 #define GHCB_MSR_HV_FT_RESP     0x081
0102 #define GHCB_MSR_HV_FT_RESP_VAL(v)          \
0103     /* GHCBData[63:12] */               \
0104     (((u64)(v) & GENMASK_ULL(63, 12)) >> 12)
0105
0106 #define GHCB_HV_FT_SNP          BIT_ULL(0)
0107 #define GHCB_HV_FT_SNP_AP_CREATION  BIT_ULL(1)
0108
0109 /* SNP Page State Change NAE event */
0110 #define VMGEXIT_PSC_MAX_ENTRY       253
0111
0112 struct psc_hdr {
0113     u16 cur_entry;
0114     u16 end_entry;
0115     u32 reserved;
0116 } __packed;
0117
0118 struct psc_entry {
0119     u64 cur_page    : 12,
0120         gfn     : 40,
0121         operation   : 4,
0122         pagesize    : 1,
0123         reserved    : 7;
0124 } __packed;
0125
0126 struct snp_psc_desc {
0127     struct psc_hdr hdr;
0128     struct psc_entry entries[VMGEXIT_PSC_MAX_ENTRY];
0129 } __packed;
0130
0131 /* Guest message request error code */
0132 #define SNP_GUEST_REQ_INVALID_LEN   BIT_ULL(32)
0133
0134 #define GHCB_MSR_TERM_REQ       0x100
0135 #define GHCB_MSR_TERM_REASON_SET_POS    12
0136 #define GHCB_MSR_TERM_REASON_SET_MASK   0xf
0137 #define GHCB_MSR_TERM_REASON_POS    16
0138 #define GHCB_MSR_TERM_REASON_MASK   0xff
0139
0140 #define GHCB_SEV_TERM_REASON(reason_set, reason_val)    \
0141     /* GHCBData[15:12] */               \
0142     (((((u64)reason_set) &  0xf) << 12) |       \
0143      /* GHCBData[23:16] */              \
0144     ((((u64)reason_val) & 0xff) << 16))
0145
0146 /* Error codes from reason set 0 */
0147 #define SEV_TERM_SET_GEN        0
0148 #define GHCB_SEV_ES_GEN_REQ     0
0149 #define GHCB_SEV_ES_PROT_UNSUPPORTED    1
0150 #define GHCB_SNP_UNSUPPORTED        2
0151
0152 /* Linux-specific reason codes (used with reason set 1) */
0153 #define SEV_TERM_SET_LINUX      1
0154 #define GHCB_TERM_REGISTER      0   /* GHCB GPA registration failure */
0155 #define GHCB_TERM_PSC           1   /* Page State Change failure */
0156 #define GHCB_TERM_PVALIDATE     2   /* Pvalidate failure */
0157 #define GHCB_TERM_NOT_VMPL0     3   /* SNP guest is not running at VMPL-0 */
0158 #define GHCB_TERM_CPUID         4   /* CPUID-validation failure */
0159 #define GHCB_TERM_CPUID_HV      5   /* CPUID failure during hypervisor fallback */
0160
0161 #define GHCB_RESP_CODE(v)       ((v) & GHCB_MSR_INFO_MASK)
0162
0163 /*
0164  * Error codes related to GHCB input that can be communicated back to the guest
0165  * by setting the lower 32-bits of the GHCB SW_EXITINFO1 field to 2.
0166  */
0167 #define GHCB_ERR_NOT_REGISTERED     1
0168 #define GHCB_ERR_INVALID_USAGE      2
0169 #define GHCB_ERR_INVALID_SCRATCH_AREA   3
0170 #define GHCB_ERR_MISSING_INPUT      4
0171 #define GHCB_ERR_INVALID_INPUT      5
0172 #define GHCB_ERR_INVALID_EVENT      6
0173
0174 #endif