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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_PROCESSOR_H
0003 #define _ASM_X86_PROCESSOR_H
0004 
0005 #include <asm/processor-flags.h>
0006 
0007 /* Forward declaration, a strange C thing */
0008 struct task_struct;
0009 struct mm_struct;
0010 struct io_bitmap;
0011 struct vm86;
0012 
0013 #include <asm/math_emu.h>
0014 #include <asm/segment.h>
0015 #include <asm/types.h>
0016 #include <uapi/asm/sigcontext.h>
0017 #include <asm/current.h>
0018 #include <asm/cpufeatures.h>
0019 #include <asm/page.h>
0020 #include <asm/pgtable_types.h>
0021 #include <asm/percpu.h>
0022 #include <asm/msr.h>
0023 #include <asm/desc_defs.h>
0024 #include <asm/nops.h>
0025 #include <asm/special_insns.h>
0026 #include <asm/fpu/types.h>
0027 #include <asm/unwind_hints.h>
0028 #include <asm/vmxfeatures.h>
0029 #include <asm/vdso/processor.h>
0030 
0031 #include <linux/personality.h>
0032 #include <linux/cache.h>
0033 #include <linux/threads.h>
0034 #include <linux/math64.h>
0035 #include <linux/err.h>
0036 #include <linux/irqflags.h>
0037 #include <linux/mem_encrypt.h>
0038 
0039 /*
0040  * We handle most unaligned accesses in hardware.  On the other hand
0041  * unaligned DMA can be quite expensive on some Nehalem processors.
0042  *
0043  * Based on this we disable the IP header alignment in network drivers.
0044  */
0045 #define NET_IP_ALIGN    0
0046 
0047 #define HBP_NUM 4
0048 
0049 /*
0050  * These alignment constraints are for performance in the vSMP case,
0051  * but in the task_struct case we must also meet hardware imposed
0052  * alignment requirements of the FPU state:
0053  */
0054 #ifdef CONFIG_X86_VSMP
0055 # define ARCH_MIN_TASKALIGN     (1 << INTERNODE_CACHE_SHIFT)
0056 # define ARCH_MIN_MMSTRUCT_ALIGN    (1 << INTERNODE_CACHE_SHIFT)
0057 #else
0058 # define ARCH_MIN_TASKALIGN     __alignof__(union fpregs_state)
0059 # define ARCH_MIN_MMSTRUCT_ALIGN    0
0060 #endif
0061 
0062 enum tlb_infos {
0063     ENTRIES,
0064     NR_INFO
0065 };
0066 
0067 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
0068 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
0069 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
0070 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
0071 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
0072 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
0073 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
0074 
0075 /*
0076  *  CPU type and hardware bug flags. Kept separately for each CPU.
0077  *  Members of this structure are referenced in head_32.S, so think twice
0078  *  before touching them. [mj]
0079  */
0080 
0081 struct cpuinfo_x86 {
0082     __u8            x86;        /* CPU family */
0083     __u8            x86_vendor; /* CPU vendor */
0084     __u8            x86_model;
0085     __u8            x86_stepping;
0086 #ifdef CONFIG_X86_64
0087     /* Number of 4K pages in DTLB/ITLB combined(in pages): */
0088     int         x86_tlbsize;
0089 #endif
0090 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
0091     __u32           vmx_capability[NVMXINTS];
0092 #endif
0093     __u8            x86_virt_bits;
0094     __u8            x86_phys_bits;
0095     /* CPUID returned core id bits: */
0096     __u8            x86_coreid_bits;
0097     __u8            cu_id;
0098     /* Max extended CPUID function supported: */
0099     __u32           extended_cpuid_level;
0100     /* Maximum supported CPUID level, -1=no CPUID: */
0101     int         cpuid_level;
0102     /*
0103      * Align to size of unsigned long because the x86_capability array
0104      * is passed to bitops which require the alignment. Use unnamed
0105      * union to enforce the array is aligned to size of unsigned long.
0106      */
0107     union {
0108         __u32       x86_capability[NCAPINTS + NBUGINTS];
0109         unsigned long   x86_capability_alignment;
0110     };
0111     char            x86_vendor_id[16];
0112     char            x86_model_id[64];
0113     /* in KB - valid for CPUS which support this call: */
0114     unsigned int        x86_cache_size;
0115     int         x86_cache_alignment;    /* In bytes */
0116     /* Cache QoS architectural values, valid only on the BSP: */
0117     int         x86_cache_max_rmid; /* max index */
0118     int         x86_cache_occ_scale;    /* scale to bytes */
0119     int         x86_cache_mbm_width_offset;
0120     int         x86_power;
0121     unsigned long       loops_per_jiffy;
0122     /* protected processor identification number */
0123     u64         ppin;
0124     /* cpuid returned max cores value: */
0125     u16         x86_max_cores;
0126     u16         apicid;
0127     u16         initial_apicid;
0128     u16         x86_clflush_size;
0129     /* number of cores as seen by the OS: */
0130     u16         booted_cores;
0131     /* Physical processor id: */
0132     u16         phys_proc_id;
0133     /* Logical processor id: */
0134     u16         logical_proc_id;
0135     /* Core id: */
0136     u16         cpu_core_id;
0137     u16         cpu_die_id;
0138     u16         logical_die_id;
0139     /* Index into per_cpu list: */
0140     u16         cpu_index;
0141     /*  Is SMT active on this core? */
0142     bool            smt_active;
0143     u32         microcode;
0144     /* Address space bits used by the cache internally */
0145     u8          x86_cache_bits;
0146     unsigned        initialized : 1;
0147 } __randomize_layout;
0148 
0149 struct cpuid_regs {
0150     u32 eax, ebx, ecx, edx;
0151 };
0152 
0153 enum cpuid_regs_idx {
0154     CPUID_EAX = 0,
0155     CPUID_EBX,
0156     CPUID_ECX,
0157     CPUID_EDX,
0158 };
0159 
0160 #define X86_VENDOR_INTEL    0
0161 #define X86_VENDOR_CYRIX    1
0162 #define X86_VENDOR_AMD      2
0163 #define X86_VENDOR_UMC      3
0164 #define X86_VENDOR_CENTAUR  5
0165 #define X86_VENDOR_TRANSMETA    7
0166 #define X86_VENDOR_NSC      8
0167 #define X86_VENDOR_HYGON    9
0168 #define X86_VENDOR_ZHAOXIN  10
0169 #define X86_VENDOR_VORTEX   11
0170 #define X86_VENDOR_NUM      12
0171 
0172 #define X86_VENDOR_UNKNOWN  0xff
0173 
0174 /*
0175  * capabilities of CPUs
0176  */
0177 extern struct cpuinfo_x86   boot_cpu_data;
0178 extern struct cpuinfo_x86   new_cpu_data;
0179 
0180 extern __u32            cpu_caps_cleared[NCAPINTS + NBUGINTS];
0181 extern __u32            cpu_caps_set[NCAPINTS + NBUGINTS];
0182 
0183 #ifdef CONFIG_SMP
0184 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
0185 #define cpu_data(cpu)       per_cpu(cpu_info, cpu)
0186 #else
0187 #define cpu_info        boot_cpu_data
0188 #define cpu_data(cpu)       boot_cpu_data
0189 #endif
0190 
0191 extern const struct seq_operations cpuinfo_op;
0192 
0193 #define cache_line_size()   (boot_cpu_data.x86_cache_alignment)
0194 
0195 extern void cpu_detect(struct cpuinfo_x86 *c);
0196 
0197 static inline unsigned long long l1tf_pfn_limit(void)
0198 {
0199     return BIT_ULL(boot_cpu_data.x86_cache_bits - 1 - PAGE_SHIFT);
0200 }
0201 
0202 extern void early_cpu_init(void);
0203 extern void identify_boot_cpu(void);
0204 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
0205 extern void print_cpu_info(struct cpuinfo_x86 *);
0206 void print_cpu_msr(struct cpuinfo_x86 *);
0207 
0208 #ifdef CONFIG_X86_32
0209 extern int have_cpuid_p(void);
0210 #else
0211 static inline int have_cpuid_p(void)
0212 {
0213     return 1;
0214 }
0215 #endif
0216 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
0217                 unsigned int *ecx, unsigned int *edx)
0218 {
0219     /* ecx is often an input as well as an output. */
0220     asm volatile("cpuid"
0221         : "=a" (*eax),
0222           "=b" (*ebx),
0223           "=c" (*ecx),
0224           "=d" (*edx)
0225         : "0" (*eax), "2" (*ecx)
0226         : "memory");
0227 }
0228 
0229 #define native_cpuid_reg(reg)                   \
0230 static inline unsigned int native_cpuid_##reg(unsigned int op)  \
0231 {                               \
0232     unsigned int eax = op, ebx, ecx = 0, edx;       \
0233                                 \
0234     native_cpuid(&eax, &ebx, &ecx, &edx);           \
0235                                 \
0236     return reg;                     \
0237 }
0238 
0239 /*
0240  * Native CPUID functions returning a single datum.
0241  */
0242 native_cpuid_reg(eax)
0243 native_cpuid_reg(ebx)
0244 native_cpuid_reg(ecx)
0245 native_cpuid_reg(edx)
0246 
0247 /*
0248  * Friendlier CR3 helpers.
0249  */
0250 static inline unsigned long read_cr3_pa(void)
0251 {
0252     return __read_cr3() & CR3_ADDR_MASK;
0253 }
0254 
0255 static inline unsigned long native_read_cr3_pa(void)
0256 {
0257     return __native_read_cr3() & CR3_ADDR_MASK;
0258 }
0259 
0260 static inline void load_cr3(pgd_t *pgdir)
0261 {
0262     write_cr3(__sme_pa(pgdir));
0263 }
0264 
0265 /*
0266  * Note that while the legacy 'TSS' name comes from 'Task State Segment',
0267  * on modern x86 CPUs the TSS also holds information important to 64-bit mode,
0268  * unrelated to the task-switch mechanism:
0269  */
0270 #ifdef CONFIG_X86_32
0271 /* This is the TSS defined by the hardware. */
0272 struct x86_hw_tss {
0273     unsigned short      back_link, __blh;
0274     unsigned long       sp0;
0275     unsigned short      ss0, __ss0h;
0276     unsigned long       sp1;
0277 
0278     /*
0279      * We don't use ring 1, so ss1 is a convenient scratch space in
0280      * the same cacheline as sp0.  We use ss1 to cache the value in
0281      * MSR_IA32_SYSENTER_CS.  When we context switch
0282      * MSR_IA32_SYSENTER_CS, we first check if the new value being
0283      * written matches ss1, and, if it's not, then we wrmsr the new
0284      * value and update ss1.
0285      *
0286      * The only reason we context switch MSR_IA32_SYSENTER_CS is
0287      * that we set it to zero in vm86 tasks to avoid corrupting the
0288      * stack if we were to go through the sysenter path from vm86
0289      * mode.
0290      */
0291     unsigned short      ss1;    /* MSR_IA32_SYSENTER_CS */
0292 
0293     unsigned short      __ss1h;
0294     unsigned long       sp2;
0295     unsigned short      ss2, __ss2h;
0296     unsigned long       __cr3;
0297     unsigned long       ip;
0298     unsigned long       flags;
0299     unsigned long       ax;
0300     unsigned long       cx;
0301     unsigned long       dx;
0302     unsigned long       bx;
0303     unsigned long       sp;
0304     unsigned long       bp;
0305     unsigned long       si;
0306     unsigned long       di;
0307     unsigned short      es, __esh;
0308     unsigned short      cs, __csh;
0309     unsigned short      ss, __ssh;
0310     unsigned short      ds, __dsh;
0311     unsigned short      fs, __fsh;
0312     unsigned short      gs, __gsh;
0313     unsigned short      ldt, __ldth;
0314     unsigned short      trace;
0315     unsigned short      io_bitmap_base;
0316 
0317 } __attribute__((packed));
0318 #else
0319 struct x86_hw_tss {
0320     u32         reserved1;
0321     u64         sp0;
0322     u64         sp1;
0323 
0324     /*
0325      * Since Linux does not use ring 2, the 'sp2' slot is unused by
0326      * hardware.  entry_SYSCALL_64 uses it as scratch space to stash
0327      * the user RSP value.
0328      */
0329     u64         sp2;
0330 
0331     u64         reserved2;
0332     u64         ist[7];
0333     u32         reserved3;
0334     u32         reserved4;
0335     u16         reserved5;
0336     u16         io_bitmap_base;
0337 
0338 } __attribute__((packed));
0339 #endif
0340 
0341 /*
0342  * IO-bitmap sizes:
0343  */
0344 #define IO_BITMAP_BITS          65536
0345 #define IO_BITMAP_BYTES         (IO_BITMAP_BITS / BITS_PER_BYTE)
0346 #define IO_BITMAP_LONGS         (IO_BITMAP_BYTES / sizeof(long))
0347 
0348 #define IO_BITMAP_OFFSET_VALID_MAP              \
0349     (offsetof(struct tss_struct, io_bitmap.bitmap) -    \
0350      offsetof(struct tss_struct, x86_tss))
0351 
0352 #define IO_BITMAP_OFFSET_VALID_ALL              \
0353     (offsetof(struct tss_struct, io_bitmap.mapall) -    \
0354      offsetof(struct tss_struct, x86_tss))
0355 
0356 #ifdef CONFIG_X86_IOPL_IOPERM
0357 /*
0358  * sizeof(unsigned long) coming from an extra "long" at the end of the
0359  * iobitmap. The limit is inclusive, i.e. the last valid byte.
0360  */
0361 # define __KERNEL_TSS_LIMIT \
0362     (IO_BITMAP_OFFSET_VALID_ALL + IO_BITMAP_BYTES + \
0363      sizeof(unsigned long) - 1)
0364 #else
0365 # define __KERNEL_TSS_LIMIT \
0366     (offsetof(struct tss_struct, x86_tss) + sizeof(struct x86_hw_tss) - 1)
0367 #endif
0368 
0369 /* Base offset outside of TSS_LIMIT so unpriviledged IO causes #GP */
0370 #define IO_BITMAP_OFFSET_INVALID    (__KERNEL_TSS_LIMIT + 1)
0371 
0372 struct entry_stack {
0373     char    stack[PAGE_SIZE];
0374 };
0375 
0376 struct entry_stack_page {
0377     struct entry_stack stack;
0378 } __aligned(PAGE_SIZE);
0379 
0380 /*
0381  * All IO bitmap related data stored in the TSS:
0382  */
0383 struct x86_io_bitmap {
0384     /* The sequence number of the last active bitmap. */
0385     u64         prev_sequence;
0386 
0387     /*
0388      * Store the dirty size of the last io bitmap offender. The next
0389      * one will have to do the cleanup as the switch out to a non io
0390      * bitmap user will just set x86_tss.io_bitmap_base to a value
0391      * outside of the TSS limit. So for sane tasks there is no need to
0392      * actually touch the io_bitmap at all.
0393      */
0394     unsigned int        prev_max;
0395 
0396     /*
0397      * The extra 1 is there because the CPU will access an
0398      * additional byte beyond the end of the IO permission
0399      * bitmap. The extra byte must be all 1 bits, and must
0400      * be within the limit.
0401      */
0402     unsigned long       bitmap[IO_BITMAP_LONGS + 1];
0403 
0404     /*
0405      * Special I/O bitmap to emulate IOPL(3). All bytes zero,
0406      * except the additional byte at the end.
0407      */
0408     unsigned long       mapall[IO_BITMAP_LONGS + 1];
0409 };
0410 
0411 struct tss_struct {
0412     /*
0413      * The fixed hardware portion.  This must not cross a page boundary
0414      * at risk of violating the SDM's advice and potentially triggering
0415      * errata.
0416      */
0417     struct x86_hw_tss   x86_tss;
0418 
0419     struct x86_io_bitmap    io_bitmap;
0420 } __aligned(PAGE_SIZE);
0421 
0422 DECLARE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw);
0423 
0424 /* Per CPU interrupt stacks */
0425 struct irq_stack {
0426     char        stack[IRQ_STACK_SIZE];
0427 } __aligned(IRQ_STACK_SIZE);
0428 
0429 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
0430 
0431 #ifdef CONFIG_X86_64
0432 struct fixed_percpu_data {
0433     /*
0434      * GCC hardcodes the stack canary as %gs:40.  Since the
0435      * irq_stack is the object at %gs:0, we reserve the bottom
0436      * 48 bytes of the irq stack for the canary.
0437      *
0438      * Once we are willing to require -mstack-protector-guard-symbol=
0439      * support for x86_64 stackprotector, we can get rid of this.
0440      */
0441     char        gs_base[40];
0442     unsigned long   stack_canary;
0443 };
0444 
0445 DECLARE_PER_CPU_FIRST(struct fixed_percpu_data, fixed_percpu_data) __visible;
0446 DECLARE_INIT_PER_CPU(fixed_percpu_data);
0447 
0448 static inline unsigned long cpu_kernelmode_gs_base(int cpu)
0449 {
0450     return (unsigned long)per_cpu(fixed_percpu_data.gs_base, cpu);
0451 }
0452 
0453 DECLARE_PER_CPU(void *, hardirq_stack_ptr);
0454 DECLARE_PER_CPU(bool, hardirq_stack_inuse);
0455 extern asmlinkage void ignore_sysret(void);
0456 
0457 /* Save actual FS/GS selectors and bases to current->thread */
0458 void current_save_fsgs(void);
0459 #else   /* X86_64 */
0460 #ifdef CONFIG_STACKPROTECTOR
0461 DECLARE_PER_CPU(unsigned long, __stack_chk_guard);
0462 #endif
0463 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack_ptr);
0464 DECLARE_PER_CPU(struct irq_stack *, softirq_stack_ptr);
0465 #endif  /* !X86_64 */
0466 
0467 struct perf_event;
0468 
0469 struct thread_struct {
0470     /* Cached TLS descriptors: */
0471     struct desc_struct  tls_array[GDT_ENTRY_TLS_ENTRIES];
0472 #ifdef CONFIG_X86_32
0473     unsigned long       sp0;
0474 #endif
0475     unsigned long       sp;
0476 #ifdef CONFIG_X86_32
0477     unsigned long       sysenter_cs;
0478 #else
0479     unsigned short      es;
0480     unsigned short      ds;
0481     unsigned short      fsindex;
0482     unsigned short      gsindex;
0483 #endif
0484 
0485 #ifdef CONFIG_X86_64
0486     unsigned long       fsbase;
0487     unsigned long       gsbase;
0488 #else
0489     /*
0490      * XXX: this could presumably be unsigned short.  Alternatively,
0491      * 32-bit kernels could be taught to use fsindex instead.
0492      */
0493     unsigned long fs;
0494     unsigned long gs;
0495 #endif
0496 
0497     /* Save middle states of ptrace breakpoints */
0498     struct perf_event   *ptrace_bps[HBP_NUM];
0499     /* Debug status used for traps, single steps, etc... */
0500     unsigned long           virtual_dr6;
0501     /* Keep track of the exact dr7 value set by the user */
0502     unsigned long           ptrace_dr7;
0503     /* Fault info: */
0504     unsigned long       cr2;
0505     unsigned long       trap_nr;
0506     unsigned long       error_code;
0507 #ifdef CONFIG_VM86
0508     /* Virtual 86 mode info */
0509     struct vm86     *vm86;
0510 #endif
0511     /* IO permissions: */
0512     struct io_bitmap    *io_bitmap;
0513 
0514     /*
0515      * IOPL. Privilege level dependent I/O permission which is
0516      * emulated via the I/O bitmap to prevent user space from disabling
0517      * interrupts.
0518      */
0519     unsigned long       iopl_emul;
0520 
0521     unsigned int        iopl_warn:1;
0522     unsigned int        sig_on_uaccess_err:1;
0523 
0524     /*
0525      * Protection Keys Register for Userspace.  Loaded immediately on
0526      * context switch. Store it in thread_struct to avoid a lookup in
0527      * the tasks's FPU xstate buffer. This value is only valid when a
0528      * task is scheduled out. For 'current' the authoritative source of
0529      * PKRU is the hardware itself.
0530      */
0531     u32         pkru;
0532 
0533     /* Floating point and extended processor state */
0534     struct fpu      fpu;
0535     /*
0536      * WARNING: 'fpu' is dynamically-sized.  It *MUST* be at
0537      * the end.
0538      */
0539 };
0540 
0541 extern void fpu_thread_struct_whitelist(unsigned long *offset, unsigned long *size);
0542 
0543 static inline void arch_thread_struct_whitelist(unsigned long *offset,
0544                         unsigned long *size)
0545 {
0546     fpu_thread_struct_whitelist(offset, size);
0547 }
0548 
0549 static inline void
0550 native_load_sp0(unsigned long sp0)
0551 {
0552     this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0);
0553 }
0554 
0555 static __always_inline void native_swapgs(void)
0556 {
0557 #ifdef CONFIG_X86_64
0558     asm volatile("swapgs" ::: "memory");
0559 #endif
0560 }
0561 
0562 static __always_inline unsigned long current_top_of_stack(void)
0563 {
0564     /*
0565      *  We can't read directly from tss.sp0: sp0 on x86_32 is special in
0566      *  and around vm86 mode and sp0 on x86_64 is special because of the
0567      *  entry trampoline.
0568      */
0569     return this_cpu_read_stable(cpu_current_top_of_stack);
0570 }
0571 
0572 static __always_inline bool on_thread_stack(void)
0573 {
0574     return (unsigned long)(current_top_of_stack() -
0575                    current_stack_pointer) < THREAD_SIZE;
0576 }
0577 
0578 #ifdef CONFIG_PARAVIRT_XXL
0579 #include <asm/paravirt.h>
0580 #else
0581 #define __cpuid         native_cpuid
0582 
0583 static inline void load_sp0(unsigned long sp0)
0584 {
0585     native_load_sp0(sp0);
0586 }
0587 
0588 #endif /* CONFIG_PARAVIRT_XXL */
0589 
0590 /* Free all resources held by a thread. */
0591 extern void release_thread(struct task_struct *);
0592 
0593 unsigned long __get_wchan(struct task_struct *p);
0594 
0595 /*
0596  * Generic CPUID function
0597  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
0598  * resulting in stale register contents being returned.
0599  */
0600 static inline void cpuid(unsigned int op,
0601              unsigned int *eax, unsigned int *ebx,
0602              unsigned int *ecx, unsigned int *edx)
0603 {
0604     *eax = op;
0605     *ecx = 0;
0606     __cpuid(eax, ebx, ecx, edx);
0607 }
0608 
0609 /* Some CPUID calls want 'count' to be placed in ecx */
0610 static inline void cpuid_count(unsigned int op, int count,
0611                    unsigned int *eax, unsigned int *ebx,
0612                    unsigned int *ecx, unsigned int *edx)
0613 {
0614     *eax = op;
0615     *ecx = count;
0616     __cpuid(eax, ebx, ecx, edx);
0617 }
0618 
0619 /*
0620  * CPUID functions returning a single datum
0621  */
0622 static inline unsigned int cpuid_eax(unsigned int op)
0623 {
0624     unsigned int eax, ebx, ecx, edx;
0625 
0626     cpuid(op, &eax, &ebx, &ecx, &edx);
0627 
0628     return eax;
0629 }
0630 
0631 static inline unsigned int cpuid_ebx(unsigned int op)
0632 {
0633     unsigned int eax, ebx, ecx, edx;
0634 
0635     cpuid(op, &eax, &ebx, &ecx, &edx);
0636 
0637     return ebx;
0638 }
0639 
0640 static inline unsigned int cpuid_ecx(unsigned int op)
0641 {
0642     unsigned int eax, ebx, ecx, edx;
0643 
0644     cpuid(op, &eax, &ebx, &ecx, &edx);
0645 
0646     return ecx;
0647 }
0648 
0649 static inline unsigned int cpuid_edx(unsigned int op)
0650 {
0651     unsigned int eax, ebx, ecx, edx;
0652 
0653     cpuid(op, &eax, &ebx, &ecx, &edx);
0654 
0655     return edx;
0656 }
0657 
0658 extern void select_idle_routine(const struct cpuinfo_x86 *c);
0659 extern void amd_e400_c1e_apic_setup(void);
0660 
0661 extern unsigned long        boot_option_idle_override;
0662 
0663 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
0664              IDLE_POLL};
0665 
0666 extern void enable_sep_cpu(void);
0667 extern int sysenter_setup(void);
0668 
0669 
0670 /* Defined in head.S */
0671 extern struct desc_ptr      early_gdt_descr;
0672 
0673 extern void switch_to_new_gdt(int);
0674 extern void load_direct_gdt(int);
0675 extern void load_fixmap_gdt(int);
0676 extern void load_percpu_segment(int);
0677 extern void cpu_init(void);
0678 extern void cpu_init_secondary(void);
0679 extern void cpu_init_exception_handling(void);
0680 extern void cr4_init(void);
0681 
0682 static inline unsigned long get_debugctlmsr(void)
0683 {
0684     unsigned long debugctlmsr = 0;
0685 
0686 #ifndef CONFIG_X86_DEBUGCTLMSR
0687     if (boot_cpu_data.x86 < 6)
0688         return 0;
0689 #endif
0690     rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
0691 
0692     return debugctlmsr;
0693 }
0694 
0695 static inline void update_debugctlmsr(unsigned long debugctlmsr)
0696 {
0697 #ifndef CONFIG_X86_DEBUGCTLMSR
0698     if (boot_cpu_data.x86 < 6)
0699         return;
0700 #endif
0701     wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
0702 }
0703 
0704 extern void set_task_blockstep(struct task_struct *task, bool on);
0705 
0706 /* Boot loader type from the setup header: */
0707 extern int          bootloader_type;
0708 extern int          bootloader_version;
0709 
0710 extern char         ignore_fpu_irq;
0711 
0712 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
0713 #define ARCH_HAS_PREFETCHW
0714 #define ARCH_HAS_SPINLOCK_PREFETCH
0715 
0716 #ifdef CONFIG_X86_32
0717 # define BASE_PREFETCH      ""
0718 # define ARCH_HAS_PREFETCH
0719 #else
0720 # define BASE_PREFETCH      "prefetcht0 %P1"
0721 #endif
0722 
0723 /*
0724  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
0725  *
0726  * It's not worth to care about 3dnow prefetches for the K6
0727  * because they are microcoded there and very slow.
0728  */
0729 static inline void prefetch(const void *x)
0730 {
0731     alternative_input(BASE_PREFETCH, "prefetchnta %P1",
0732               X86_FEATURE_XMM,
0733               "m" (*(const char *)x));
0734 }
0735 
0736 /*
0737  * 3dnow prefetch to get an exclusive cache line.
0738  * Useful for spinlocks to avoid one state transition in the
0739  * cache coherency protocol:
0740  */
0741 static __always_inline void prefetchw(const void *x)
0742 {
0743     alternative_input(BASE_PREFETCH, "prefetchw %P1",
0744               X86_FEATURE_3DNOWPREFETCH,
0745               "m" (*(const char *)x));
0746 }
0747 
0748 static inline void spin_lock_prefetch(const void *x)
0749 {
0750     prefetchw(x);
0751 }
0752 
0753 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
0754                TOP_OF_KERNEL_STACK_PADDING)
0755 
0756 #define task_top_of_stack(task) ((unsigned long)(task_pt_regs(task) + 1))
0757 
0758 #define task_pt_regs(task) \
0759 ({                                  \
0760     unsigned long __ptr = (unsigned long)task_stack_page(task); \
0761     __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;     \
0762     ((struct pt_regs *)__ptr) - 1;                  \
0763 })
0764 
0765 #ifdef CONFIG_X86_32
0766 #define INIT_THREAD  {                            \
0767     .sp0            = TOP_OF_INIT_STACK,              \
0768     .sysenter_cs        = __KERNEL_CS,                \
0769 }
0770 
0771 #define KSTK_ESP(task)      (task_pt_regs(task)->sp)
0772 
0773 #else
0774 #define INIT_THREAD { }
0775 
0776 extern unsigned long KSTK_ESP(struct task_struct *task);
0777 
0778 #endif /* CONFIG_X86_64 */
0779 
0780 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
0781                            unsigned long new_sp);
0782 
0783 /*
0784  * This decides where the kernel will search for a free chunk of vm
0785  * space during mmap's.
0786  */
0787 #define __TASK_UNMAPPED_BASE(task_size) (PAGE_ALIGN(task_size / 3))
0788 #define TASK_UNMAPPED_BASE      __TASK_UNMAPPED_BASE(TASK_SIZE_LOW)
0789 
0790 #define KSTK_EIP(task)      (task_pt_regs(task)->ip)
0791 
0792 /* Get/set a process' ability to use the timestamp counter instruction */
0793 #define GET_TSC_CTL(adr)    get_tsc_mode((adr))
0794 #define SET_TSC_CTL(val)    set_tsc_mode((val))
0795 
0796 extern int get_tsc_mode(unsigned long adr);
0797 extern int set_tsc_mode(unsigned int val);
0798 
0799 DECLARE_PER_CPU(u64, msr_misc_features_shadow);
0800 
0801 extern u16 get_llc_id(unsigned int cpu);
0802 
0803 #ifdef CONFIG_CPU_SUP_AMD
0804 extern u32 amd_get_nodes_per_socket(void);
0805 extern u32 amd_get_highest_perf(void);
0806 #else
0807 static inline u32 amd_get_nodes_per_socket(void)    { return 0; }
0808 static inline u32 amd_get_highest_perf(void)        { return 0; }
0809 #endif
0810 
0811 #define for_each_possible_hypervisor_cpuid_base(function) \
0812     for (function = 0x40000000; function < 0x40010000; function += 0x100)
0813 
0814 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
0815 {
0816     uint32_t base, eax, signature[3];
0817 
0818     for_each_possible_hypervisor_cpuid_base(base) {
0819         cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
0820 
0821         if (!memcmp(sig, signature, 12) &&
0822             (leaves == 0 || ((eax - base) >= leaves)))
0823             return base;
0824     }
0825 
0826     return 0;
0827 }
0828 
0829 extern unsigned long arch_align_stack(unsigned long sp);
0830 void free_init_pages(const char *what, unsigned long begin, unsigned long end);
0831 extern void free_kernel_image_pages(const char *what, void *begin, void *end);
0832 
0833 void default_idle(void);
0834 #ifdef  CONFIG_XEN
0835 bool xen_set_default_idle(void);
0836 #else
0837 #define xen_set_default_idle 0
0838 #endif
0839 
0840 void __noreturn stop_this_cpu(void *dummy);
0841 void microcode_check(void);
0842 
0843 enum l1tf_mitigations {
0844     L1TF_MITIGATION_OFF,
0845     L1TF_MITIGATION_FLUSH_NOWARN,
0846     L1TF_MITIGATION_FLUSH,
0847     L1TF_MITIGATION_FLUSH_NOSMT,
0848     L1TF_MITIGATION_FULL,
0849     L1TF_MITIGATION_FULL_FORCE
0850 };
0851 
0852 extern enum l1tf_mitigations l1tf_mitigation;
0853 
0854 enum mds_mitigations {
0855     MDS_MITIGATION_OFF,
0856     MDS_MITIGATION_FULL,
0857     MDS_MITIGATION_VMWERV,
0858 };
0859 
0860 #ifdef CONFIG_X86_SGX
0861 int arch_memory_failure(unsigned long pfn, int flags);
0862 #define arch_memory_failure arch_memory_failure
0863 
0864 bool arch_is_platform_page(u64 paddr);
0865 #define arch_is_platform_page arch_is_platform_page
0866 #endif
0867 
0868 #endif /* _ASM_X86_PROCESSOR_H */
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