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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_PROCESSOR_FLAGS_H
0003 #define _ASM_X86_PROCESSOR_FLAGS_H
0004 
0005 #include <uapi/asm/processor-flags.h>
0006 #include <linux/mem_encrypt.h>
0007 
0008 #ifdef CONFIG_VM86
0009 #define X86_VM_MASK X86_EFLAGS_VM
0010 #else
0011 #define X86_VM_MASK 0 /* No VM86 support */
0012 #endif
0013 
0014 /*
0015  * CR3's layout varies depending on several things.
0016  *
0017  * If CR4.PCIDE is set (64-bit only), then CR3[11:0] is the address space ID.
0018  * If PAE is enabled, then CR3[11:5] is part of the PDPT address
0019  * (i.e. it's 32-byte aligned, not page-aligned) and CR3[4:0] is ignored.
0020  * Otherwise (non-PAE, non-PCID), CR3[3] is PWT, CR3[4] is PCD, and
0021  * CR3[2:0] and CR3[11:5] are ignored.
0022  *
0023  * In all cases, Linux puts zeros in the low ignored bits and in PWT and PCD.
0024  *
0025  * CR3[63] is always read as zero.  If CR4.PCIDE is set, then CR3[63] may be
0026  * written as 1 to prevent the write to CR3 from flushing the TLB.
0027  *
0028  * On systems with SME, one bit (in a variable position!) is stolen to indicate
0029  * that the top-level paging structure is encrypted.
0030  *
0031  * All of the remaining bits indicate the physical address of the top-level
0032  * paging structure.
0033  *
0034  * CR3_ADDR_MASK is the mask used by read_cr3_pa().
0035  */
0036 #ifdef CONFIG_X86_64
0037 /* Mask off the address space ID and SME encryption bits. */
0038 #define CR3_ADDR_MASK   __sme_clr(0x7FFFFFFFFFFFF000ull)
0039 #define CR3_PCID_MASK   0xFFFull
0040 #define CR3_NOFLUSH BIT_ULL(63)
0041 
0042 #else
0043 /*
0044  * CR3_ADDR_MASK needs at least bits 31:5 set on PAE systems, and we save
0045  * a tiny bit of code size by setting all the bits.
0046  */
0047 #define CR3_ADDR_MASK   0xFFFFFFFFull
0048 #define CR3_PCID_MASK   0ull
0049 #define CR3_NOFLUSH 0
0050 #endif
0051 
0052 #ifdef CONFIG_PAGE_TABLE_ISOLATION
0053 # define X86_CR3_PTI_PCID_USER_BIT  11
0054 #endif
0055 
0056 #endif /* _ASM_X86_PROCESSOR_FLAGS_H */