include/asm/platform_sst_audio.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * platform_sst_audio.h:  sst audio platform data header file
0004  *
0005  * Copyright (C) 2012-14 Intel Corporation
0006  * Author: Jeeja KP <jeeja.kp@intel.com>
0007  *  Omair Mohammed Abdullah <omair.m.abdullah@intel.com>
0008  *  Vinod Koul ,vinod.koul@intel.com>
0009  */
0010 #ifndef _PLATFORM_SST_AUDIO_H_
0011 #define _PLATFORM_SST_AUDIO_H_
0012
0013 #define MAX_NUM_STREAMS_MRFLD   25
0014 #define MAX_NUM_STREAMS MAX_NUM_STREAMS_MRFLD
0015
0016 enum sst_audio_task_id_mrfld {
0017     SST_TASK_ID_NONE = 0,
0018     SST_TASK_ID_SBA = 1,
0019     SST_TASK_ID_MEDIA = 3,
0020     SST_TASK_ID_MAX = SST_TASK_ID_MEDIA,
0021 };
0022
0023 /* Device IDs for Merrifield are Pipe IDs,
0024  * ref: DSP spec v0.75 */
0025 enum sst_audio_device_id_mrfld {
0026     /* Output pipeline IDs */
0027     PIPE_ID_OUT_START = 0x0,
0028     PIPE_CODEC_OUT0 = 0x2,
0029     PIPE_CODEC_OUT1 = 0x3,
0030     PIPE_SPROT_LOOP_OUT = 0x4,
0031     PIPE_MEDIA_LOOP1_OUT = 0x5,
0032     PIPE_MEDIA_LOOP2_OUT = 0x6,
0033     PIPE_VOIP_OUT = 0xC,
0034     PIPE_PCM0_OUT = 0xD,
0035     PIPE_PCM1_OUT = 0xE,
0036     PIPE_PCM2_OUT = 0xF,
0037     PIPE_MEDIA0_OUT = 0x12,
0038     PIPE_MEDIA1_OUT = 0x13,
0039 /* Input Pipeline IDs */
0040     PIPE_ID_IN_START = 0x80,
0041     PIPE_CODEC_IN0 = 0x82,
0042     PIPE_CODEC_IN1 = 0x83,
0043     PIPE_SPROT_LOOP_IN = 0x84,
0044     PIPE_MEDIA_LOOP1_IN = 0x85,
0045     PIPE_MEDIA_LOOP2_IN = 0x86,
0046     PIPE_VOIP_IN = 0x8C,
0047     PIPE_PCM0_IN = 0x8D,
0048     PIPE_PCM1_IN = 0x8E,
0049     PIPE_MEDIA0_IN = 0x8F,
0050     PIPE_MEDIA1_IN = 0x90,
0051     PIPE_MEDIA2_IN = 0x91,
0052     PIPE_MEDIA3_IN = 0x9C,
0053     PIPE_RSVD = 0xFF,
0054 };
0055
0056 /* The stream map for each platform consists of an array of the below
0057  * stream map structure.
0058  */
0059 struct sst_dev_stream_map {
0060     u8 dev_num;     /* device id */
0061     u8 subdev_num;      /* substream */
0062     u8 direction;
0063     u8 device_id;       /* fw id */
0064     u8 task_id;     /* fw task */
0065     u8 status;
0066 };
0067
0068 struct sst_platform_data {
0069     /* Intel software platform id*/
0070     struct sst_dev_stream_map *pdev_strm_map;
0071     unsigned int strm_map_size;
0072 };
0073
0074 struct sst_info {
0075     u32 iram_start;
0076     u32 iram_end;
0077     bool iram_use;
0078     u32 dram_start;
0079     u32 dram_end;
0080     bool dram_use;
0081     u32 imr_start;
0082     u32 imr_end;
0083     bool imr_use;
0084     u32 mailbox_start;
0085     bool use_elf;
0086     bool lpe_viewpt_rqd;
0087     unsigned int max_streams;
0088     u32 dma_max_len;
0089     u8 num_probes;
0090 };
0091
0092 struct sst_lib_dnld_info {
0093     unsigned int mod_base;
0094     unsigned int mod_end;
0095     unsigned int mod_table_offset;
0096     unsigned int mod_table_size;
0097     bool mod_ddr_dnld;
0098 };
0099
0100 struct sst_res_info {
0101     unsigned int shim_offset;
0102     unsigned int shim_size;
0103     unsigned int shim_phy_addr;
0104     unsigned int ssp0_offset;
0105     unsigned int ssp0_size;
0106     unsigned int dma0_offset;
0107     unsigned int dma0_size;
0108     unsigned int dma1_offset;
0109     unsigned int dma1_size;
0110     unsigned int iram_offset;
0111     unsigned int iram_size;
0112     unsigned int dram_offset;
0113     unsigned int dram_size;
0114     unsigned int mbox_offset;
0115     unsigned int mbox_size;
0116     unsigned int acpi_lpe_res_index;
0117     unsigned int acpi_ddr_index;
0118     unsigned int acpi_ipc_irq_index;
0119 };
0120
0121 struct sst_ipc_info {
0122     int ipc_offset;
0123     unsigned int mbox_recv_off;
0124 };
0125
0126 struct sst_platform_info {
0127     const struct sst_info *probe_data;
0128     const struct sst_ipc_info *ipc_info;
0129     const struct sst_res_info *res_info;
0130     const struct sst_lib_dnld_info *lib_info;
0131     const char *platform;
0132     bool streams_lost_on_suspend;
0133 };
0134 int add_sst_platform_device(void);
0135 #endif
0136