include/asm/perf_event_p4.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Netburst Performance Events (P4, old Xeon)
0004  */
0005
0006 #ifndef PERF_EVENT_P4_H
0007 #define PERF_EVENT_P4_H
0008
0009 #include <linux/cpu.h>
0010 #include <linux/bitops.h>
0011
0012 /*
0013  * NetBurst has performance MSRs shared between
0014  * threads if HT is turned on, ie for both logical
0015  * processors (mem: in turn in Atom with HT support
0016  * perf-MSRs are not shared and every thread has its
0017  * own perf-MSRs set)
0018  */
0019 #define ARCH_P4_TOTAL_ESCR  (46)
0020 #define ARCH_P4_RESERVED_ESCR   (2) /* IQ_ESCR(0,1) not always present */
0021 #define ARCH_P4_MAX_ESCR    (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
0022 #define ARCH_P4_MAX_CCCR    (18)
0023
0024 #define ARCH_P4_CNTRVAL_BITS    (40)
0025 #define ARCH_P4_CNTRVAL_MASK    ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
0026 #define ARCH_P4_UNFLAGGED_BIT   ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
0027
0028 #define P4_ESCR_EVENT_MASK  0x7e000000ULL
0029 #define P4_ESCR_EVENT_SHIFT 25
0030 #define P4_ESCR_EVENTMASK_MASK  0x01fffe00ULL
0031 #define P4_ESCR_EVENTMASK_SHIFT 9
0032 #define P4_ESCR_TAG_MASK    0x000001e0ULL
0033 #define P4_ESCR_TAG_SHIFT   5
0034 #define P4_ESCR_TAG_ENABLE  0x00000010ULL
0035 #define P4_ESCR_T0_OS       0x00000008ULL
0036 #define P4_ESCR_T0_USR      0x00000004ULL
0037 #define P4_ESCR_T1_OS       0x00000002ULL
0038 #define P4_ESCR_T1_USR      0x00000001ULL
0039
0040 #define P4_ESCR_EVENT(v)    ((v) << P4_ESCR_EVENT_SHIFT)
0041 #define P4_ESCR_EMASK(v)    ((v) << P4_ESCR_EVENTMASK_SHIFT)
0042 #define P4_ESCR_TAG(v)      ((v) << P4_ESCR_TAG_SHIFT)
0043
0044 #define P4_CCCR_OVF         0x80000000ULL
0045 #define P4_CCCR_CASCADE         0x40000000ULL
0046 #define P4_CCCR_OVF_PMI_T0      0x04000000ULL
0047 #define P4_CCCR_OVF_PMI_T1      0x08000000ULL
0048 #define P4_CCCR_FORCE_OVF       0x02000000ULL
0049 #define P4_CCCR_EDGE            0x01000000ULL
0050 #define P4_CCCR_THRESHOLD_MASK      0x00f00000ULL
0051 #define P4_CCCR_THRESHOLD_SHIFT     20
0052 #define P4_CCCR_COMPLEMENT      0x00080000ULL
0053 #define P4_CCCR_COMPARE         0x00040000ULL
0054 #define P4_CCCR_ESCR_SELECT_MASK    0x0000e000ULL
0055 #define P4_CCCR_ESCR_SELECT_SHIFT   13
0056 #define P4_CCCR_ENABLE          0x00001000ULL
0057 #define P4_CCCR_THREAD_SINGLE       0x00010000ULL
0058 #define P4_CCCR_THREAD_BOTH     0x00020000ULL
0059 #define P4_CCCR_THREAD_ANY      0x00030000ULL
0060 #define P4_CCCR_RESERVED        0x00000fffULL
0061
0062 #define P4_CCCR_THRESHOLD(v)        ((v) << P4_CCCR_THRESHOLD_SHIFT)
0063 #define P4_CCCR_ESEL(v)         ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
0064
0065 #define P4_GEN_ESCR_EMASK(class, name, bit) \
0066     class##__##name = ((1ULL << bit) << P4_ESCR_EVENTMASK_SHIFT)
0067 #define P4_ESCR_EMASK_BIT(class, name)      class##__##name
0068
0069 /*
0070  * config field is 64bit width and consists of
0071  * HT << 63 | ESCR << 32 | CCCR
0072  * where HT is HyperThreading bit (since ESCR
0073  * has it reserved we may use it for own purpose)
0074  *
0075  * note that this is NOT the addresses of respective
0076  * ESCR and CCCR but rather an only packed value should
0077  * be unpacked and written to a proper addresses
0078  *
0079  * the base idea is to pack as much info as possible
0080  */
0081 #define p4_config_pack_escr(v)      (((u64)(v)) << 32)
0082 #define p4_config_pack_cccr(v)      (((u64)(v)) & 0xffffffffULL)
0083 #define p4_config_unpack_escr(v)    (((u64)(v)) >> 32)
0084 #define p4_config_unpack_cccr(v)    (((u64)(v)) & 0xffffffffULL)
0085
0086 #define p4_config_unpack_emask(v)           \
0087     ({                      \
0088         u32 t = p4_config_unpack_escr((v)); \
0089         t = t &  P4_ESCR_EVENTMASK_MASK;    \
0090         t = t >> P4_ESCR_EVENTMASK_SHIFT;   \
0091         t;                  \
0092     })
0093
0094 #define p4_config_unpack_event(v)           \
0095     ({                      \
0096         u32 t = p4_config_unpack_escr((v)); \
0097         t = t &  P4_ESCR_EVENT_MASK;        \
0098         t = t >> P4_ESCR_EVENT_SHIFT;       \
0099         t;                  \
0100     })
0101
0102 #define P4_CONFIG_HT_SHIFT      63
0103 #define P4_CONFIG_HT            (1ULL << P4_CONFIG_HT_SHIFT)
0104
0105 /*
0106  * If an event has alias it should be marked
0107  * with a special bit. (Don't forget to check
0108  * P4_PEBS_CONFIG_MASK and related bits on
0109  * modification.)
0110  */
0111 #define P4_CONFIG_ALIASABLE     (1ULL << 9)
0112
0113 /*
0114  * The bits we allow to pass for RAW events
0115  */
0116 #define P4_CONFIG_MASK_ESCR     \
0117     P4_ESCR_EVENT_MASK  |   \
0118     P4_ESCR_EVENTMASK_MASK  |   \
0119     P4_ESCR_TAG_MASK    |   \
0120     P4_ESCR_TAG_ENABLE
0121
0122 #define P4_CONFIG_MASK_CCCR     \
0123     P4_CCCR_EDGE        |   \
0124     P4_CCCR_THRESHOLD_MASK  |   \
0125     P4_CCCR_COMPLEMENT  |   \
0126     P4_CCCR_COMPARE     |   \
0127     P4_CCCR_THREAD_ANY  |   \
0128     P4_CCCR_RESERVED
0129
0130 /* some dangerous bits are reserved for kernel internals */
0131 #define P4_CONFIG_MASK                    \
0132     (p4_config_pack_escr(P4_CONFIG_MASK_ESCR))  | \
0133     (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR))
0134
0135 /*
0136  * In case of event aliasing we need to preserve some
0137  * caller bits, otherwise the mapping won't be complete.
0138  */
0139 #define P4_CONFIG_EVENT_ALIAS_MASK            \
0140     (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)   | \
0141      p4_config_pack_cccr(P4_CCCR_EDGE       | \
0142                  P4_CCCR_THRESHOLD_MASK | \
0143                  P4_CCCR_COMPLEMENT     | \
0144                  P4_CCCR_COMPARE))
0145
0146 #define  P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS         \
0147     ((P4_CONFIG_HT)                 | \
0148      p4_config_pack_escr(P4_ESCR_T0_OS      | \
0149                  P4_ESCR_T0_USR     | \
0150                  P4_ESCR_T1_OS      | \
0151                  P4_ESCR_T1_USR)        | \
0152      p4_config_pack_cccr(P4_CCCR_OVF        | \
0153                  P4_CCCR_CASCADE        | \
0154                  P4_CCCR_FORCE_OVF      | \
0155                  P4_CCCR_THREAD_ANY     | \
0156                  P4_CCCR_OVF_PMI_T0     | \
0157                  P4_CCCR_OVF_PMI_T1     | \
0158                  P4_CONFIG_ALIASABLE))
0159
0160 static inline bool p4_is_event_cascaded(u64 config)
0161 {
0162     u32 cccr = p4_config_unpack_cccr(config);
0163     return !!(cccr & P4_CCCR_CASCADE);
0164 }
0165
0166 static inline int p4_ht_config_thread(u64 config)
0167 {
0168     return !!(config & P4_CONFIG_HT);
0169 }
0170
0171 static inline u64 p4_set_ht_bit(u64 config)
0172 {
0173     return config | P4_CONFIG_HT;
0174 }
0175
0176 static inline u64 p4_clear_ht_bit(u64 config)
0177 {
0178     return config & ~P4_CONFIG_HT;
0179 }
0180
0181 static inline int p4_ht_active(void)
0182 {
0183 #ifdef CONFIG_SMP
0184     return smp_num_siblings > 1;
0185 #endif
0186     return 0;
0187 }
0188
0189 static inline int p4_ht_thread(int cpu)
0190 {
0191 #ifdef CONFIG_SMP
0192     if (smp_num_siblings == 2)
0193         return cpu != cpumask_first(this_cpu_cpumask_var_ptr(cpu_sibling_map));
0194 #endif
0195     return 0;
0196 }
0197
0198 static inline int p4_should_swap_ts(u64 config, int cpu)
0199 {
0200     return p4_ht_config_thread(config) ^ p4_ht_thread(cpu);
0201 }
0202
0203 static inline u32 p4_default_cccr_conf(int cpu)
0204 {
0205     /*
0206      * Note that P4_CCCR_THREAD_ANY is "required" on
0207      * non-HT machines (on HT machines we count TS events
0208      * regardless the state of second logical processor
0209      */
0210     u32 cccr = P4_CCCR_THREAD_ANY;
0211
0212     if (!p4_ht_thread(cpu))
0213         cccr |= P4_CCCR_OVF_PMI_T0;
0214     else
0215         cccr |= P4_CCCR_OVF_PMI_T1;
0216
0217     return cccr;
0218 }
0219
0220 static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
0221 {
0222     u32 escr = 0;
0223
0224     if (!p4_ht_thread(cpu)) {
0225         if (!exclude_os)
0226             escr |= P4_ESCR_T0_OS;
0227         if (!exclude_usr)
0228             escr |= P4_ESCR_T0_USR;
0229     } else {
0230         if (!exclude_os)
0231             escr |= P4_ESCR_T1_OS;
0232         if (!exclude_usr)
0233             escr |= P4_ESCR_T1_USR;
0234     }
0235
0236     return escr;
0237 }
0238
0239 /*
0240  * This are the events which should be used in "Event Select"
0241  * field of ESCR register, they are like unique keys which allow
0242  * the kernel to determinate which CCCR and COUNTER should be
0243  * used to track an event
0244  */
0245 enum P4_EVENTS {
0246     P4_EVENT_TC_DELIVER_MODE,
0247     P4_EVENT_BPU_FETCH_REQUEST,
0248     P4_EVENT_ITLB_REFERENCE,
0249     P4_EVENT_MEMORY_CANCEL,
0250     P4_EVENT_MEMORY_COMPLETE,
0251     P4_EVENT_LOAD_PORT_REPLAY,
0252     P4_EVENT_STORE_PORT_REPLAY,
0253     P4_EVENT_MOB_LOAD_REPLAY,
0254     P4_EVENT_PAGE_WALK_TYPE,
0255     P4_EVENT_BSQ_CACHE_REFERENCE,
0256     P4_EVENT_IOQ_ALLOCATION,
0257     P4_EVENT_IOQ_ACTIVE_ENTRIES,
0258     P4_EVENT_FSB_DATA_ACTIVITY,
0259     P4_EVENT_BSQ_ALLOCATION,
0260     P4_EVENT_BSQ_ACTIVE_ENTRIES,
0261     P4_EVENT_SSE_INPUT_ASSIST,
0262     P4_EVENT_PACKED_SP_UOP,
0263     P4_EVENT_PACKED_DP_UOP,
0264     P4_EVENT_SCALAR_SP_UOP,
0265     P4_EVENT_SCALAR_DP_UOP,
0266     P4_EVENT_64BIT_MMX_UOP,
0267     P4_EVENT_128BIT_MMX_UOP,
0268     P4_EVENT_X87_FP_UOP,
0269     P4_EVENT_TC_MISC,
0270     P4_EVENT_GLOBAL_POWER_EVENTS,
0271     P4_EVENT_TC_MS_XFER,
0272     P4_EVENT_UOP_QUEUE_WRITES,
0273     P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE,
0274     P4_EVENT_RETIRED_BRANCH_TYPE,
0275     P4_EVENT_RESOURCE_STALL,
0276     P4_EVENT_WC_BUFFER,
0277     P4_EVENT_B2B_CYCLES,
0278     P4_EVENT_BNR,
0279     P4_EVENT_SNOOP,
0280     P4_EVENT_RESPONSE,
0281     P4_EVENT_FRONT_END_EVENT,
0282     P4_EVENT_EXECUTION_EVENT,
0283     P4_EVENT_REPLAY_EVENT,
0284     P4_EVENT_INSTR_RETIRED,
0285     P4_EVENT_UOPS_RETIRED,
0286     P4_EVENT_UOP_TYPE,
0287     P4_EVENT_BRANCH_RETIRED,
0288     P4_EVENT_MISPRED_BRANCH_RETIRED,
0289     P4_EVENT_X87_ASSIST,
0290     P4_EVENT_MACHINE_CLEAR,
0291     P4_EVENT_INSTR_COMPLETED,
0292 };
0293
0294 #define P4_OPCODE(event)        event##_OPCODE
0295 #define P4_OPCODE_ESEL(opcode)      ((opcode & 0x00ff) >> 0)
0296 #define P4_OPCODE_EVNT(opcode)      ((opcode & 0xff00) >> 8)
0297 #define P4_OPCODE_PACK(event, sel)  (((event) << 8) | sel)
0298
0299 /*
0300  * Comments below the event represent ESCR restriction
0301  * for this event and counter index per ESCR
0302  *
0303  * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early
0304  * processor builds (family 0FH, models 01H-02H). These MSRs
0305  * are not available on later versions, so that we don't use
0306  * them completely
0307  *
0308  * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly
0309  * working so that we should not use this CCCR and respective
0310  * counter as result
0311  */
0312 enum P4_EVENT_OPCODES {
0313     P4_OPCODE(P4_EVENT_TC_DELIVER_MODE)     = P4_OPCODE_PACK(0x01, 0x01),
0314     /*
0315      * MSR_P4_TC_ESCR0: 4, 5
0316      * MSR_P4_TC_ESCR1: 6, 7
0317      */
0318
0319     P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST)       = P4_OPCODE_PACK(0x03, 0x00),
0320     /*
0321      * MSR_P4_BPU_ESCR0:    0, 1
0322      * MSR_P4_BPU_ESCR1:    2, 3
0323      */
0324
0325     P4_OPCODE(P4_EVENT_ITLB_REFERENCE)      = P4_OPCODE_PACK(0x18, 0x03),
0326     /*
0327      * MSR_P4_ITLB_ESCR0:   0, 1
0328      * MSR_P4_ITLB_ESCR1:   2, 3
0329      */
0330
0331     P4_OPCODE(P4_EVENT_MEMORY_CANCEL)       = P4_OPCODE_PACK(0x02, 0x05),
0332     /*
0333      * MSR_P4_DAC_ESCR0:    8, 9
0334      * MSR_P4_DAC_ESCR1:    10, 11
0335      */
0336
0337     P4_OPCODE(P4_EVENT_MEMORY_COMPLETE)     = P4_OPCODE_PACK(0x08, 0x02),
0338     /*
0339      * MSR_P4_SAAT_ESCR0:   8, 9
0340      * MSR_P4_SAAT_ESCR1:   10, 11
0341      */
0342
0343     P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY)        = P4_OPCODE_PACK(0x04, 0x02),
0344     /*
0345      * MSR_P4_SAAT_ESCR0:   8, 9
0346      * MSR_P4_SAAT_ESCR1:   10, 11
0347      */
0348
0349     P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY)       = P4_OPCODE_PACK(0x05, 0x02),
0350     /*
0351      * MSR_P4_SAAT_ESCR0:   8, 9
0352      * MSR_P4_SAAT_ESCR1:   10, 11
0353      */
0354
0355     P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY)     = P4_OPCODE_PACK(0x03, 0x02),
0356     /*
0357      * MSR_P4_MOB_ESCR0:    0, 1
0358      * MSR_P4_MOB_ESCR1:    2, 3
0359      */
0360
0361     P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE)      = P4_OPCODE_PACK(0x01, 0x04),
0362     /*
0363      * MSR_P4_PMH_ESCR0:    0, 1
0364      * MSR_P4_PMH_ESCR1:    2, 3
0365      */
0366
0367     P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE)     = P4_OPCODE_PACK(0x0c, 0x07),
0368     /*
0369      * MSR_P4_BSU_ESCR0:    0, 1
0370      * MSR_P4_BSU_ESCR1:    2, 3
0371      */
0372
0373     P4_OPCODE(P4_EVENT_IOQ_ALLOCATION)      = P4_OPCODE_PACK(0x03, 0x06),
0374     /*
0375      * MSR_P4_FSB_ESCR0:    0, 1
0376      * MSR_P4_FSB_ESCR1:    2, 3
0377      */
0378
0379     P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES)      = P4_OPCODE_PACK(0x1a, 0x06),
0380     /*
0381      * MSR_P4_FSB_ESCR1:    2, 3
0382      */
0383
0384     P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY)       = P4_OPCODE_PACK(0x17, 0x06),
0385     /*
0386      * MSR_P4_FSB_ESCR0:    0, 1
0387      * MSR_P4_FSB_ESCR1:    2, 3
0388      */
0389
0390     P4_OPCODE(P4_EVENT_BSQ_ALLOCATION)      = P4_OPCODE_PACK(0x05, 0x07),
0391     /*
0392      * MSR_P4_BSU_ESCR0:    0, 1
0393      */
0394
0395     P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES)      = P4_OPCODE_PACK(0x06, 0x07),
0396     /*
0397      * NOTE: no ESCR name in docs, it's guessed
0398      * MSR_P4_BSU_ESCR1:    2, 3
0399      */
0400
0401     P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST)        = P4_OPCODE_PACK(0x34, 0x01),
0402     /*
0403      * MSR_P4_FIRM_ESCR0:   8, 9
0404      * MSR_P4_FIRM_ESCR1:   10, 11
0405      */
0406
0407     P4_OPCODE(P4_EVENT_PACKED_SP_UOP)       = P4_OPCODE_PACK(0x08, 0x01),
0408     /*
0409      * MSR_P4_FIRM_ESCR0:   8, 9
0410      * MSR_P4_FIRM_ESCR1:   10, 11
0411      */
0412
0413     P4_OPCODE(P4_EVENT_PACKED_DP_UOP)       = P4_OPCODE_PACK(0x0c, 0x01),
0414     /*
0415      * MSR_P4_FIRM_ESCR0:   8, 9
0416      * MSR_P4_FIRM_ESCR1:   10, 11
0417      */
0418
0419     P4_OPCODE(P4_EVENT_SCALAR_SP_UOP)       = P4_OPCODE_PACK(0x0a, 0x01),
0420     /*
0421      * MSR_P4_FIRM_ESCR0:   8, 9
0422      * MSR_P4_FIRM_ESCR1:   10, 11
0423      */
0424
0425     P4_OPCODE(P4_EVENT_SCALAR_DP_UOP)       = P4_OPCODE_PACK(0x0e, 0x01),
0426     /*
0427      * MSR_P4_FIRM_ESCR0:   8, 9
0428      * MSR_P4_FIRM_ESCR1:   10, 11
0429      */
0430
0431     P4_OPCODE(P4_EVENT_64BIT_MMX_UOP)       = P4_OPCODE_PACK(0x02, 0x01),
0432     /*
0433      * MSR_P4_FIRM_ESCR0:   8, 9
0434      * MSR_P4_FIRM_ESCR1:   10, 11
0435      */
0436
0437     P4_OPCODE(P4_EVENT_128BIT_MMX_UOP)      = P4_OPCODE_PACK(0x1a, 0x01),
0438     /*
0439      * MSR_P4_FIRM_ESCR0:   8, 9
0440      * MSR_P4_FIRM_ESCR1:   10, 11
0441      */
0442
0443     P4_OPCODE(P4_EVENT_X87_FP_UOP)          = P4_OPCODE_PACK(0x04, 0x01),
0444     /*
0445      * MSR_P4_FIRM_ESCR0:   8, 9
0446      * MSR_P4_FIRM_ESCR1:   10, 11
0447      */
0448
0449     P4_OPCODE(P4_EVENT_TC_MISC)         = P4_OPCODE_PACK(0x06, 0x01),
0450     /*
0451      * MSR_P4_TC_ESCR0: 4, 5
0452      * MSR_P4_TC_ESCR1: 6, 7
0453      */
0454
0455     P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS)     = P4_OPCODE_PACK(0x13, 0x06),
0456     /*
0457      * MSR_P4_FSB_ESCR0:    0, 1
0458      * MSR_P4_FSB_ESCR1:    2, 3
0459      */
0460
0461     P4_OPCODE(P4_EVENT_TC_MS_XFER)          = P4_OPCODE_PACK(0x05, 0x00),
0462     /*
0463      * MSR_P4_MS_ESCR0: 4, 5
0464      * MSR_P4_MS_ESCR1: 6, 7
0465      */
0466
0467     P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES)        = P4_OPCODE_PACK(0x09, 0x00),
0468     /*
0469      * MSR_P4_MS_ESCR0: 4, 5
0470      * MSR_P4_MS_ESCR1: 6, 7
0471      */
0472
0473     P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02),
0474     /*
0475      * MSR_P4_TBPU_ESCR0:   4, 5
0476      * MSR_P4_TBPU_ESCR1:   6, 7
0477      */
0478
0479     P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE)     = P4_OPCODE_PACK(0x04, 0x02),
0480     /*
0481      * MSR_P4_TBPU_ESCR0:   4, 5
0482      * MSR_P4_TBPU_ESCR1:   6, 7
0483      */
0484
0485     P4_OPCODE(P4_EVENT_RESOURCE_STALL)      = P4_OPCODE_PACK(0x01, 0x01),
0486     /*
0487      * MSR_P4_ALF_ESCR0:    12, 13, 16
0488      * MSR_P4_ALF_ESCR1:    14, 15, 17
0489      */
0490
0491     P4_OPCODE(P4_EVENT_WC_BUFFER)           = P4_OPCODE_PACK(0x05, 0x05),
0492     /*
0493      * MSR_P4_DAC_ESCR0:    8, 9
0494      * MSR_P4_DAC_ESCR1:    10, 11
0495      */
0496
0497     P4_OPCODE(P4_EVENT_B2B_CYCLES)          = P4_OPCODE_PACK(0x16, 0x03),
0498     /*
0499      * MSR_P4_FSB_ESCR0:    0, 1
0500      * MSR_P4_FSB_ESCR1:    2, 3
0501      */
0502
0503     P4_OPCODE(P4_EVENT_BNR)             = P4_OPCODE_PACK(0x08, 0x03),
0504     /*
0505      * MSR_P4_FSB_ESCR0:    0, 1
0506      * MSR_P4_FSB_ESCR1:    2, 3
0507      */
0508
0509     P4_OPCODE(P4_EVENT_SNOOP)           = P4_OPCODE_PACK(0x06, 0x03),
0510     /*
0511      * MSR_P4_FSB_ESCR0:    0, 1
0512      * MSR_P4_FSB_ESCR1:    2, 3
0513      */
0514
0515     P4_OPCODE(P4_EVENT_RESPONSE)            = P4_OPCODE_PACK(0x04, 0x03),
0516     /*
0517      * MSR_P4_FSB_ESCR0:    0, 1
0518      * MSR_P4_FSB_ESCR1:    2, 3
0519      */
0520
0521     P4_OPCODE(P4_EVENT_FRONT_END_EVENT)     = P4_OPCODE_PACK(0x08, 0x05),
0522     /*
0523      * MSR_P4_CRU_ESCR2:    12, 13, 16
0524      * MSR_P4_CRU_ESCR3:    14, 15, 17
0525      */
0526
0527     P4_OPCODE(P4_EVENT_EXECUTION_EVENT)     = P4_OPCODE_PACK(0x0c, 0x05),
0528     /*
0529      * MSR_P4_CRU_ESCR2:    12, 13, 16
0530      * MSR_P4_CRU_ESCR3:    14, 15, 17
0531      */
0532
0533     P4_OPCODE(P4_EVENT_REPLAY_EVENT)        = P4_OPCODE_PACK(0x09, 0x05),
0534     /*
0535      * MSR_P4_CRU_ESCR2:    12, 13, 16
0536      * MSR_P4_CRU_ESCR3:    14, 15, 17
0537      */
0538
0539     P4_OPCODE(P4_EVENT_INSTR_RETIRED)       = P4_OPCODE_PACK(0x02, 0x04),
0540     /*
0541      * MSR_P4_CRU_ESCR0:    12, 13, 16
0542      * MSR_P4_CRU_ESCR1:    14, 15, 17
0543      */
0544
0545     P4_OPCODE(P4_EVENT_UOPS_RETIRED)        = P4_OPCODE_PACK(0x01, 0x04),
0546     /*
0547      * MSR_P4_CRU_ESCR0:    12, 13, 16
0548      * MSR_P4_CRU_ESCR1:    14, 15, 17
0549      */
0550
0551     P4_OPCODE(P4_EVENT_UOP_TYPE)            = P4_OPCODE_PACK(0x02, 0x02),
0552     /*
0553      * MSR_P4_RAT_ESCR0:    12, 13, 16
0554      * MSR_P4_RAT_ESCR1:    14, 15, 17
0555      */
0556
0557     P4_OPCODE(P4_EVENT_BRANCH_RETIRED)      = P4_OPCODE_PACK(0x06, 0x05),
0558     /*
0559      * MSR_P4_CRU_ESCR2:    12, 13, 16
0560      * MSR_P4_CRU_ESCR3:    14, 15, 17
0561      */
0562
0563     P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED)  = P4_OPCODE_PACK(0x03, 0x04),
0564     /*
0565      * MSR_P4_CRU_ESCR0:    12, 13, 16
0566      * MSR_P4_CRU_ESCR1:    14, 15, 17
0567      */
0568
0569     P4_OPCODE(P4_EVENT_X87_ASSIST)          = P4_OPCODE_PACK(0x03, 0x05),
0570     /*
0571      * MSR_P4_CRU_ESCR2:    12, 13, 16
0572      * MSR_P4_CRU_ESCR3:    14, 15, 17
0573      */
0574
0575     P4_OPCODE(P4_EVENT_MACHINE_CLEAR)       = P4_OPCODE_PACK(0x02, 0x05),
0576     /*
0577      * MSR_P4_CRU_ESCR2:    12, 13, 16
0578      * MSR_P4_CRU_ESCR3:    14, 15, 17
0579      */
0580
0581     P4_OPCODE(P4_EVENT_INSTR_COMPLETED)     = P4_OPCODE_PACK(0x07, 0x04),
0582     /*
0583      * MSR_P4_CRU_ESCR0:    12, 13, 16
0584      * MSR_P4_CRU_ESCR1:    14, 15, 17
0585      */
0586 };
0587
0588 /*
0589  * a caller should use P4_ESCR_EMASK_NAME helper to
0590  * pick the EventMask needed, for example
0591  *
0592  *  P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD)
0593  */
0594 enum P4_ESCR_EMASKS {
0595     P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0),
0596     P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1),
0597     P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2),
0598     P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3),
0599     P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4),
0600     P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5),
0601     P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6),
0602
0603     P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0),
0604
0605     P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0),
0606     P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1),
0607     P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2),
0608
0609     P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2),
0610     P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3),
0611
0612     P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0),
0613     P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1),
0614
0615     P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1),
0616
0617     P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1),
0618
0619     P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1),
0620     P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3),
0621     P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4),
0622     P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5),
0623
0624     P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0),
0625     P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1),
0626
0627     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0),
0628     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1),
0629     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2),
0630     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3),
0631     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4),
0632     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5),
0633     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8),
0634     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9),
0635     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10),
0636
0637     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0),
0638     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5),
0639     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6),
0640     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7),
0641     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8),
0642     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9),
0643     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10),
0644     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11),
0645     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13),
0646     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14),
0647     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15),
0648
0649     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0),
0650     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5),
0651     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6),
0652     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7),
0653     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8),
0654     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9),
0655     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10),
0656     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11),
0657     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13),
0658     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14),
0659     P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15),
0660
0661     P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0),
0662     P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1),
0663     P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2),
0664     P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3),
0665     P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4),
0666     P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5),
0667
0668     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0),
0669     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1),
0670     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2),
0671     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3),
0672     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5),
0673     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6),
0674     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7),
0675     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8),
0676     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9),
0677     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10),
0678     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11),
0679     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12),
0680     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13),
0681
0682     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0),
0683     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1),
0684     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2),
0685     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3),
0686     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5),
0687     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6),
0688     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7),
0689     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8),
0690     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9),
0691     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10),
0692     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11),
0693     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12),
0694     P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13),
0695
0696     P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15),
0697
0698     P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15),
0699
0700     P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15),
0701
0702     P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15),
0703
0704     P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15),
0705
0706     P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15),
0707
0708     P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15),
0709
0710     P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15),
0711
0712     P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4),
0713
0714     P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0),
0715
0716     P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0),
0717
0718     P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0),
0719     P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1),
0720     P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2),
0721
0722     P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1),
0723     P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2),
0724     P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3),
0725     P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4),
0726
0727     P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1),
0728     P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2),
0729     P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3),
0730     P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4),
0731
0732     P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5),
0733
0734     P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0),
0735     P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1),
0736
0737     P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0),
0738     P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1),
0739
0740     P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0),
0741     P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1),
0742     P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2),
0743     P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3),
0744     P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4),
0745     P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5),
0746     P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6),
0747     P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7),
0748
0749     P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0),
0750     P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1),
0751
0752     P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0),
0753     P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1),
0754     P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2),
0755     P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3),
0756
0757     P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0),
0758     P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1),
0759
0760     P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1),
0761     P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2),
0762
0763     P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0),
0764     P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1),
0765     P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2),
0766     P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3),
0767
0768     P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0),
0769
0770     P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0),
0771     P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1),
0772     P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2),
0773     P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3),
0774     P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4),
0775
0776     P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0),
0777     P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1),
0778     P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2),
0779
0780     P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0),
0781     P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1),
0782 };
0783
0784 /*
0785  * Note we have UOP and PEBS bits reserved for now
0786  * just in case if we will need them once
0787  */
0788 #define P4_PEBS_CONFIG_ENABLE       (1ULL << 7)
0789 #define P4_PEBS_CONFIG_UOP_TAG      (1ULL << 8)
0790 #define P4_PEBS_CONFIG_METRIC_MASK  0x3FLL
0791 #define P4_PEBS_CONFIG_MASK     0xFFLL
0792
0793 /*
0794  * mem: Only counters MSR_IQ_COUNTER4 (16) and
0795  * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling
0796  */
0797 #define P4_PEBS_ENABLE          0x02000000ULL
0798 #define P4_PEBS_ENABLE_UOP_TAG      0x01000000ULL
0799
0800 #define p4_config_unpack_metric(v)  (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)
0801 #define p4_config_unpack_pebs(v)    (((u64)(v)) & P4_PEBS_CONFIG_MASK)
0802
0803 #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask))
0804
0805 enum P4_PEBS_METRIC {
0806     P4_PEBS_METRIC__none,
0807
0808     P4_PEBS_METRIC__1stl_cache_load_miss_retired,
0809     P4_PEBS_METRIC__2ndl_cache_load_miss_retired,
0810     P4_PEBS_METRIC__dtlb_load_miss_retired,
0811     P4_PEBS_METRIC__dtlb_store_miss_retired,
0812     P4_PEBS_METRIC__dtlb_all_miss_retired,
0813     P4_PEBS_METRIC__tagged_mispred_branch,
0814     P4_PEBS_METRIC__mob_load_replay_retired,
0815     P4_PEBS_METRIC__split_load_retired,
0816     P4_PEBS_METRIC__split_store_retired,
0817
0818     P4_PEBS_METRIC__max
0819 };
0820
0821 /*
0822  * Notes on internal configuration of ESCR+CCCR tuples
0823  *
0824  * Since P4 has quite the different architecture of
0825  * performance registers in compare with "architectural"
0826  * once and we have on 64 bits to keep configuration
0827  * of performance event, the following trick is used.
0828  *
0829  * 1) Since both ESCR and CCCR registers have only low
0830  *    32 bits valuable, we pack them into a single 64 bit
0831  *    configuration. Low 32 bits of such config correspond
0832  *    to low 32 bits of CCCR register and high 32 bits
0833  *    correspond to low 32 bits of ESCR register.
0834  *
0835  * 2) The meaning of every bit of such config field can
0836  *    be found in Intel SDM but it should be noted that
0837  *    we "borrow" some reserved bits for own usage and
0838  *    clean them or set to a proper value when we do
0839  *    a real write to hardware registers.
0840  *
0841  * 3) The format of bits of config is the following
0842  *    and should be either 0 or set to some predefined
0843  *    values:
0844  *
0845  *    Low 32 bits
0846  *    -----------
0847  *      0-6: P4_PEBS_METRIC enum
0848  *     7-11:                    reserved
0849  *       12:                    reserved (Enable)
0850  *    13-15:                    reserved (ESCR select)
0851  *    16-17: Active Thread
0852  *       18: Compare
0853  *       19: Complement
0854  *    20-23: Threshold
0855  *       24: Edge
0856  *       25:                    reserved (FORCE_OVF)
0857  *       26:                    reserved (OVF_PMI_T0)
0858  *       27:                    reserved (OVF_PMI_T1)
0859  *    28-29:                    reserved
0860  *       30:                    reserved (Cascade)
0861  *       31:                    reserved (OVF)
0862  *
0863  *    High 32 bits
0864  *    ------------
0865  *        0:                    reserved (T1_USR)
0866  *        1:                    reserved (T1_OS)
0867  *        2:                    reserved (T0_USR)
0868  *        3:                    reserved (T0_OS)
0869  *        4: Tag Enable
0870  *      5-8: Tag Value
0871  *     9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
0872  *    25-30: enum P4_EVENTS
0873  *       31:                    reserved (HT thread)
0874  */
0875
0876 #endif /* PERF_EVENT_P4_H */
0877