include/asm/perf_event.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_PERF_EVENT_H
0003 #define _ASM_X86_PERF_EVENT_H
0004
0005 #include <linux/static_call.h>
0006
0007 /*
0008  * Performance event hw details:
0009  */
0010
0011 #define INTEL_PMC_MAX_GENERIC                      32
0012 #define INTEL_PMC_MAX_FIXED                    16
0013 #define INTEL_PMC_IDX_FIXED                    32
0014
0015 #define X86_PMC_IDX_MAX                        64
0016
0017 #define MSR_ARCH_PERFMON_PERFCTR0                 0xc1
0018 #define MSR_ARCH_PERFMON_PERFCTR1                 0xc2
0019
0020 #define MSR_ARCH_PERFMON_EVENTSEL0               0x186
0021 #define MSR_ARCH_PERFMON_EVENTSEL1               0x187
0022
0023 #define ARCH_PERFMON_EVENTSEL_EVENT         0x000000FFULL
0024 #define ARCH_PERFMON_EVENTSEL_UMASK         0x0000FF00ULL
0025 #define ARCH_PERFMON_EVENTSEL_USR           (1ULL << 16)
0026 #define ARCH_PERFMON_EVENTSEL_OS            (1ULL << 17)
0027 #define ARCH_PERFMON_EVENTSEL_EDGE          (1ULL << 18)
0028 #define ARCH_PERFMON_EVENTSEL_PIN_CONTROL       (1ULL << 19)
0029 #define ARCH_PERFMON_EVENTSEL_INT           (1ULL << 20)
0030 #define ARCH_PERFMON_EVENTSEL_ANY           (1ULL << 21)
0031 #define ARCH_PERFMON_EVENTSEL_ENABLE            (1ULL << 22)
0032 #define ARCH_PERFMON_EVENTSEL_INV           (1ULL << 23)
0033 #define ARCH_PERFMON_EVENTSEL_CMASK         0xFF000000ULL
0034
0035 #define HSW_IN_TX                   (1ULL << 32)
0036 #define HSW_IN_TX_CHECKPOINTED              (1ULL << 33)
0037 #define ICL_EVENTSEL_ADAPTIVE               (1ULL << 34)
0038 #define ICL_FIXED_0_ADAPTIVE                (1ULL << 32)
0039
0040 #define AMD64_EVENTSEL_INT_CORE_ENABLE          (1ULL << 36)
0041 #define AMD64_EVENTSEL_GUESTONLY            (1ULL << 40)
0042 #define AMD64_EVENTSEL_HOSTONLY             (1ULL << 41)
0043
0044 #define AMD64_EVENTSEL_INT_CORE_SEL_SHIFT       37
0045 #define AMD64_EVENTSEL_INT_CORE_SEL_MASK        \
0046     (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
0047
0048 #define AMD64_EVENTSEL_EVENT    \
0049     (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
0050 #define INTEL_ARCH_EVENT_MASK   \
0051     (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
0052
0053 #define AMD64_L3_SLICE_SHIFT                48
0054 #define AMD64_L3_SLICE_MASK             \
0055     (0xFULL << AMD64_L3_SLICE_SHIFT)
0056 #define AMD64_L3_SLICEID_MASK               \
0057     (0x7ULL << AMD64_L3_SLICE_SHIFT)
0058
0059 #define AMD64_L3_THREAD_SHIFT               56
0060 #define AMD64_L3_THREAD_MASK                \
0061     (0xFFULL << AMD64_L3_THREAD_SHIFT)
0062 #define AMD64_L3_F19H_THREAD_MASK           \
0063     (0x3ULL << AMD64_L3_THREAD_SHIFT)
0064
0065 #define AMD64_L3_EN_ALL_CORES               BIT_ULL(47)
0066 #define AMD64_L3_EN_ALL_SLICES              BIT_ULL(46)
0067
0068 #define AMD64_L3_COREID_SHIFT               42
0069 #define AMD64_L3_COREID_MASK                \
0070     (0x7ULL << AMD64_L3_COREID_SHIFT)
0071
0072 #define X86_RAW_EVENT_MASK      \
0073     (ARCH_PERFMON_EVENTSEL_EVENT |  \
0074      ARCH_PERFMON_EVENTSEL_UMASK |  \
0075      ARCH_PERFMON_EVENTSEL_EDGE  |  \
0076      ARCH_PERFMON_EVENTSEL_INV   |  \
0077      ARCH_PERFMON_EVENTSEL_CMASK)
0078 #define X86_ALL_EVENT_FLAGS             \
0079     (ARCH_PERFMON_EVENTSEL_EDGE |       \
0080      ARCH_PERFMON_EVENTSEL_INV |        \
0081      ARCH_PERFMON_EVENTSEL_CMASK |      \
0082      ARCH_PERFMON_EVENTSEL_ANY |        \
0083      ARCH_PERFMON_EVENTSEL_PIN_CONTROL |    \
0084      HSW_IN_TX |                \
0085      HSW_IN_TX_CHECKPOINTED)
0086 #define AMD64_RAW_EVENT_MASK        \
0087     (X86_RAW_EVENT_MASK          |  \
0088      AMD64_EVENTSEL_EVENT)
0089 #define AMD64_RAW_EVENT_MASK_NB     \
0090     (AMD64_EVENTSEL_EVENT        |  \
0091      ARCH_PERFMON_EVENTSEL_UMASK)
0092
0093 #define AMD64_PERFMON_V2_EVENTSEL_EVENT_NB  \
0094     (AMD64_EVENTSEL_EVENT   |       \
0095      GENMASK_ULL(37, 36))
0096
0097 #define AMD64_PERFMON_V2_EVENTSEL_UMASK_NB  \
0098     (ARCH_PERFMON_EVENTSEL_UMASK    |   \
0099      GENMASK_ULL(27, 24))
0100
0101 #define AMD64_PERFMON_V2_RAW_EVENT_MASK_NB      \
0102     (AMD64_PERFMON_V2_EVENTSEL_EVENT_NB |   \
0103      AMD64_PERFMON_V2_EVENTSEL_UMASK_NB)
0104
0105 #define AMD64_NUM_COUNTERS              4
0106 #define AMD64_NUM_COUNTERS_CORE             6
0107 #define AMD64_NUM_COUNTERS_NB               4
0108
0109 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL       0x3c
0110 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK     (0x00 << 8)
0111 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX     0
0112 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
0113         (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
0114
0115 #define ARCH_PERFMON_BRANCH_MISSES_RETIRED      6
0116 #define ARCH_PERFMON_EVENTS_COUNT           7
0117
0118 #define PEBS_DATACFG_MEMINFO    BIT_ULL(0)
0119 #define PEBS_DATACFG_GP BIT_ULL(1)
0120 #define PEBS_DATACFG_XMMS   BIT_ULL(2)
0121 #define PEBS_DATACFG_LBRS   BIT_ULL(3)
0122 #define PEBS_DATACFG_LBR_SHIFT  24
0123
0124 /*
0125  * Intel "Architectural Performance Monitoring" CPUID
0126  * detection/enumeration details:
0127  */
0128 union cpuid10_eax {
0129     struct {
0130         unsigned int version_id:8;
0131         unsigned int num_counters:8;
0132         unsigned int bit_width:8;
0133         unsigned int mask_length:8;
0134     } split;
0135     unsigned int full;
0136 };
0137
0138 union cpuid10_ebx {
0139     struct {
0140         unsigned int no_unhalted_core_cycles:1;
0141         unsigned int no_instructions_retired:1;
0142         unsigned int no_unhalted_reference_cycles:1;
0143         unsigned int no_llc_reference:1;
0144         unsigned int no_llc_misses:1;
0145         unsigned int no_branch_instruction_retired:1;
0146         unsigned int no_branch_misses_retired:1;
0147     } split;
0148     unsigned int full;
0149 };
0150
0151 union cpuid10_edx {
0152     struct {
0153         unsigned int num_counters_fixed:5;
0154         unsigned int bit_width_fixed:8;
0155         unsigned int reserved1:2;
0156         unsigned int anythread_deprecated:1;
0157         unsigned int reserved2:16;
0158     } split;
0159     unsigned int full;
0160 };
0161
0162 /*
0163  * Intel Architectural LBR CPUID detection/enumeration details:
0164  */
0165 union cpuid28_eax {
0166     struct {
0167         /* Supported LBR depth values */
0168         unsigned int    lbr_depth_mask:8;
0169         unsigned int    reserved:22;
0170         /* Deep C-state Reset */
0171         unsigned int    lbr_deep_c_reset:1;
0172         /* IP values contain LIP */
0173         unsigned int    lbr_lip:1;
0174     } split;
0175     unsigned int        full;
0176 };
0177
0178 union cpuid28_ebx {
0179     struct {
0180         /* CPL Filtering Supported */
0181         unsigned int    lbr_cpl:1;
0182         /* Branch Filtering Supported */
0183         unsigned int    lbr_filter:1;
0184         /* Call-stack Mode Supported */
0185         unsigned int    lbr_call_stack:1;
0186     } split;
0187     unsigned int            full;
0188 };
0189
0190 union cpuid28_ecx {
0191     struct {
0192         /* Mispredict Bit Supported */
0193         unsigned int    lbr_mispred:1;
0194         /* Timed LBRs Supported */
0195         unsigned int    lbr_timed_lbr:1;
0196         /* Branch Type Field Supported */
0197         unsigned int    lbr_br_type:1;
0198     } split;
0199     unsigned int            full;
0200 };
0201
0202 /*
0203  * AMD "Extended Performance Monitoring and Debug" CPUID
0204  * detection/enumeration details:
0205  */
0206 union cpuid_0x80000022_ebx {
0207     struct {
0208         /* Number of Core Performance Counters */
0209         unsigned int    num_core_pmc:4;
0210         unsigned int    reserved:6;
0211         /* Number of Data Fabric Counters */
0212         unsigned int    num_df_pmc:6;
0213     } split;
0214     unsigned int        full;
0215 };
0216
0217 struct x86_pmu_capability {
0218     int     version;
0219     int     num_counters_gp;
0220     int     num_counters_fixed;
0221     int     bit_width_gp;
0222     int     bit_width_fixed;
0223     unsigned int    events_mask;
0224     int     events_mask_len;
0225     unsigned int    pebs_ept    :1;
0226 };
0227
0228 /*
0229  * Fixed-purpose performance events:
0230  */
0231
0232 /* RDPMC offset for Fixed PMCs */
0233 #define INTEL_PMC_FIXED_RDPMC_BASE      (1 << 30)
0234 #define INTEL_PMC_FIXED_RDPMC_METRICS       (1 << 29)
0235
0236 /*
0237  * All the fixed-mode PMCs are configured via this single MSR:
0238  */
0239 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL 0x38d
0240
0241 /*
0242  * There is no event-code assigned to the fixed-mode PMCs.
0243  *
0244  * For a fixed-mode PMC, which has an equivalent event on a general-purpose
0245  * PMC, the event-code of the equivalent event is used for the fixed-mode PMC,
0246  * e.g., Instr_Retired.Any and CPU_CLK_Unhalted.Core.
0247  *
0248  * For a fixed-mode PMC, which doesn't have an equivalent event, a
0249  * pseudo-encoding is used, e.g., CPU_CLK_Unhalted.Ref and TOPDOWN.SLOTS.
0250  * The pseudo event-code for a fixed-mode PMC must be 0x00.
0251  * The pseudo umask-code is 0xX. The X equals the index of the fixed
0252  * counter + 1, e.g., the fixed counter 2 has the pseudo-encoding 0x0300.
0253  *
0254  * The counts are available in separate MSRs:
0255  */
0256
0257 /* Instr_Retired.Any: */
0258 #define MSR_ARCH_PERFMON_FIXED_CTR0 0x309
0259 #define INTEL_PMC_IDX_FIXED_INSTRUCTIONS    (INTEL_PMC_IDX_FIXED + 0)
0260
0261 /* CPU_CLK_Unhalted.Core: */
0262 #define MSR_ARCH_PERFMON_FIXED_CTR1 0x30a
0263 #define INTEL_PMC_IDX_FIXED_CPU_CYCLES  (INTEL_PMC_IDX_FIXED + 1)
0264
0265 /* CPU_CLK_Unhalted.Ref: event=0x00,umask=0x3 (pseudo-encoding) */
0266 #define MSR_ARCH_PERFMON_FIXED_CTR2 0x30b
0267 #define INTEL_PMC_IDX_FIXED_REF_CYCLES  (INTEL_PMC_IDX_FIXED + 2)
0268 #define INTEL_PMC_MSK_FIXED_REF_CYCLES  (1ULL << INTEL_PMC_IDX_FIXED_REF_CYCLES)
0269
0270 /* TOPDOWN.SLOTS: event=0x00,umask=0x4 (pseudo-encoding) */
0271 #define MSR_ARCH_PERFMON_FIXED_CTR3 0x30c
0272 #define INTEL_PMC_IDX_FIXED_SLOTS   (INTEL_PMC_IDX_FIXED + 3)
0273 #define INTEL_PMC_MSK_FIXED_SLOTS   (1ULL << INTEL_PMC_IDX_FIXED_SLOTS)
0274
0275 static inline bool use_fixed_pseudo_encoding(u64 code)
0276 {
0277     return !(code & 0xff);
0278 }
0279
0280 /*
0281  * We model BTS tracing as another fixed-mode PMC.
0282  *
0283  * We choose the value 47 for the fixed index of BTS, since lower
0284  * values are used by actual fixed events and higher values are used
0285  * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
0286  */
0287 #define INTEL_PMC_IDX_FIXED_BTS         (INTEL_PMC_IDX_FIXED + 15)
0288
0289 /*
0290  * The PERF_METRICS MSR is modeled as several magic fixed-mode PMCs, one for
0291  * each TopDown metric event.
0292  *
0293  * Internally the TopDown metric events are mapped to the FxCtr 3 (SLOTS).
0294  */
0295 #define INTEL_PMC_IDX_METRIC_BASE       (INTEL_PMC_IDX_FIXED + 16)
0296 #define INTEL_PMC_IDX_TD_RETIRING       (INTEL_PMC_IDX_METRIC_BASE + 0)
0297 #define INTEL_PMC_IDX_TD_BAD_SPEC       (INTEL_PMC_IDX_METRIC_BASE + 1)
0298 #define INTEL_PMC_IDX_TD_FE_BOUND       (INTEL_PMC_IDX_METRIC_BASE + 2)
0299 #define INTEL_PMC_IDX_TD_BE_BOUND       (INTEL_PMC_IDX_METRIC_BASE + 3)
0300 #define INTEL_PMC_IDX_TD_HEAVY_OPS      (INTEL_PMC_IDX_METRIC_BASE + 4)
0301 #define INTEL_PMC_IDX_TD_BR_MISPREDICT      (INTEL_PMC_IDX_METRIC_BASE + 5)
0302 #define INTEL_PMC_IDX_TD_FETCH_LAT      (INTEL_PMC_IDX_METRIC_BASE + 6)
0303 #define INTEL_PMC_IDX_TD_MEM_BOUND      (INTEL_PMC_IDX_METRIC_BASE + 7)
0304 #define INTEL_PMC_IDX_METRIC_END        INTEL_PMC_IDX_TD_MEM_BOUND
0305 #define INTEL_PMC_MSK_TOPDOWN           ((0xffull << INTEL_PMC_IDX_METRIC_BASE) | \
0306                         INTEL_PMC_MSK_FIXED_SLOTS)
0307
0308 /*
0309  * There is no event-code assigned to the TopDown events.
0310  *
0311  * For the slots event, use the pseudo code of the fixed counter 3.
0312  *
0313  * For the metric events, the pseudo event-code is 0x00.
0314  * The pseudo umask-code starts from the middle of the pseudo event
0315  * space, 0x80.
0316  */
0317 #define INTEL_TD_SLOTS              0x0400  /* TOPDOWN.SLOTS */
0318 /* Level 1 metrics */
0319 #define INTEL_TD_METRIC_RETIRING        0x8000  /* Retiring metric */
0320 #define INTEL_TD_METRIC_BAD_SPEC        0x8100  /* Bad speculation metric */
0321 #define INTEL_TD_METRIC_FE_BOUND        0x8200  /* FE bound metric */
0322 #define INTEL_TD_METRIC_BE_BOUND        0x8300  /* BE bound metric */
0323 /* Level 2 metrics */
0324 #define INTEL_TD_METRIC_HEAVY_OPS       0x8400  /* Heavy Operations metric */
0325 #define INTEL_TD_METRIC_BR_MISPREDICT       0x8500  /* Branch Mispredict metric */
0326 #define INTEL_TD_METRIC_FETCH_LAT       0x8600  /* Fetch Latency metric */
0327 #define INTEL_TD_METRIC_MEM_BOUND       0x8700  /* Memory bound metric */
0328
0329 #define INTEL_TD_METRIC_MAX         INTEL_TD_METRIC_MEM_BOUND
0330 #define INTEL_TD_METRIC_NUM         8
0331
0332 static inline bool is_metric_idx(int idx)
0333 {
0334     return (unsigned)(idx - INTEL_PMC_IDX_METRIC_BASE) < INTEL_TD_METRIC_NUM;
0335 }
0336
0337 static inline bool is_topdown_idx(int idx)
0338 {
0339     return is_metric_idx(idx) || idx == INTEL_PMC_IDX_FIXED_SLOTS;
0340 }
0341
0342 #define INTEL_PMC_OTHER_TOPDOWN_BITS(bit)   \
0343             (~(0x1ull << bit) & INTEL_PMC_MSK_TOPDOWN)
0344
0345 #define GLOBAL_STATUS_COND_CHG          BIT_ULL(63)
0346 #define GLOBAL_STATUS_BUFFER_OVF_BIT        62
0347 #define GLOBAL_STATUS_BUFFER_OVF        BIT_ULL(GLOBAL_STATUS_BUFFER_OVF_BIT)
0348 #define GLOBAL_STATUS_UNC_OVF           BIT_ULL(61)
0349 #define GLOBAL_STATUS_ASIF          BIT_ULL(60)
0350 #define GLOBAL_STATUS_COUNTERS_FROZEN       BIT_ULL(59)
0351 #define GLOBAL_STATUS_LBRS_FROZEN_BIT       58
0352 #define GLOBAL_STATUS_LBRS_FROZEN       BIT_ULL(GLOBAL_STATUS_LBRS_FROZEN_BIT)
0353 #define GLOBAL_STATUS_TRACE_TOPAPMI_BIT     55
0354 #define GLOBAL_STATUS_TRACE_TOPAPMI     BIT_ULL(GLOBAL_STATUS_TRACE_TOPAPMI_BIT)
0355 #define GLOBAL_STATUS_PERF_METRICS_OVF_BIT  48
0356
0357 #define GLOBAL_CTRL_EN_PERF_METRICS     48
0358 /*
0359  * We model guest LBR event tracing as another fixed-mode PMC like BTS.
0360  *
0361  * We choose bit 58 because it's used to indicate LBR stack frozen state
0362  * for architectural perfmon v4, also we unconditionally mask that bit in
0363  * the handle_pmi_common(), so it'll never be set in the overflow handling.
0364  *
0365  * With this fake counter assigned, the guest LBR event user (such as KVM),
0366  * can program the LBR registers on its own, and we don't actually do anything
0367  * with then in the host context.
0368  */
0369 #define INTEL_PMC_IDX_FIXED_VLBR    (GLOBAL_STATUS_LBRS_FROZEN_BIT)
0370
0371 /*
0372  * Pseudo-encoding the guest LBR event as event=0x00,umask=0x1b,
0373  * since it would claim bit 58 which is effectively Fixed26.
0374  */
0375 #define INTEL_FIXED_VLBR_EVENT  0x1b00
0376
0377 /*
0378  * Adaptive PEBS v4
0379  */
0380
0381 struct pebs_basic {
0382     u64 format_size;
0383     u64 ip;
0384     u64 applicable_counters;
0385     u64 tsc;
0386 };
0387
0388 struct pebs_meminfo {
0389     u64 address;
0390     u64 aux;
0391     u64 latency;
0392     u64 tsx_tuning;
0393 };
0394
0395 struct pebs_gprs {
0396     u64 flags, ip, ax, cx, dx, bx, sp, bp, si, di;
0397     u64 r8, r9, r10, r11, r12, r13, r14, r15;
0398 };
0399
0400 struct pebs_xmm {
0401     u64 xmm[16*2];  /* two entries for each register */
0402 };
0403
0404 /*
0405  * AMD Extended Performance Monitoring and Debug cpuid feature detection
0406  */
0407 #define EXT_PERFMON_DEBUG_FEATURES      0x80000022
0408
0409 /*
0410  * IBS cpuid feature detection
0411  */
0412
0413 #define IBS_CPUID_FEATURES      0x8000001b
0414
0415 /*
0416  * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but
0417  * bit 0 is used to indicate the existence of IBS.
0418  */
0419 #define IBS_CAPS_AVAIL          (1U<<0)
0420 #define IBS_CAPS_FETCHSAM       (1U<<1)
0421 #define IBS_CAPS_OPSAM          (1U<<2)
0422 #define IBS_CAPS_RDWROPCNT      (1U<<3)
0423 #define IBS_CAPS_OPCNT          (1U<<4)
0424 #define IBS_CAPS_BRNTRGT        (1U<<5)
0425 #define IBS_CAPS_OPCNTEXT       (1U<<6)
0426 #define IBS_CAPS_RIPINVALIDCHK      (1U<<7)
0427 #define IBS_CAPS_OPBRNFUSE      (1U<<8)
0428 #define IBS_CAPS_FETCHCTLEXTD       (1U<<9)
0429 #define IBS_CAPS_OPDATA4        (1U<<10)
0430 #define IBS_CAPS_ZEN4           (1U<<11)
0431
0432 #define IBS_CAPS_DEFAULT        (IBS_CAPS_AVAIL     \
0433                      | IBS_CAPS_FETCHSAM    \
0434                      | IBS_CAPS_OPSAM)
0435
0436 /*
0437  * IBS APIC setup
0438  */
0439 #define IBSCTL              0x1cc
0440 #define IBSCTL_LVT_OFFSET_VALID     (1ULL<<8)
0441 #define IBSCTL_LVT_OFFSET_MASK      0x0F
0442
0443 /* IBS fetch bits/masks */
0444 #define IBS_FETCH_L3MISSONLY    (1ULL<<59)
0445 #define IBS_FETCH_RAND_EN   (1ULL<<57)
0446 #define IBS_FETCH_VAL       (1ULL<<49)
0447 #define IBS_FETCH_ENABLE    (1ULL<<48)
0448 #define IBS_FETCH_CNT       0xFFFF0000ULL
0449 #define IBS_FETCH_MAX_CNT   0x0000FFFFULL
0450
0451 /*
0452  * IBS op bits/masks
0453  * The lower 7 bits of the current count are random bits
0454  * preloaded by hardware and ignored in software
0455  */
0456 #define IBS_OP_CUR_CNT      (0xFFF80ULL<<32)
0457 #define IBS_OP_CUR_CNT_RAND (0x0007FULL<<32)
0458 #define IBS_OP_CNT_CTL      (1ULL<<19)
0459 #define IBS_OP_VAL      (1ULL<<18)
0460 #define IBS_OP_ENABLE       (1ULL<<17)
0461 #define IBS_OP_L3MISSONLY   (1ULL<<16)
0462 #define IBS_OP_MAX_CNT      0x0000FFFFULL
0463 #define IBS_OP_MAX_CNT_EXT  0x007FFFFFULL   /* not a register bit mask */
0464 #define IBS_OP_MAX_CNT_EXT_MASK (0x7FULL<<20)   /* separate upper 7 bits */
0465 #define IBS_RIP_INVALID     (1ULL<<38)
0466
0467 #ifdef CONFIG_X86_LOCAL_APIC
0468 extern u32 get_ibs_caps(void);
0469 #else
0470 static inline u32 get_ibs_caps(void) { return 0; }
0471 #endif
0472
0473 #ifdef CONFIG_PERF_EVENTS
0474 extern void perf_events_lapic_init(void);
0475
0476 /*
0477  * Abuse bits {3,5} of the cpu eflags register. These flags are otherwise
0478  * unused and ABI specified to be 0, so nobody should care what we do with
0479  * them.
0480  *
0481  * EXACT - the IP points to the exact instruction that triggered the
0482  *         event (HW bugs exempt).
0483  * VM    - original X86_VM_MASK; see set_linear_ip().
0484  */
0485 #define PERF_EFLAGS_EXACT   (1UL << 3)
0486 #define PERF_EFLAGS_VM      (1UL << 5)
0487
0488 struct pt_regs;
0489 struct x86_perf_regs {
0490     struct pt_regs  regs;
0491     u64     *xmm_regs;
0492 };
0493
0494 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
0495 extern unsigned long perf_misc_flags(struct pt_regs *regs);
0496 #define perf_misc_flags(regs)   perf_misc_flags(regs)
0497
0498 #include <asm/stacktrace.h>
0499
0500 /*
0501  * We abuse bit 3 from flags to pass exact information, see perf_misc_flags
0502  * and the comment with PERF_EFLAGS_EXACT.
0503  */
0504 #define perf_arch_fetch_caller_regs(regs, __ip)     {   \
0505     (regs)->ip = (__ip);                    \
0506     (regs)->sp = (unsigned long)__builtin_frame_address(0); \
0507     (regs)->cs = __KERNEL_CS;               \
0508     regs->flags = 0;                    \
0509 }
0510
0511 struct perf_guest_switch_msr {
0512     unsigned msr;
0513     u64 host, guest;
0514 };
0515
0516 struct x86_pmu_lbr {
0517     unsigned int    nr;
0518     unsigned int    from;
0519     unsigned int    to;
0520     unsigned int    info;
0521 };
0522
0523 extern void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap);
0524 extern u64 perf_get_hw_event_config(int hw_event);
0525 extern void perf_check_microcode(void);
0526 extern void perf_clear_dirty_counters(void);
0527 extern int x86_perf_rdpmc_index(struct perf_event *event);
0528 #else
0529 static inline void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
0530 {
0531     memset(cap, 0, sizeof(*cap));
0532 }
0533
0534 static inline u64 perf_get_hw_event_config(int hw_event)
0535 {
0536     return 0;
0537 }
0538
0539 static inline void perf_events_lapic_init(void) { }
0540 static inline void perf_check_microcode(void) { }
0541 #endif
0542
0543 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
0544 extern struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data);
0545 extern int x86_perf_get_lbr(struct x86_pmu_lbr *lbr);
0546 #else
0547 struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data);
0548 static inline int x86_perf_get_lbr(struct x86_pmu_lbr *lbr)
0549 {
0550     return -1;
0551 }
0552 #endif
0553
0554 #ifdef CONFIG_CPU_SUP_INTEL
0555  extern void intel_pt_handle_vmx(int on);
0556 #else
0557 static inline void intel_pt_handle_vmx(int on)
0558 {
0559
0560 }
0561 #endif
0562
0563 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
0564  extern void amd_pmu_enable_virt(void);
0565  extern void amd_pmu_disable_virt(void);
0566
0567 #if defined(CONFIG_PERF_EVENTS_AMD_BRS)
0568
0569 #define PERF_NEEDS_LOPWR_CB 1
0570
0571 /*
0572  * architectural low power callback impacts
0573  * drivers/acpi/processor_idle.c
0574  * drivers/acpi/acpi_pad.c
0575  */
0576 extern void perf_amd_brs_lopwr_cb(bool lopwr_in);
0577
0578 DECLARE_STATIC_CALL(perf_lopwr_cb, perf_amd_brs_lopwr_cb);
0579
0580 static inline void perf_lopwr_cb(bool lopwr_in)
0581 {
0582     static_call_mod(perf_lopwr_cb)(lopwr_in);
0583 }
0584
0585 #endif /* PERF_NEEDS_LOPWR_CB */
0586
0587 #else
0588  static inline void amd_pmu_enable_virt(void) { }
0589  static inline void amd_pmu_disable_virt(void) { }
0590 #endif
0591
0592 #define arch_perf_out_copy_user copy_from_user_nmi
0593
0594 #endif /* _ASM_X86_PERF_EVENT_H */