include/asm/pci_x86.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  Low-Level PCI Access for i386 machines.
0004  *
0005  *  (c) 1999 Martin Mares <mj@ucw.cz>
0006  */
0007
0008 #include <linux/errno.h>
0009 #include <linux/init.h>
0010 #include <linux/ioport.h>
0011 #include <linux/spinlock.h>
0012
0013 #undef DEBUG
0014
0015 #ifdef DEBUG
0016 #define DBG(fmt, ...) printk(fmt, ##__VA_ARGS__)
0017 #else
0018 #define DBG(fmt, ...)               \
0019 do {                        \
0020     if (0)                  \
0021         printk(fmt, ##__VA_ARGS__); \
0022 } while (0)
0023 #endif
0024
0025 #define PCI_PROBE_BIOS      0x0001
0026 #define PCI_PROBE_CONF1     0x0002
0027 #define PCI_PROBE_CONF2     0x0004
0028 #define PCI_PROBE_MMCONF    0x0008
0029 #define PCI_PROBE_MASK      0x000f
0030 #define PCI_PROBE_NOEARLY   0x0010
0031
0032 #define PCI_NO_CHECKS       0x0400
0033 #define PCI_USE_PIRQ_MASK   0x0800
0034 #define PCI_ASSIGN_ROMS     0x1000
0035 #define PCI_BIOS_IRQ_SCAN   0x2000
0036 #define PCI_ASSIGN_ALL_BUSSES   0x4000
0037 #define PCI_CAN_SKIP_ISA_ALIGN  0x8000
0038 #define PCI_USE__CRS        0x10000
0039 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
0040 #define PCI_HAS_IO_ECS      0x40000
0041 #define PCI_NOASSIGN_ROMS   0x80000
0042 #define PCI_ROOT_NO_CRS     0x100000
0043 #define PCI_NOASSIGN_BARS   0x200000
0044 #define PCI_BIG_ROOT_WINDOW 0x400000
0045 #define PCI_USE_E820        0x800000
0046 #define PCI_NO_E820     0x1000000
0047
0048 extern unsigned int pci_probe;
0049 extern unsigned long pirq_table_addr;
0050
0051 enum pci_bf_sort_state {
0052     pci_bf_sort_default,
0053     pci_force_nobf,
0054     pci_force_bf,
0055     pci_dmi_bf,
0056 };
0057
0058 /* pci-i386.c */
0059
0060 void pcibios_resource_survey(void);
0061 void pcibios_set_cache_line_size(void);
0062
0063 /* pci-pc.c */
0064
0065 extern int pcibios_last_bus;
0066 extern struct pci_ops pci_root_ops;
0067
0068 void pcibios_scan_specific_bus(int busn);
0069
0070 /* pci-irq.c */
0071
0072 struct pci_dev;
0073
0074 struct irq_info {
0075     u8 bus, devfn;          /* Bus, device and function */
0076     struct {
0077         u8 link;        /* IRQ line ID, chipset dependent,
0078                        0 = not routed */
0079         u16 bitmap;     /* Available IRQs */
0080     } __attribute__((packed)) irq[4];
0081     u8 slot;            /* Slot number, 0=onboard */
0082     u8 rfu;
0083 } __attribute__((packed));
0084
0085 struct irq_routing_table {
0086     u32 signature;          /* PIRQ_SIGNATURE should be here */
0087     u16 version;            /* PIRQ_VERSION */
0088     u16 size;           /* Table size in bytes */
0089     u8 rtr_bus, rtr_devfn;      /* Where the interrupt router lies */
0090     u16 exclusive_irqs;     /* IRQs devoted exclusively to
0091                        PCI usage */
0092     u16 rtr_vendor, rtr_device; /* Vendor and device ID of
0093                        interrupt router */
0094     u32 miniport_data;      /* Crap */
0095     u8 rfu[11];
0096     u8 checksum;            /* Modulo 256 checksum must give 0 */
0097     struct irq_info slots[];
0098 } __attribute__((packed));
0099
0100 struct irt_routing_table {
0101     u32 signature;          /* IRT_SIGNATURE should be here */
0102     u8 size;            /* Number of entries provided */
0103     u8 used;            /* Number of entries actually used */
0104     u16 exclusive_irqs;     /* IRQs devoted exclusively to
0105                        PCI usage */
0106     struct irq_info slots[];
0107 } __attribute__((packed));
0108
0109 extern unsigned int pcibios_irq_mask;
0110
0111 extern raw_spinlock_t pci_config_lock;
0112
0113 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
0114 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
0115
0116 extern bool mp_should_keep_irq(struct device *dev);
0117
0118 struct pci_raw_ops {
0119     int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
0120                         int reg, int len, u32 *val);
0121     int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
0122                         int reg, int len, u32 val);
0123 };
0124
0125 extern const struct pci_raw_ops *raw_pci_ops;
0126 extern const struct pci_raw_ops *raw_pci_ext_ops;
0127
0128 extern const struct pci_raw_ops pci_mmcfg;
0129 extern const struct pci_raw_ops pci_direct_conf1;
0130 extern bool port_cf9_safe;
0131
0132 /* arch_initcall level */
0133 #ifdef CONFIG_PCI_DIRECT
0134 extern int pci_direct_probe(void);
0135 extern void pci_direct_init(int type);
0136 #else
0137 static inline int pci_direct_probe(void) { return -1; }
0138 static inline  void pci_direct_init(int type) { }
0139 #endif
0140
0141 #ifdef CONFIG_PCI_BIOS
0142 extern void pci_pcbios_init(void);
0143 #else
0144 static inline void pci_pcbios_init(void) { }
0145 #endif
0146
0147 extern void __init dmi_check_pciprobe(void);
0148 extern void __init dmi_check_skip_isa_align(void);
0149
0150 /* some common used subsys_initcalls */
0151 #ifdef CONFIG_PCI
0152 extern int __init pci_acpi_init(void);
0153 #else
0154 static inline int  __init pci_acpi_init(void)
0155 {
0156     return -EINVAL;
0157 }
0158 #endif
0159 extern void __init pcibios_irq_init(void);
0160 extern int __init pcibios_init(void);
0161 extern int pci_legacy_init(void);
0162 extern void pcibios_fixup_irqs(void);
0163
0164 /* pci-mmconfig.c */
0165
0166 /* "PCI MMCONFIG %04x [bus %02x-%02x]" */
0167 #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
0168
0169 struct pci_mmcfg_region {
0170     struct list_head list;
0171     struct resource res;
0172     u64 address;
0173     char __iomem *virt;
0174     u16 segment;
0175     u8 start_bus;
0176     u8 end_bus;
0177     char name[PCI_MMCFG_RESOURCE_NAME_LEN];
0178 };
0179
0180 extern int __init pci_mmcfg_arch_init(void);
0181 extern void __init pci_mmcfg_arch_free(void);
0182 extern int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg);
0183 extern void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg);
0184 extern int pci_mmconfig_insert(struct device *dev, u16 seg, u8 start, u8 end,
0185                    phys_addr_t addr);
0186 extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
0187 extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
0188 extern struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
0189                             int end, u64 addr);
0190
0191 extern struct list_head pci_mmcfg_list;
0192
0193 #define PCI_MMCFG_BUS_OFFSET(bus)      ((bus) << 20)
0194
0195 /*
0196  * On AMD Fam10h CPUs, all PCI MMIO configuration space accesses must use
0197  * %eax.  No other source or target registers may be used.  The following
0198  * mmio_config_* accessors enforce this.  See "BIOS and Kernel Developer's
0199  * Guide (BKDG) For AMD Family 10h Processors", rev. 3.48, sec 2.11.1,
0200  * "MMIO Configuration Coding Requirements".
0201  */
0202 static inline unsigned char mmio_config_readb(void __iomem *pos)
0203 {
0204     u8 val;
0205     asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
0206     return val;
0207 }
0208
0209 static inline unsigned short mmio_config_readw(void __iomem *pos)
0210 {
0211     u16 val;
0212     asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
0213     return val;
0214 }
0215
0216 static inline unsigned int mmio_config_readl(void __iomem *pos)
0217 {
0218     u32 val;
0219     asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
0220     return val;
0221 }
0222
0223 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
0224 {
0225     asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
0226 }
0227
0228 static inline void mmio_config_writew(void __iomem *pos, u16 val)
0229 {
0230     asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
0231 }
0232
0233 static inline void mmio_config_writel(void __iomem *pos, u32 val)
0234 {
0235     asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
0236 }
0237
0238 #ifdef CONFIG_PCI
0239 # ifdef CONFIG_ACPI
0240 #  define x86_default_pci_init      pci_acpi_init
0241 # else
0242 #  define x86_default_pci_init      pci_legacy_init
0243 # endif
0244 # define x86_default_pci_init_irq   pcibios_irq_init
0245 # define x86_default_pci_fixup_irqs pcibios_fixup_irqs
0246 #else
0247 # define x86_default_pci_init       NULL
0248 # define x86_default_pci_init_irq   NULL
0249 # define x86_default_pci_fixup_irqs NULL
0250 #endif
0251
0252 #if defined(CONFIG_PCI) && defined(CONFIG_ACPI)
0253 extern bool pci_use_e820;
0254 #else
0255 #define pci_use_e820 false
0256 #endif