asm/numachip/numachip_csr.h

0001 /*
0002  * This file is subject to the terms and conditions of the GNU General Public
0003  * License.  See the file "COPYING" in the main directory of this archive
0004  * for more details.
0005  *
0006  * Numascale NumaConnect-Specific Header file
0007  *
0008  * Copyright (C) 2011 Numascale AS. All rights reserved.
0009  *
0010  * Send feedback to <support@numascale.com>
0011  *
0012  */
0013
0014 #ifndef _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
0015 #define _ASM_X86_NUMACHIP_NUMACHIP_CSR_H
0016
0017 #include <linux/smp.h>
0018 #include <linux/io.h>
0019
0020 #define CSR_NODE_SHIFT      16
0021 #define CSR_NODE_BITS(p)    (((unsigned long)(p)) << CSR_NODE_SHIFT)
0022 #define CSR_NODE_MASK       0x0fff      /* 4K nodes */
0023
0024 /* 32K CSR space, b15 indicates geo/non-geo */
0025 #define CSR_OFFSET_MASK 0x7fffUL
0026 #define CSR_G0_NODE_IDS (0x008 + (0 << 12))
0027 #define CSR_G3_EXT_IRQ_GEN (0x030 + (3 << 12))
0028
0029 /*
0030  * Local CSR space starts in global CSR space with "nodeid" = 0xfff0, however
0031  * when using the direct mapping on x86_64, both start and size needs to be
0032  * aligned with PMD_SIZE which is 2M
0033  */
0034 #define NUMACHIP_LCSR_BASE  0x3ffffe000000ULL
0035 #define NUMACHIP_LCSR_LIM   0x3fffffffffffULL
0036 #define NUMACHIP_LCSR_SIZE  (NUMACHIP_LCSR_LIM - NUMACHIP_LCSR_BASE + 1)
0037 #define NUMACHIP_LAPIC_BITS 8
0038
0039 static inline void *lcsr_address(unsigned long offset)
0040 {
0041     return __va(NUMACHIP_LCSR_BASE | (1UL << 15) |
0042         CSR_NODE_BITS(0xfff0) | (offset & CSR_OFFSET_MASK));
0043 }
0044
0045 static inline unsigned int read_lcsr(unsigned long offset)
0046 {
0047     return swab32(readl(lcsr_address(offset)));
0048 }
0049
0050 static inline void write_lcsr(unsigned long offset, unsigned int val)
0051 {
0052     writel(swab32(val), lcsr_address(offset));
0053 }
0054
0055 /*
0056  * On NumaChip2, local CSR space is 16MB and starts at fixed offset below 4G
0057  */
0058
0059 #define NUMACHIP2_LCSR_BASE       0xf0000000UL
0060 #define NUMACHIP2_LCSR_SIZE       0x1000000UL
0061 #define NUMACHIP2_APIC_ICR        0x100000
0062 #define NUMACHIP2_TIMER_DEADLINE  0x200000
0063 #define NUMACHIP2_TIMER_INT       0x200008
0064 #define NUMACHIP2_TIMER_NOW       0x200018
0065 #define NUMACHIP2_TIMER_RESET     0x200020
0066
0067 static inline void __iomem *numachip2_lcsr_address(unsigned long offset)
0068 {
0069     return (void __iomem *)__va(NUMACHIP2_LCSR_BASE |
0070         (offset & (NUMACHIP2_LCSR_SIZE - 1)));
0071 }
0072
0073 static inline u32 numachip2_read32_lcsr(unsigned long offset)
0074 {
0075     return readl(numachip2_lcsr_address(offset));
0076 }
0077
0078 static inline u64 numachip2_read64_lcsr(unsigned long offset)
0079 {
0080     return readq(numachip2_lcsr_address(offset));
0081 }
0082
0083 static inline void numachip2_write32_lcsr(unsigned long offset, u32 val)
0084 {
0085     writel(val, numachip2_lcsr_address(offset));
0086 }
0087
0088 static inline void numachip2_write64_lcsr(unsigned long offset, u64 val)
0089 {
0090     writeq(val, numachip2_lcsr_address(offset));
0091 }
0092
0093 static inline unsigned int numachip2_timer(void)
0094 {
0095     return (smp_processor_id() % 48) << 6;
0096 }
0097
0098 #endif /* _ASM_X86_NUMACHIP_NUMACHIP_CSR_H */