include/asm/mpspec_def.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_MPSPEC_DEF_H
0003 #define _ASM_X86_MPSPEC_DEF_H
0004
0005 /*
0006  * Structure definitions for SMP machines following the
0007  * Intel Multiprocessing Specification 1.1 and 1.4.
0008  */
0009
0010 /*
0011  * This tag identifies where the SMP configuration
0012  * information is.
0013  */
0014
0015 #define SMP_MAGIC_IDENT (('_'<<24) | ('P'<<16) | ('M'<<8) | '_')
0016
0017 #ifdef CONFIG_X86_32
0018 # define MAX_MPC_ENTRY 1024
0019 #endif
0020
0021 /* Intel MP Floating Pointer Structure */
0022 struct mpf_intel {
0023     char signature[4];      /* "_MP_"           */
0024     unsigned int physptr;       /* Configuration table address  */
0025     unsigned char length;       /* Our length (paragraphs)  */
0026     unsigned char specification;    /* Specification version    */
0027     unsigned char checksum;     /* Checksum (makes sum 0)   */
0028     unsigned char feature1;     /* Standard or configuration ?  */
0029     unsigned char feature2;     /* Bit7 set for IMCR|PIC    */
0030     unsigned char feature3;     /* Unused (0)           */
0031     unsigned char feature4;     /* Unused (0)           */
0032     unsigned char feature5;     /* Unused (0)           */
0033 };
0034
0035 #define MPC_SIGNATURE "PCMP"
0036
0037 struct mpc_table {
0038     char signature[4];
0039     unsigned short length;      /* Size of table */
0040     char spec;          /* 0x01 */
0041     char checksum;
0042     char oem[8];
0043     char productid[12];
0044     unsigned int oemptr;        /* 0 if not present */
0045     unsigned short oemsize;     /* 0 if not present */
0046     unsigned short oemcount;
0047     unsigned int lapic;     /* APIC address */
0048     unsigned int reserved;
0049 };
0050
0051 /* Followed by entries */
0052
0053 #define MP_PROCESSOR        0
0054 #define MP_BUS          1
0055 #define MP_IOAPIC       2
0056 #define MP_INTSRC       3
0057 #define MP_LINTSRC      4
0058 /* Used by IBM NUMA-Q to describe node locality */
0059 #define MP_TRANSLATION      192
0060
0061 #define CPU_ENABLED     1   /* Processor is available */
0062 #define CPU_BOOTPROCESSOR   2   /* Processor is the boot CPU */
0063
0064 #define CPU_STEPPING_MASK   0x000F
0065 #define CPU_MODEL_MASK      0x00F0
0066 #define CPU_FAMILY_MASK     0x0F00
0067
0068 struct mpc_cpu {
0069     unsigned char type;
0070     unsigned char apicid;       /* Local APIC number */
0071     unsigned char apicver;      /* Its versions */
0072     unsigned char cpuflag;
0073     unsigned int cpufeature;
0074     unsigned int featureflag;   /* CPUID feature value */
0075     unsigned int reserved[2];
0076 };
0077
0078 struct mpc_bus {
0079     unsigned char type;
0080     unsigned char busid;
0081     unsigned char bustype[6];
0082 };
0083
0084 /* List of Bus Type string values, Intel MP Spec. */
0085 #define BUSTYPE_EISA    "EISA"
0086 #define BUSTYPE_ISA "ISA"
0087 #define BUSTYPE_INTERN  "INTERN"    /* Internal BUS */
0088 #define BUSTYPE_MCA "MCA"       /* Obsolete */
0089 #define BUSTYPE_VL  "VL"        /* Local bus */
0090 #define BUSTYPE_PCI "PCI"
0091 #define BUSTYPE_PCMCIA  "PCMCIA"
0092 #define BUSTYPE_CBUS    "CBUS"
0093 #define BUSTYPE_CBUSII  "CBUSII"
0094 #define BUSTYPE_FUTURE  "FUTURE"
0095 #define BUSTYPE_MBI "MBI"
0096 #define BUSTYPE_MBII    "MBII"
0097 #define BUSTYPE_MPI "MPI"
0098 #define BUSTYPE_MPSA    "MPSA"
0099 #define BUSTYPE_NUBUS   "NUBUS"
0100 #define BUSTYPE_TC  "TC"
0101 #define BUSTYPE_VME "VME"
0102 #define BUSTYPE_XPRESS  "XPRESS"
0103
0104 #define MPC_APIC_USABLE     0x01
0105
0106 struct mpc_ioapic {
0107     unsigned char type;
0108     unsigned char apicid;
0109     unsigned char apicver;
0110     unsigned char flags;
0111     unsigned int apicaddr;
0112 };
0113
0114 struct mpc_intsrc {
0115     unsigned char type;
0116     unsigned char irqtype;
0117     unsigned short irqflag;
0118     unsigned char srcbus;
0119     unsigned char srcbusirq;
0120     unsigned char dstapic;
0121     unsigned char dstirq;
0122 };
0123
0124 enum mp_irq_source_types {
0125     mp_INT = 0,
0126     mp_NMI = 1,
0127     mp_SMI = 2,
0128     mp_ExtINT = 3
0129 };
0130
0131 #define MP_IRQPOL_DEFAULT   0x0
0132 #define MP_IRQPOL_ACTIVE_HIGH   0x1
0133 #define MP_IRQPOL_RESERVED  0x2
0134 #define MP_IRQPOL_ACTIVE_LOW    0x3
0135 #define MP_IRQPOL_MASK      0x3
0136
0137 #define MP_IRQTRIG_DEFAULT  0x0
0138 #define MP_IRQTRIG_EDGE     0x4
0139 #define MP_IRQTRIG_RESERVED 0x8
0140 #define MP_IRQTRIG_LEVEL    0xc
0141 #define MP_IRQTRIG_MASK     0xc
0142
0143 #define MP_APIC_ALL 0xFF
0144
0145 struct mpc_lintsrc {
0146     unsigned char type;
0147     unsigned char irqtype;
0148     unsigned short irqflag;
0149     unsigned char srcbusid;
0150     unsigned char srcbusirq;
0151     unsigned char destapic;
0152     unsigned char destapiclint;
0153 };
0154
0155 #define MPC_OEM_SIGNATURE "_OEM"
0156
0157 struct mpc_oemtable {
0158     char signature[4];
0159     unsigned short length;      /* Size of table */
0160     char  rev;          /* 0x01 */
0161     char  checksum;
0162     char  mpc[8];
0163 };
0164
0165 /*
0166  *  Default configurations
0167  *
0168  *  1   2 CPU ISA 82489DX
0169  *  2   2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining
0170  *  3   2 CPU EISA 82489DX
0171  *  4   2 CPU MCA 82489DX
0172  *  5   2 CPU ISA+PCI
0173  *  6   2 CPU EISA+PCI
0174  *  7   2 CPU MCA+PCI
0175  */
0176
0177 enum mp_bustype {
0178     MP_BUS_ISA = 1,
0179     MP_BUS_EISA,
0180     MP_BUS_PCI,
0181 };
0182 #endif /* _ASM_X86_MPSPEC_DEF_H */