include/asm/microcode_intel.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_MICROCODE_INTEL_H
0003 #define _ASM_X86_MICROCODE_INTEL_H
0004
0005 #include <asm/microcode.h>
0006
0007 struct microcode_header_intel {
0008     unsigned int            hdrver;
0009     unsigned int            rev;
0010     unsigned int            date;
0011     unsigned int            sig;
0012     unsigned int            cksum;
0013     unsigned int            ldrver;
0014     unsigned int            pf;
0015     unsigned int            datasize;
0016     unsigned int            totalsize;
0017     unsigned int            reserved[3];
0018 };
0019
0020 struct microcode_intel {
0021     struct microcode_header_intel hdr;
0022     unsigned int            bits[];
0023 };
0024
0025 /* microcode format is extended from prescott processors */
0026 struct extended_signature {
0027     unsigned int            sig;
0028     unsigned int            pf;
0029     unsigned int            cksum;
0030 };
0031
0032 struct extended_sigtable {
0033     unsigned int            count;
0034     unsigned int            cksum;
0035     unsigned int            reserved[3];
0036     struct extended_signature sigs[];
0037 };
0038
0039 #define DEFAULT_UCODE_DATASIZE  (2000)
0040 #define MC_HEADER_SIZE      (sizeof(struct microcode_header_intel))
0041 #define DEFAULT_UCODE_TOTALSIZE (DEFAULT_UCODE_DATASIZE + MC_HEADER_SIZE)
0042 #define EXT_HEADER_SIZE     (sizeof(struct extended_sigtable))
0043 #define EXT_SIGNATURE_SIZE  (sizeof(struct extended_signature))
0044
0045 #define get_totalsize(mc) \
0046     (((struct microcode_intel *)mc)->hdr.datasize ? \
0047      ((struct microcode_intel *)mc)->hdr.totalsize : \
0048      DEFAULT_UCODE_TOTALSIZE)
0049
0050 #define get_datasize(mc) \
0051     (((struct microcode_intel *)mc)->hdr.datasize ? \
0052      ((struct microcode_intel *)mc)->hdr.datasize : DEFAULT_UCODE_DATASIZE)
0053
0054 #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
0055
0056 static inline u32 intel_get_microcode_revision(void)
0057 {
0058     u32 rev, dummy;
0059
0060     native_wrmsrl(MSR_IA32_UCODE_REV, 0);
0061
0062     /* As documented in the SDM: Do a CPUID 1 here */
0063     native_cpuid_eax(1);
0064
0065     /* get the current revision from MSR 0x8B */
0066     native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
0067
0068     return rev;
0069 }
0070
0071 #ifdef CONFIG_MICROCODE_INTEL
0072 extern void __init load_ucode_intel_bsp(void);
0073 extern void load_ucode_intel_ap(void);
0074 extern void show_ucode_info_early(void);
0075 extern int __init save_microcode_in_initrd_intel(void);
0076 void reload_ucode_intel(void);
0077 #else
0078 static inline __init void load_ucode_intel_bsp(void) {}
0079 static inline void load_ucode_intel_ap(void) {}
0080 static inline void show_ucode_info_early(void) {}
0081 static inline int __init save_microcode_in_initrd_intel(void) { return -EINVAL; }
0082 static inline void reload_ucode_intel(void) {}
0083 #endif
0084
0085 #endif /* _ASM_X86_MICROCODE_INTEL_H */