include/asm/microcode_amd.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_MICROCODE_AMD_H
0003 #define _ASM_X86_MICROCODE_AMD_H
0004
0005 #include <asm/microcode.h>
0006
0007 #define UCODE_MAGIC         0x00414d44
0008 #define UCODE_EQUIV_CPU_TABLE_TYPE  0x00000000
0009 #define UCODE_UCODE_TYPE        0x00000001
0010
0011 #define SECTION_HDR_SIZE        8
0012 #define CONTAINER_HDR_SZ        12
0013
0014 struct equiv_cpu_entry {
0015     u32 installed_cpu;
0016     u32 fixed_errata_mask;
0017     u32 fixed_errata_compare;
0018     u16 equiv_cpu;
0019     u16 res;
0020 } __attribute__((packed));
0021
0022 struct microcode_header_amd {
0023     u32 data_code;
0024     u32 patch_id;
0025     u16 mc_patch_data_id;
0026     u8  mc_patch_data_len;
0027     u8  init_flag;
0028     u32 mc_patch_data_checksum;
0029     u32 nb_dev_id;
0030     u32 sb_dev_id;
0031     u16 processor_rev_id;
0032     u8  nb_rev_id;
0033     u8  sb_rev_id;
0034     u8  bios_api_rev;
0035     u8  reserved1[3];
0036     u32 match_reg[8];
0037 } __attribute__((packed));
0038
0039 struct microcode_amd {
0040     struct microcode_header_amd hdr;
0041     unsigned int            mpb[];
0042 };
0043
0044 #define PATCH_MAX_SIZE (3 * PAGE_SIZE)
0045
0046 #ifdef CONFIG_MICROCODE_AMD
0047 extern void __init load_ucode_amd_bsp(unsigned int family);
0048 extern void load_ucode_amd_ap(unsigned int family);
0049 extern int __init save_microcode_in_initrd_amd(unsigned int family);
0050 void reload_ucode_amd(void);
0051 #else
0052 static inline void __init load_ucode_amd_bsp(unsigned int family) {}
0053 static inline void load_ucode_amd_ap(unsigned int family) {}
0054 static inline int __init
0055 save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }
0056 static inline void reload_ucode_amd(void) {}
0057 #endif
0058 #endif /* _ASM_X86_MICROCODE_AMD_H */