include/asm/mce.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_MCE_H
0003 #define _ASM_X86_MCE_H
0004
0005 #include <uapi/asm/mce.h>
0006
0007 /*
0008  * Machine Check support for x86
0009  */
0010
0011 /* MCG_CAP register defines */
0012 #define MCG_BANKCNT_MASK    0xff         /* Number of Banks */
0013 #define MCG_CTL_P       BIT_ULL(8)   /* MCG_CTL register available */
0014 #define MCG_EXT_P       BIT_ULL(9)   /* Extended registers available */
0015 #define MCG_CMCI_P      BIT_ULL(10)  /* CMCI supported */
0016 #define MCG_EXT_CNT_MASK    0xff0000     /* Number of Extended registers */
0017 #define MCG_EXT_CNT_SHIFT   16
0018 #define MCG_EXT_CNT(c)      (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
0019 #define MCG_SER_P       BIT_ULL(24)  /* MCA recovery/new status bits */
0020 #define MCG_ELOG_P      BIT_ULL(26)  /* Extended error log supported */
0021 #define MCG_LMCE_P      BIT_ULL(27)  /* Local machine check supported */
0022
0023 /* MCG_STATUS register defines */
0024 #define MCG_STATUS_RIPV     BIT_ULL(0)   /* restart ip valid */
0025 #define MCG_STATUS_EIPV     BIT_ULL(1)   /* ip points to correct instruction */
0026 #define MCG_STATUS_MCIP     BIT_ULL(2)   /* machine check in progress */
0027 #define MCG_STATUS_LMCES    BIT_ULL(3)   /* LMCE signaled */
0028
0029 /* MCG_EXT_CTL register defines */
0030 #define MCG_EXT_CTL_LMCE_EN BIT_ULL(0) /* Enable LMCE */
0031
0032 /* MCi_STATUS register defines */
0033 #define MCI_STATUS_VAL      BIT_ULL(63)  /* valid error */
0034 #define MCI_STATUS_OVER     BIT_ULL(62)  /* previous errors lost */
0035 #define MCI_STATUS_UC       BIT_ULL(61)  /* uncorrected error */
0036 #define MCI_STATUS_EN       BIT_ULL(60)  /* error enabled */
0037 #define MCI_STATUS_MISCV    BIT_ULL(59)  /* misc error reg. valid */
0038 #define MCI_STATUS_ADDRV    BIT_ULL(58)  /* addr reg. valid */
0039 #define MCI_STATUS_PCC      BIT_ULL(57)  /* processor context corrupt */
0040 #define MCI_STATUS_S        BIT_ULL(56)  /* Signaled machine check */
0041 #define MCI_STATUS_AR       BIT_ULL(55)  /* Action required */
0042 #define MCI_STATUS_CEC_SHIFT    38           /* Corrected Error Count */
0043 #define MCI_STATUS_CEC_MASK GENMASK_ULL(52,38)
0044 #define MCI_STATUS_CEC(c)   (((c) & MCI_STATUS_CEC_MASK) >> MCI_STATUS_CEC_SHIFT)
0045
0046 /* AMD-specific bits */
0047 #define MCI_STATUS_TCC      BIT_ULL(55)  /* Task context corrupt */
0048 #define MCI_STATUS_SYNDV    BIT_ULL(53)  /* synd reg. valid */
0049 #define MCI_STATUS_DEFERRED BIT_ULL(44)  /* uncorrected error, deferred exception */
0050 #define MCI_STATUS_POISON   BIT_ULL(43)  /* access poisonous data */
0051 #define MCI_STATUS_SCRUB    BIT_ULL(40)  /* Error detected during scrub operation */
0052
0053 /*
0054  * McaX field if set indicates a given bank supports MCA extensions:
0055  *  - Deferred error interrupt type is specifiable by bank.
0056  *  - MCx_MISC0[BlkPtr] field indicates presence of extended MISC registers,
0057  *    But should not be used to determine MSR numbers.
0058  *  - TCC bit is present in MCx_STATUS.
0059  */
0060 #define MCI_CONFIG_MCAX     0x1
0061 #define MCI_IPID_MCATYPE    0xFFFF0000
0062 #define MCI_IPID_HWID       0xFFF
0063
0064 /*
0065  * Note that the full MCACOD field of IA32_MCi_STATUS MSR is
0066  * bits 15:0.  But bit 12 is the 'F' bit, defined for corrected
0067  * errors to indicate that errors are being filtered by hardware.
0068  * We should mask out bit 12 when looking for specific signatures
0069  * of uncorrected errors - so the F bit is deliberately skipped
0070  * in this #define.
0071  */
0072 #define MCACOD        0xefff     /* MCA Error Code */
0073
0074 /* Architecturally defined codes from SDM Vol. 3B Chapter 15 */
0075 #define MCACOD_SCRUB    0x00C0  /* 0xC0-0xCF Memory Scrubbing */
0076 #define MCACOD_SCRUBMSK 0xeff0  /* Skip bit 12 ('F' bit) */
0077 #define MCACOD_L3WB 0x017A  /* L3 Explicit Writeback */
0078 #define MCACOD_DATA 0x0134  /* Data Load */
0079 #define MCACOD_INSTR    0x0150  /* Instruction Fetch */
0080
0081 /* MCi_MISC register defines */
0082 #define MCI_MISC_ADDR_LSB(m)    ((m) & 0x3f)
0083 #define MCI_MISC_ADDR_MODE(m)   (((m) >> 6) & 7)
0084 #define  MCI_MISC_ADDR_SEGOFF   0   /* segment offset */
0085 #define  MCI_MISC_ADDR_LINEAR   1   /* linear address */
0086 #define  MCI_MISC_ADDR_PHYS 2   /* physical address */
0087 #define  MCI_MISC_ADDR_MEM  3   /* memory address */
0088 #define  MCI_MISC_ADDR_GENERIC  7   /* generic */
0089
0090 /* CTL2 register defines */
0091 #define MCI_CTL2_CMCI_EN        BIT_ULL(30)
0092 #define MCI_CTL2_CMCI_THRESHOLD_MASK    0x7fffULL
0093
0094 #define MCJ_CTX_MASK        3
0095 #define MCJ_CTX(flags)      ((flags) & MCJ_CTX_MASK)
0096 #define MCJ_CTX_RANDOM      0    /* inject context: random */
0097 #define MCJ_CTX_PROCESS     0x1  /* inject context: process */
0098 #define MCJ_CTX_IRQ     0x2  /* inject context: IRQ */
0099 #define MCJ_NMI_BROADCAST   0x4  /* do NMI broadcasting */
0100 #define MCJ_EXCEPTION       0x8  /* raise as exception */
0101 #define MCJ_IRQ_BROADCAST   0x10 /* do IRQ broadcasting */
0102
0103 #define MCE_OVERFLOW 0      /* bit 0 in flags means overflow */
0104
0105 #define MCE_LOG_MIN_LEN 32U
0106 #define MCE_LOG_SIGNATURE   "MACHINECHECK"
0107
0108 /* AMD Scalable MCA */
0109 #define MSR_AMD64_SMCA_MC0_CTL      0xc0002000
0110 #define MSR_AMD64_SMCA_MC0_STATUS   0xc0002001
0111 #define MSR_AMD64_SMCA_MC0_ADDR     0xc0002002
0112 #define MSR_AMD64_SMCA_MC0_MISC0    0xc0002003
0113 #define MSR_AMD64_SMCA_MC0_CONFIG   0xc0002004
0114 #define MSR_AMD64_SMCA_MC0_IPID     0xc0002005
0115 #define MSR_AMD64_SMCA_MC0_SYND     0xc0002006
0116 #define MSR_AMD64_SMCA_MC0_DESTAT   0xc0002008
0117 #define MSR_AMD64_SMCA_MC0_DEADDR   0xc0002009
0118 #define MSR_AMD64_SMCA_MC0_MISC1    0xc000200a
0119 #define MSR_AMD64_SMCA_MCx_CTL(x)   (MSR_AMD64_SMCA_MC0_CTL + 0x10*(x))
0120 #define MSR_AMD64_SMCA_MCx_STATUS(x)    (MSR_AMD64_SMCA_MC0_STATUS + 0x10*(x))
0121 #define MSR_AMD64_SMCA_MCx_ADDR(x)  (MSR_AMD64_SMCA_MC0_ADDR + 0x10*(x))
0122 #define MSR_AMD64_SMCA_MCx_MISC(x)  (MSR_AMD64_SMCA_MC0_MISC0 + 0x10*(x))
0123 #define MSR_AMD64_SMCA_MCx_CONFIG(x)    (MSR_AMD64_SMCA_MC0_CONFIG + 0x10*(x))
0124 #define MSR_AMD64_SMCA_MCx_IPID(x)  (MSR_AMD64_SMCA_MC0_IPID + 0x10*(x))
0125 #define MSR_AMD64_SMCA_MCx_SYND(x)  (MSR_AMD64_SMCA_MC0_SYND + 0x10*(x))
0126 #define MSR_AMD64_SMCA_MCx_DESTAT(x)    (MSR_AMD64_SMCA_MC0_DESTAT + 0x10*(x))
0127 #define MSR_AMD64_SMCA_MCx_DEADDR(x)    (MSR_AMD64_SMCA_MC0_DEADDR + 0x10*(x))
0128 #define MSR_AMD64_SMCA_MCx_MISCy(x, y)  ((MSR_AMD64_SMCA_MC0_MISC1 + y) + (0x10*(x)))
0129
0130 #define XEC(x, mask)            (((x) >> 16) & mask)
0131
0132 /* mce.kflags flag bits for logging etc. */
0133 #define MCE_HANDLED_CEC     BIT_ULL(0)
0134 #define MCE_HANDLED_UC      BIT_ULL(1)
0135 #define MCE_HANDLED_EXTLOG  BIT_ULL(2)
0136 #define MCE_HANDLED_NFIT    BIT_ULL(3)
0137 #define MCE_HANDLED_EDAC    BIT_ULL(4)
0138 #define MCE_HANDLED_MCELOG  BIT_ULL(5)
0139
0140 /*
0141  * Indicates an MCE which has happened in kernel space but from
0142  * which the kernel can recover simply by executing fixup_exception()
0143  * so that an error is returned to the caller of the function that
0144  * hit the machine check.
0145  */
0146 #define MCE_IN_KERNEL_RECOV BIT_ULL(6)
0147
0148 /*
0149  * Indicates an MCE that happened in kernel space while copying data
0150  * from user. In this case fixup_exception() gets the kernel to the
0151  * error exit for the copy function. Machine check handler can then
0152  * treat it like a fault taken in user mode.
0153  */
0154 #define MCE_IN_KERNEL_COPYIN    BIT_ULL(7)
0155
0156 /*
0157  * This structure contains all data related to the MCE log.  Also
0158  * carries a signature to make it easier to find from external
0159  * debugging tools.  Each entry is only valid when its finished flag
0160  * is set.
0161  */
0162 struct mce_log_buffer {
0163     char signature[12]; /* "MACHINECHECK" */
0164     unsigned len;       /* = elements in .mce_entry[] */
0165     unsigned next;
0166     unsigned flags;
0167     unsigned recordlen; /* length of struct mce */
0168     struct mce entry[];
0169 };
0170
0171 /* Highest last */
0172 enum mce_notifier_prios {
0173     MCE_PRIO_LOWEST,
0174     MCE_PRIO_MCELOG,
0175     MCE_PRIO_EDAC,
0176     MCE_PRIO_NFIT,
0177     MCE_PRIO_EXTLOG,
0178     MCE_PRIO_UC,
0179     MCE_PRIO_EARLY,
0180     MCE_PRIO_CEC,
0181     MCE_PRIO_HIGHEST = MCE_PRIO_CEC
0182 };
0183
0184 struct notifier_block;
0185 extern void mce_register_decode_chain(struct notifier_block *nb);
0186 extern void mce_unregister_decode_chain(struct notifier_block *nb);
0187
0188 #include <linux/percpu.h>
0189 #include <linux/atomic.h>
0190
0191 extern int mce_p5_enabled;
0192
0193 #ifdef CONFIG_ARCH_HAS_COPY_MC
0194 extern void enable_copy_mc_fragile(void);
0195 unsigned long __must_check copy_mc_fragile(void *dst, const void *src, unsigned cnt);
0196 #else
0197 static inline void enable_copy_mc_fragile(void)
0198 {
0199 }
0200 #endif
0201
0202 struct cper_ia_proc_ctx;
0203
0204 #ifdef CONFIG_X86_MCE
0205 int mcheck_init(void);
0206 void mcheck_cpu_init(struct cpuinfo_x86 *c);
0207 void mcheck_cpu_clear(struct cpuinfo_x86 *c);
0208 int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
0209                    u64 lapic_id);
0210 #else
0211 static inline int mcheck_init(void) { return 0; }
0212 static inline void mcheck_cpu_init(struct cpuinfo_x86 *c) {}
0213 static inline void mcheck_cpu_clear(struct cpuinfo_x86 *c) {}
0214 static inline int apei_smca_report_x86_error(struct cper_ia_proc_ctx *ctx_info,
0215                          u64 lapic_id) { return -EINVAL; }
0216 #endif
0217
0218 void mce_setup(struct mce *m);
0219 void mce_log(struct mce *m);
0220 DECLARE_PER_CPU(struct device *, mce_device);
0221
0222 /* Maximum number of MCA banks per CPU. */
0223 #define MAX_NR_BANKS 64
0224
0225 #ifdef CONFIG_X86_MCE_INTEL
0226 void mce_intel_feature_init(struct cpuinfo_x86 *c);
0227 void mce_intel_feature_clear(struct cpuinfo_x86 *c);
0228 void cmci_clear(void);
0229 void cmci_reenable(void);
0230 void cmci_rediscover(void);
0231 void cmci_recheck(void);
0232 #else
0233 static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
0234 static inline void mce_intel_feature_clear(struct cpuinfo_x86 *c) { }
0235 static inline void cmci_clear(void) {}
0236 static inline void cmci_reenable(void) {}
0237 static inline void cmci_rediscover(void) {}
0238 static inline void cmci_recheck(void) {}
0239 #endif
0240
0241 int mce_available(struct cpuinfo_x86 *c);
0242 bool mce_is_memory_error(struct mce *m);
0243 bool mce_is_correctable(struct mce *m);
0244 int mce_usable_address(struct mce *m);
0245
0246 DECLARE_PER_CPU(unsigned, mce_exception_count);
0247 DECLARE_PER_CPU(unsigned, mce_poll_count);
0248
0249 typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
0250 DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
0251
0252 enum mcp_flags {
0253     MCP_TIMESTAMP   = BIT(0),   /* log time stamp */
0254     MCP_UC      = BIT(1),   /* log uncorrected errors */
0255     MCP_DONTLOG = BIT(2),   /* only clear, don't log */
0256     MCP_QUEUE_LOG   = BIT(3),   /* only queue to genpool */
0257 };
0258 bool machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
0259
0260 int mce_notify_irq(void);
0261
0262 DECLARE_PER_CPU(struct mce, injectm);
0263
0264 /* Disable CMCI/polling for MCA bank claimed by firmware */
0265 extern void mce_disable_bank(int bank);
0266
0267 /*
0268  * Exception handler
0269  */
0270 void do_machine_check(struct pt_regs *pt_regs);
0271
0272 /*
0273  * Threshold handler
0274  */
0275 extern void (*mce_threshold_vector)(void);
0276
0277 /* Deferred error interrupt handler */
0278 extern void (*deferred_error_int_vector)(void);
0279
0280 /*
0281  * Used by APEI to report memory error via /dev/mcelog
0282  */
0283
0284 struct cper_sec_mem_err;
0285 extern void apei_mce_report_mem_error(int corrected,
0286                       struct cper_sec_mem_err *mem_err);
0287
0288 /*
0289  * Enumerate new IP types and HWID values in AMD processors which support
0290  * Scalable MCA.
0291  */
0292 #ifdef CONFIG_X86_MCE_AMD
0293
0294 /* These may be used by multiple smca_hwid_mcatypes */
0295 enum smca_bank_types {
0296     SMCA_LS = 0,    /* Load Store */
0297     SMCA_LS_V2,
0298     SMCA_IF,    /* Instruction Fetch */
0299     SMCA_L2_CACHE,  /* L2 Cache */
0300     SMCA_DE,    /* Decoder Unit */
0301     SMCA_RESERVED,  /* Reserved */
0302     SMCA_EX,    /* Execution Unit */
0303     SMCA_FP,    /* Floating Point */
0304     SMCA_L3_CACHE,  /* L3 Cache */
0305     SMCA_CS,    /* Coherent Slave */
0306     SMCA_CS_V2,
0307     SMCA_PIE,   /* Power, Interrupts, etc. */
0308     SMCA_UMC,   /* Unified Memory Controller */
0309     SMCA_UMC_V2,
0310     SMCA_PB,    /* Parameter Block */
0311     SMCA_PSP,   /* Platform Security Processor */
0312     SMCA_PSP_V2,
0313     SMCA_SMU,   /* System Management Unit */
0314     SMCA_SMU_V2,
0315     SMCA_MP5,   /* Microprocessor 5 Unit */
0316     SMCA_MPDMA, /* MPDMA Unit */
0317     SMCA_NBIO,  /* Northbridge IO Unit */
0318     SMCA_PCIE,  /* PCI Express Unit */
0319     SMCA_PCIE_V2,
0320     SMCA_XGMI_PCS,  /* xGMI PCS Unit */
0321     SMCA_NBIF,  /* NBIF Unit */
0322     SMCA_SHUB,  /* System HUB Unit */
0323     SMCA_SATA,  /* SATA Unit */
0324     SMCA_USB,   /* USB Unit */
0325     SMCA_GMI_PCS,   /* GMI PCS Unit */
0326     SMCA_XGMI_PHY,  /* xGMI PHY Unit */
0327     SMCA_WAFL_PHY,  /* WAFL PHY Unit */
0328     SMCA_GMI_PHY,   /* GMI PHY Unit */
0329     N_SMCA_BANK_TYPES
0330 };
0331
0332 extern const char *smca_get_long_name(enum smca_bank_types t);
0333 extern bool amd_mce_is_memory_error(struct mce *m);
0334
0335 extern int mce_threshold_create_device(unsigned int cpu);
0336 extern int mce_threshold_remove_device(unsigned int cpu);
0337
0338 void mce_amd_feature_init(struct cpuinfo_x86 *c);
0339 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank);
0340 #else
0341
0342 static inline int mce_threshold_create_device(unsigned int cpu)     { return 0; };
0343 static inline int mce_threshold_remove_device(unsigned int cpu)     { return 0; };
0344 static inline bool amd_mce_is_memory_error(struct mce *m)       { return false; };
0345 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)      { }
0346 #endif
0347
0348 static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c)    { return mce_amd_feature_init(c); }
0349 #endif /* _ASM_X86_MCE_H */