include/asm/mach_timer.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *  Machine specific calibrate_tsc() for generic.
0004  *  Split out from timer_tsc.c by Osamu Tomita <tomita@cinet.co.jp>
0005  */
0006 /* ------ Calibrate the TSC -------
0007  * Return 2^32 * (1 / (TSC clocks per usec)) for do_fast_gettimeoffset().
0008  * Too much 64-bit arithmetic here to do this cleanly in C, and for
0009  * accuracy's sake we want to keep the overhead on the CTC speaker (channel 2)
0010  * output busy loop as low as possible. We avoid reading the CTC registers
0011  * directly because of the awkward 8-bit access mechanism of the 82C54
0012  * device.
0013  */
0014 #ifndef _ASM_X86_MACH_DEFAULT_MACH_TIMER_H
0015 #define _ASM_X86_MACH_DEFAULT_MACH_TIMER_H
0016
0017 #define CALIBRATE_TIME_MSEC 30 /* 30 msecs */
0018 #define CALIBRATE_LATCH \
0019     ((PIT_TICK_RATE * CALIBRATE_TIME_MSEC + 1000/2)/1000)
0020
0021 static inline void mach_prepare_counter(void)
0022 {
0023        /* Set the Gate high, disable speaker */
0024     outb((inb(0x61) & ~0x02) | 0x01, 0x61);
0025
0026     /*
0027      * Now let's take care of CTC channel 2
0028      *
0029      * Set the Gate high, program CTC channel 2 for mode 0,
0030      * (interrupt on terminal count mode), binary count,
0031      * load 5 * LATCH count, (LSB and MSB) to begin countdown.
0032      *
0033      * Some devices need a delay here.
0034      */
0035     outb(0xb0, 0x43);           /* binary, mode 0, LSB/MSB, Ch 2 */
0036     outb_p(CALIBRATE_LATCH & 0xff, 0x42);   /* LSB of count */
0037     outb_p(CALIBRATE_LATCH >> 8, 0x42);       /* MSB of count */
0038 }
0039
0040 static inline void mach_countup(unsigned long *count_p)
0041 {
0042     unsigned long count = 0;
0043     do {
0044         count++;
0045     } while ((inb_p(0x61) & 0x20) == 0);
0046     *count_p = count;
0047 }
0048
0049 #endif /* _ASM_X86_MACH_DEFAULT_MACH_TIMER_H */