0001
0002 #ifndef _ASM_X86_IO_APIC_H
0003 #define _ASM_X86_IO_APIC_H
0004
0005 #include <linux/types.h>
0006 #include <asm/mpspec.h>
0007 #include <asm/apicdef.h>
0008 #include <asm/irq_vectors.h>
0009 #include <asm/x86_init.h>
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019 union IO_APIC_reg_00 {
0020 u32 raw;
0021 struct {
0022 u32 __reserved_2 : 14,
0023 LTS : 1,
0024 delivery_type : 1,
0025 __reserved_1 : 8,
0026 ID : 8;
0027 } __attribute__ ((packed)) bits;
0028 };
0029
0030 union IO_APIC_reg_01 {
0031 u32 raw;
0032 struct {
0033 u32 version : 8,
0034 __reserved_2 : 7,
0035 PRQ : 1,
0036 entries : 8,
0037 __reserved_1 : 8;
0038 } __attribute__ ((packed)) bits;
0039 };
0040
0041 union IO_APIC_reg_02 {
0042 u32 raw;
0043 struct {
0044 u32 __reserved_2 : 24,
0045 arbitration : 4,
0046 __reserved_1 : 4;
0047 } __attribute__ ((packed)) bits;
0048 };
0049
0050 union IO_APIC_reg_03 {
0051 u32 raw;
0052 struct {
0053 u32 boot_DT : 1,
0054 __reserved_1 : 31;
0055 } __attribute__ ((packed)) bits;
0056 };
0057
0058 struct IO_APIC_route_entry {
0059 union {
0060 struct {
0061 u64 vector : 8,
0062 delivery_mode : 3,
0063 dest_mode_logical : 1,
0064 delivery_status : 1,
0065 active_low : 1,
0066 irr : 1,
0067 is_level : 1,
0068 masked : 1,
0069 reserved_0 : 15,
0070 reserved_1 : 17,
0071 virt_destid_8_14 : 7,
0072 destid_0_7 : 8;
0073 };
0074 struct {
0075 u64 ir_shared_0 : 8,
0076 ir_zero : 3,
0077 ir_index_15 : 1,
0078 ir_shared_1 : 5,
0079 ir_reserved_0 : 31,
0080 ir_format : 1,
0081 ir_index_0_14 : 15;
0082 };
0083 struct {
0084 u64 w1 : 32,
0085 w2 : 32;
0086 };
0087 };
0088 } __attribute__ ((packed));
0089
0090 struct irq_alloc_info;
0091 struct ioapic_domain_cfg;
0092
0093 #define IOAPIC_MAP_ALLOC 0x1
0094 #define IOAPIC_MAP_CHECK 0x2
0095
0096 #ifdef CONFIG_X86_IO_APIC
0097
0098
0099
0100
0101 extern int nr_ioapics;
0102
0103 extern int mpc_ioapic_id(int ioapic);
0104 extern unsigned int mpc_ioapic_addr(int ioapic);
0105
0106
0107 extern int mp_irq_entries;
0108
0109
0110 extern struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
0111
0112
0113 extern int skip_ioapic_setup;
0114
0115
0116 extern int noioapicquirk;
0117
0118
0119 extern int noioapicreroute;
0120
0121 extern u32 gsi_top;
0122
0123 extern unsigned long io_apic_irqs;
0124
0125 #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1 << (x)) & io_apic_irqs))
0126
0127
0128
0129
0130
0131 #define io_apic_assign_pci_irqs \
0132 (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
0133
0134 struct irq_cfg;
0135 extern void ioapic_insert_resources(void);
0136 extern int arch_early_ioapic_init(void);
0137
0138 extern int save_ioapic_entries(void);
0139 extern void mask_ioapic_entries(void);
0140 extern int restore_ioapic_entries(void);
0141
0142 extern void setup_ioapic_ids_from_mpc(void);
0143 extern void setup_ioapic_ids_from_mpc_nocheck(void);
0144
0145 extern int mp_find_ioapic(u32 gsi);
0146 extern int mp_find_ioapic_pin(int ioapic, u32 gsi);
0147 extern int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
0148 struct irq_alloc_info *info);
0149 extern void mp_unmap_irq(int irq);
0150 extern int mp_register_ioapic(int id, u32 address, u32 gsi_base,
0151 struct ioapic_domain_cfg *cfg);
0152 extern int mp_unregister_ioapic(u32 gsi_base);
0153 extern int mp_ioapic_registered(u32 gsi_base);
0154
0155 extern void ioapic_set_alloc_attr(struct irq_alloc_info *info,
0156 int node, int trigger, int polarity);
0157
0158 extern void mp_save_irq(struct mpc_intsrc *m);
0159
0160 extern void disable_ioapic_support(void);
0161
0162 extern void __init io_apic_init_mappings(void);
0163 extern unsigned int native_io_apic_read(unsigned int apic, unsigned int reg);
0164 extern void native_restore_boot_irq_mode(void);
0165
0166 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
0167 {
0168 return x86_apic_ops.io_apic_read(apic, reg);
0169 }
0170
0171 extern void setup_IO_APIC(void);
0172 extern void enable_IO_APIC(void);
0173 extern void clear_IO_APIC(void);
0174 extern void restore_boot_irq_mode(void);
0175 extern int IO_APIC_get_PCI_irq_vector(int bus, int devfn, int pin);
0176 extern void print_IO_APICs(void);
0177 #else
0178
0179 #define IO_APIC_IRQ(x) 0
0180 #define io_apic_assign_pci_irqs 0
0181 #define setup_ioapic_ids_from_mpc x86_init_noop
0182 static inline void ioapic_insert_resources(void) { }
0183 static inline int arch_early_ioapic_init(void) { return 0; }
0184 static inline void print_IO_APICs(void) {}
0185 #define gsi_top (NR_IRQS_LEGACY)
0186 static inline int mp_find_ioapic(u32 gsi) { return 0; }
0187 static inline int mp_map_gsi_to_irq(u32 gsi, unsigned int flags,
0188 struct irq_alloc_info *info)
0189 {
0190 return gsi;
0191 }
0192
0193 static inline void mp_unmap_irq(int irq) { }
0194
0195 static inline int save_ioapic_entries(void)
0196 {
0197 return -ENOMEM;
0198 }
0199
0200 static inline void mask_ioapic_entries(void) { }
0201 static inline int restore_ioapic_entries(void)
0202 {
0203 return -ENOMEM;
0204 }
0205
0206 static inline void mp_save_irq(struct mpc_intsrc *m) { }
0207 static inline void disable_ioapic_support(void) { }
0208 static inline void io_apic_init_mappings(void) { }
0209 #define native_io_apic_read NULL
0210 #define native_restore_boot_irq_mode NULL
0211
0212 static inline void setup_IO_APIC(void) { }
0213 static inline void enable_IO_APIC(void) { }
0214 static inline void restore_boot_irq_mode(void) { }
0215
0216 #endif
0217
0218 #endif