include/asm/intel_punit_ipc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_INTEL_PUNIT_IPC_H_
0003 #define  _ASM_X86_INTEL_PUNIT_IPC_H_
0004
0005 /*
0006  * Three types of 8bit P-Unit IPC commands are supported,
0007  * bit[7:6]: [00]: BIOS; [01]: GTD; [10]: ISPD.
0008  */
0009 typedef enum {
0010     BIOS_IPC = 0,
0011     GTDRIVER_IPC,
0012     ISPDRIVER_IPC,
0013     RESERVED_IPC,
0014 } IPC_TYPE;
0015
0016 #define IPC_TYPE_OFFSET         6
0017 #define IPC_PUNIT_BIOS_CMD_BASE     (BIOS_IPC << IPC_TYPE_OFFSET)
0018 #define IPC_PUNIT_GTD_CMD_BASE      (GTDDRIVER_IPC << IPC_TYPE_OFFSET)
0019 #define IPC_PUNIT_ISPD_CMD_BASE     (ISPDRIVER_IPC << IPC_TYPE_OFFSET)
0020 #define IPC_PUNIT_CMD_TYPE_MASK     (RESERVED_IPC << IPC_TYPE_OFFSET)
0021
0022 /* BIOS => Pcode commands */
0023 #define IPC_PUNIT_BIOS_ZERO         (IPC_PUNIT_BIOS_CMD_BASE | 0x00)
0024 #define IPC_PUNIT_BIOS_VR_INTERFACE     (IPC_PUNIT_BIOS_CMD_BASE | 0x01)
0025 #define IPC_PUNIT_BIOS_READ_PCS         (IPC_PUNIT_BIOS_CMD_BASE | 0x02)
0026 #define IPC_PUNIT_BIOS_WRITE_PCS        (IPC_PUNIT_BIOS_CMD_BASE | 0x03)
0027 #define IPC_PUNIT_BIOS_READ_PCU_CONFIG      (IPC_PUNIT_BIOS_CMD_BASE | 0x04)
0028 #define IPC_PUNIT_BIOS_WRITE_PCU_CONFIG     (IPC_PUNIT_BIOS_CMD_BASE | 0x05)
0029 #define IPC_PUNIT_BIOS_READ_PL1_SETTING     (IPC_PUNIT_BIOS_CMD_BASE | 0x06)
0030 #define IPC_PUNIT_BIOS_WRITE_PL1_SETTING    (IPC_PUNIT_BIOS_CMD_BASE | 0x07)
0031 #define IPC_PUNIT_BIOS_TRIGGER_VDD_RAM      (IPC_PUNIT_BIOS_CMD_BASE | 0x08)
0032 #define IPC_PUNIT_BIOS_READ_TELE_INFO       (IPC_PUNIT_BIOS_CMD_BASE | 0x09)
0033 #define IPC_PUNIT_BIOS_READ_TELE_TRACE_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0a)
0034 #define IPC_PUNIT_BIOS_WRITE_TELE_TRACE_CTRL    (IPC_PUNIT_BIOS_CMD_BASE | 0x0b)
0035 #define IPC_PUNIT_BIOS_READ_TELE_EVENT_CTRL (IPC_PUNIT_BIOS_CMD_BASE | 0x0c)
0036 #define IPC_PUNIT_BIOS_WRITE_TELE_EVENT_CTRL    (IPC_PUNIT_BIOS_CMD_BASE | 0x0d)
0037 #define IPC_PUNIT_BIOS_READ_TELE_TRACE      (IPC_PUNIT_BIOS_CMD_BASE | 0x0e)
0038 #define IPC_PUNIT_BIOS_WRITE_TELE_TRACE     (IPC_PUNIT_BIOS_CMD_BASE | 0x0f)
0039 #define IPC_PUNIT_BIOS_READ_TELE_EVENT      (IPC_PUNIT_BIOS_CMD_BASE | 0x10)
0040 #define IPC_PUNIT_BIOS_WRITE_TELE_EVENT     (IPC_PUNIT_BIOS_CMD_BASE | 0x11)
0041 #define IPC_PUNIT_BIOS_READ_MODULE_TEMP     (IPC_PUNIT_BIOS_CMD_BASE | 0x12)
0042 #define IPC_PUNIT_BIOS_RESERVED         (IPC_PUNIT_BIOS_CMD_BASE | 0x13)
0043 #define IPC_PUNIT_BIOS_READ_VOLTAGE_OVER    (IPC_PUNIT_BIOS_CMD_BASE | 0x14)
0044 #define IPC_PUNIT_BIOS_WRITE_VOLTAGE_OVER   (IPC_PUNIT_BIOS_CMD_BASE | 0x15)
0045 #define IPC_PUNIT_BIOS_READ_RATIO_OVER      (IPC_PUNIT_BIOS_CMD_BASE | 0x16)
0046 #define IPC_PUNIT_BIOS_WRITE_RATIO_OVER     (IPC_PUNIT_BIOS_CMD_BASE | 0x17)
0047 #define IPC_PUNIT_BIOS_READ_VF_GL_CTRL      (IPC_PUNIT_BIOS_CMD_BASE | 0x18)
0048 #define IPC_PUNIT_BIOS_WRITE_VF_GL_CTRL     (IPC_PUNIT_BIOS_CMD_BASE | 0x19)
0049 #define IPC_PUNIT_BIOS_READ_FM_SOC_TEMP_THRESH  (IPC_PUNIT_BIOS_CMD_BASE | 0x1a)
0050 #define IPC_PUNIT_BIOS_WRITE_FM_SOC_TEMP_THRESH (IPC_PUNIT_BIOS_CMD_BASE | 0x1b)
0051
0052 /* GT Driver => Pcode commands */
0053 #define IPC_PUNIT_GTD_ZERO          (IPC_PUNIT_GTD_CMD_BASE | 0x00)
0054 #define IPC_PUNIT_GTD_CONFIG            (IPC_PUNIT_GTD_CMD_BASE | 0x01)
0055 #define IPC_PUNIT_GTD_READ_ICCP_LIC_CDYN_SCAL   (IPC_PUNIT_GTD_CMD_BASE | 0x02)
0056 #define IPC_PUNIT_GTD_WRITE_ICCP_LIC_CDYN_SCAL  (IPC_PUNIT_GTD_CMD_BASE | 0x03)
0057 #define IPC_PUNIT_GTD_GET_WM_VAL        (IPC_PUNIT_GTD_CMD_BASE | 0x06)
0058 #define IPC_PUNIT_GTD_WRITE_CONFIG_WISHREQ  (IPC_PUNIT_GTD_CMD_BASE | 0x07)
0059 #define IPC_PUNIT_GTD_READ_REQ_DUTY_CYCLE   (IPC_PUNIT_GTD_CMD_BASE | 0x16)
0060 #define IPC_PUNIT_GTD_DIS_VOL_FREQ_CHG_REQUEST  (IPC_PUNIT_GTD_CMD_BASE | 0x17)
0061 #define IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_CTRL  (IPC_PUNIT_GTD_CMD_BASE | 0x1a)
0062 #define IPC_PUNIT_GTD_DYNA_DUTY_CYCLE_TUNING    (IPC_PUNIT_GTD_CMD_BASE | 0x1c)
0063
0064 /* ISP Driver => Pcode commands */
0065 #define IPC_PUNIT_ISPD_ZERO         (IPC_PUNIT_ISPD_CMD_BASE | 0x00)
0066 #define IPC_PUNIT_ISPD_CONFIG           (IPC_PUNIT_ISPD_CMD_BASE | 0x01)
0067 #define IPC_PUNIT_ISPD_GET_ISP_LTR_VAL      (IPC_PUNIT_ISPD_CMD_BASE | 0x02)
0068 #define IPC_PUNIT_ISPD_ACCESS_IU_FREQ_BOUNDS    (IPC_PUNIT_ISPD_CMD_BASE | 0x03)
0069 #define IPC_PUNIT_ISPD_READ_CDYN_LEVEL      (IPC_PUNIT_ISPD_CMD_BASE | 0x04)
0070 #define IPC_PUNIT_ISPD_WRITE_CDYN_LEVEL     (IPC_PUNIT_ISPD_CMD_BASE | 0x05)
0071
0072 /* Error codes */
0073 #define IPC_PUNIT_ERR_SUCCESS           0
0074 #define IPC_PUNIT_ERR_INVALID_CMD       1
0075 #define IPC_PUNIT_ERR_INVALID_PARAMETER     2
0076 #define IPC_PUNIT_ERR_CMD_TIMEOUT       3
0077 #define IPC_PUNIT_ERR_CMD_LOCKED        4
0078 #define IPC_PUNIT_ERR_INVALID_VR_ID     5
0079 #define IPC_PUNIT_ERR_VR_ERR            6
0080
0081 #if IS_ENABLED(CONFIG_INTEL_PUNIT_IPC)
0082
0083 int intel_punit_ipc_simple_command(int cmd, int para1, int para2);
0084 int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out);
0085
0086 #else
0087
0088 static inline int intel_punit_ipc_simple_command(int cmd,
0089                           int para1, int para2)
0090 {
0091     return -ENODEV;
0092 }
0093
0094 static inline int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2,
0095                       u32 *in, u32 *out)
0096 {
0097     return -ENODEV;
0098 }
0099
0100 #endif /* CONFIG_INTEL_PUNIT_IPC */
0101
0102 #endif