include/asm/intel_pt.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_INTEL_PT_H
0003 #define _ASM_X86_INTEL_PT_H
0004
0005 #define PT_CPUID_LEAVES     2
0006 #define PT_CPUID_REGS_NUM   4 /* number of registers (eax, ebx, ecx, edx) */
0007
0008 enum pt_capabilities {
0009     PT_CAP_max_subleaf = 0,
0010     PT_CAP_cr3_filtering,
0011     PT_CAP_psb_cyc,
0012     PT_CAP_ip_filtering,
0013     PT_CAP_mtc,
0014     PT_CAP_ptwrite,
0015     PT_CAP_power_event_trace,
0016     PT_CAP_event_trace,
0017     PT_CAP_tnt_disable,
0018     PT_CAP_topa_output,
0019     PT_CAP_topa_multiple_entries,
0020     PT_CAP_single_range_output,
0021     PT_CAP_output_subsys,
0022     PT_CAP_payloads_lip,
0023     PT_CAP_num_address_ranges,
0024     PT_CAP_mtc_periods,
0025     PT_CAP_cycle_thresholds,
0026     PT_CAP_psb_periods,
0027 };
0028
0029 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_INTEL)
0030 void cpu_emergency_stop_pt(void);
0031 extern u32 intel_pt_validate_hw_cap(enum pt_capabilities cap);
0032 extern u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities cap);
0033 extern int is_intel_pt_event(struct perf_event *event);
0034 #else
0035 static inline void cpu_emergency_stop_pt(void) {}
0036 static inline u32 intel_pt_validate_hw_cap(enum pt_capabilities cap) { return 0; }
0037 static inline u32 intel_pt_validate_cap(u32 *caps, enum pt_capabilities capability) { return 0; }
0038 static inline int is_intel_pt_event(struct perf_event *event) { return 0; }
0039 #endif
0040
0041 #endif /* _ASM_X86_INTEL_PT_H */