include/asm/intel_ds.h

0001 #ifndef _ASM_INTEL_DS_H
0002 #define _ASM_INTEL_DS_H
0003
0004 #include <linux/percpu-defs.h>
0005
0006 #define BTS_BUFFER_SIZE     (PAGE_SIZE << 4)
0007 #define PEBS_BUFFER_SIZE    (PAGE_SIZE << 4)
0008
0009 /* The maximal number of PEBS events: */
0010 #define MAX_PEBS_EVENTS_FMT4    8
0011 #define MAX_PEBS_EVENTS     32
0012 #define MAX_FIXED_PEBS_EVENTS   16
0013
0014 /*
0015  * A debug store configuration.
0016  *
0017  * We only support architectures that use 64bit fields.
0018  */
0019 struct debug_store {
0020     u64 bts_buffer_base;
0021     u64 bts_index;
0022     u64 bts_absolute_maximum;
0023     u64 bts_interrupt_threshold;
0024     u64 pebs_buffer_base;
0025     u64 pebs_index;
0026     u64 pebs_absolute_maximum;
0027     u64 pebs_interrupt_threshold;
0028     u64 pebs_event_reset[MAX_PEBS_EVENTS + MAX_FIXED_PEBS_EVENTS];
0029 } __aligned(PAGE_SIZE);
0030
0031 DECLARE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
0032
0033 struct debug_store_buffers {
0034     char    bts_buffer[BTS_BUFFER_SIZE];
0035     char    pebs_buffer[PEBS_BUFFER_SIZE];
0036 };
0037
0038 #endif