include/asm/intel-family.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_INTEL_FAMILY_H
0003 #define _ASM_X86_INTEL_FAMILY_H
0004
0005 /*
0006  * "Big Core" Processors (Branded as Core, Xeon, etc...)
0007  *
0008  * While adding a new CPUID for a new microarchitecture, add a new
0009  * group to keep logically sorted out in chronological order. Within
0010  * that group keep the CPUID for the variants sorted by model number.
0011  *
0012  * The defined symbol names have the following form:
0013  *  INTEL_FAM6{OPTFAMILY}_{MICROARCH}{OPTDIFF}
0014  * where:
0015  * OPTFAMILY    Describes the family of CPUs that this belongs to. Default
0016  *      is assumed to be "_CORE" (and should be omitted). Other values
0017  *      currently in use are _ATOM and _XEON_PHI
0018  * MICROARCH    Is the code name for the micro-architecture for this core.
0019  *      N.B. Not the platform name.
0020  * OPTDIFF  If needed, a short string to differentiate by market segment.
0021  *
0022  *      Common OPTDIFFs:
0023  *
0024  *          - regular client parts
0025  *      _L  - regular mobile parts
0026  *      _G  - parts with extra graphics on
0027  *      _X  - regular server parts
0028  *      _D  - micro server parts
0029  *      _N,_P   - other mobile parts
0030  *      _S  - other client parts
0031  *
0032  *      Historical OPTDIFFs:
0033  *
0034  *      _EP - 2 socket server parts
0035  *      _EX - 4+ socket server parts
0036  *
0037  * The #define line may optionally include a comment including platform or core
0038  * names. An exception is made for skylake/kabylake where steppings seem to have gotten
0039  * their own names :-(
0040  */
0041
0042 /* Wildcard match for FAM6 so X86_MATCH_INTEL_FAM6_MODEL(ANY) works */
0043 #define INTEL_FAM6_ANY          X86_MODEL_ANY
0044
0045 #define INTEL_FAM6_CORE_YONAH       0x0E
0046
0047 #define INTEL_FAM6_CORE2_MEROM      0x0F
0048 #define INTEL_FAM6_CORE2_MEROM_L    0x16
0049 #define INTEL_FAM6_CORE2_PENRYN     0x17
0050 #define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
0051
0052 #define INTEL_FAM6_NEHALEM      0x1E
0053 #define INTEL_FAM6_NEHALEM_G        0x1F /* Auburndale / Havendale */
0054 #define INTEL_FAM6_NEHALEM_EP       0x1A
0055 #define INTEL_FAM6_NEHALEM_EX       0x2E
0056
0057 #define INTEL_FAM6_WESTMERE     0x25
0058 #define INTEL_FAM6_WESTMERE_EP      0x2C
0059 #define INTEL_FAM6_WESTMERE_EX      0x2F
0060
0061 #define INTEL_FAM6_SANDYBRIDGE      0x2A
0062 #define INTEL_FAM6_SANDYBRIDGE_X    0x2D
0063 #define INTEL_FAM6_IVYBRIDGE        0x3A
0064 #define INTEL_FAM6_IVYBRIDGE_X      0x3E
0065
0066 #define INTEL_FAM6_HASWELL      0x3C
0067 #define INTEL_FAM6_HASWELL_X        0x3F
0068 #define INTEL_FAM6_HASWELL_L        0x45
0069 #define INTEL_FAM6_HASWELL_G        0x46
0070
0071 #define INTEL_FAM6_BROADWELL        0x3D
0072 #define INTEL_FAM6_BROADWELL_G      0x47
0073 #define INTEL_FAM6_BROADWELL_X      0x4F
0074 #define INTEL_FAM6_BROADWELL_D      0x56
0075
0076 #define INTEL_FAM6_SKYLAKE_L        0x4E    /* Sky Lake             */
0077 #define INTEL_FAM6_SKYLAKE      0x5E    /* Sky Lake             */
0078 #define INTEL_FAM6_SKYLAKE_X        0x55    /* Sky Lake             */
0079 /*                 CASCADELAKE_X    0x55       Sky Lake -- s: 7     */
0080 /*                 COOPERLAKE_X     0x55       Sky Lake -- s: 11    */
0081
0082 #define INTEL_FAM6_KABYLAKE_L       0x8E    /* Sky Lake             */
0083 /*                 AMBERLAKE_L      0x8E       Sky Lake -- s: 9     */
0084 /*                 COFFEELAKE_L     0x8E       Sky Lake -- s: 10    */
0085 /*                 WHISKEYLAKE_L    0x8E       Sky Lake -- s: 11,12 */
0086
0087 #define INTEL_FAM6_KABYLAKE     0x9E    /* Sky Lake             */
0088 /*                 COFFEELAKE       0x9E       Sky Lake -- s: 10-13 */
0089
0090 #define INTEL_FAM6_COMETLAKE        0xA5    /* Sky Lake             */
0091 #define INTEL_FAM6_COMETLAKE_L      0xA6    /* Sky Lake             */
0092
0093 #define INTEL_FAM6_CANNONLAKE_L     0x66    /* Palm Cove */
0094
0095 #define INTEL_FAM6_ICELAKE_X        0x6A    /* Sunny Cove */
0096 #define INTEL_FAM6_ICELAKE_D        0x6C    /* Sunny Cove */
0097 #define INTEL_FAM6_ICELAKE      0x7D    /* Sunny Cove */
0098 #define INTEL_FAM6_ICELAKE_L        0x7E    /* Sunny Cove */
0099 #define INTEL_FAM6_ICELAKE_NNPI     0x9D    /* Sunny Cove */
0100
0101 #define INTEL_FAM6_LAKEFIELD        0x8A    /* Sunny Cove / Tremont */
0102
0103 #define INTEL_FAM6_ROCKETLAKE       0xA7    /* Cypress Cove */
0104
0105 #define INTEL_FAM6_TIGERLAKE_L      0x8C    /* Willow Cove */
0106 #define INTEL_FAM6_TIGERLAKE        0x8D    /* Willow Cove */
0107
0108 #define INTEL_FAM6_SAPPHIRERAPIDS_X 0x8F    /* Golden Cove */
0109
0110 #define INTEL_FAM6_ALDERLAKE        0x97    /* Golden Cove / Gracemont */
0111 #define INTEL_FAM6_ALDERLAKE_L      0x9A    /* Golden Cove / Gracemont */
0112 #define INTEL_FAM6_ALDERLAKE_N      0xBE
0113
0114 #define INTEL_FAM6_RAPTORLAKE       0xB7
0115 #define INTEL_FAM6_RAPTORLAKE_P     0xBA
0116 #define INTEL_FAM6_RAPTORLAKE_S     0xBF
0117
0118 #define INTEL_FAM6_METEORLAKE       0xAC
0119 #define INTEL_FAM6_METEORLAKE_L     0xAA
0120
0121 /* "Small Core" Processors (Atom) */
0122
0123 #define INTEL_FAM6_ATOM_BONNELL     0x1C /* Diamondville, Pineview */
0124 #define INTEL_FAM6_ATOM_BONNELL_MID 0x26 /* Silverthorne, Lincroft */
0125
0126 #define INTEL_FAM6_ATOM_SALTWELL    0x36 /* Cedarview */
0127 #define INTEL_FAM6_ATOM_SALTWELL_MID    0x27 /* Penwell */
0128 #define INTEL_FAM6_ATOM_SALTWELL_TABLET 0x35 /* Cloverview */
0129
0130 #define INTEL_FAM6_ATOM_SILVERMONT  0x37 /* Bay Trail, Valleyview */
0131 #define INTEL_FAM6_ATOM_SILVERMONT_D    0x4D /* Avaton, Rangely */
0132 #define INTEL_FAM6_ATOM_SILVERMONT_MID  0x4A /* Merriefield */
0133
0134 #define INTEL_FAM6_ATOM_AIRMONT     0x4C /* Cherry Trail, Braswell */
0135 #define INTEL_FAM6_ATOM_AIRMONT_MID 0x5A /* Moorefield */
0136 #define INTEL_FAM6_ATOM_AIRMONT_NP  0x75 /* Lightning Mountain */
0137
0138 #define INTEL_FAM6_ATOM_GOLDMONT    0x5C /* Apollo Lake */
0139 #define INTEL_FAM6_ATOM_GOLDMONT_D  0x5F /* Denverton */
0140
0141 /* Note: the micro-architecture is "Goldmont Plus" */
0142 #define INTEL_FAM6_ATOM_GOLDMONT_PLUS   0x7A /* Gemini Lake */
0143
0144 #define INTEL_FAM6_ATOM_TREMONT_D   0x86 /* Jacobsville */
0145 #define INTEL_FAM6_ATOM_TREMONT     0x96 /* Elkhart Lake */
0146 #define INTEL_FAM6_ATOM_TREMONT_L   0x9C /* Jasper Lake */
0147
0148 /* Xeon Phi */
0149
0150 #define INTEL_FAM6_XEON_PHI_KNL     0x57 /* Knights Landing */
0151 #define INTEL_FAM6_XEON_PHI_KNM     0x85 /* Knights Mill */
0152
0153 /* Family 5 */
0154 #define INTEL_FAM5_QUARK_X1000      0x09 /* Quark X1000 SoC */
0155
0156 #endif /* _ASM_X86_INTEL_FAMILY_H */