include/asm/gart.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_GART_H
0003 #define _ASM_X86_GART_H
0004
0005 #include <asm/e820/api.h>
0006
0007 extern void set_up_gart_resume(u32, u32);
0008
0009 extern int fallback_aper_order;
0010 extern int fallback_aper_force;
0011 extern int fix_aperture;
0012
0013 /* PTE bits. */
0014 #define GPTE_VALID  1
0015 #define GPTE_COHERENT   2
0016
0017 /* Aperture control register bits. */
0018 #define GARTEN      (1<<0)
0019 #define DISGARTCPU  (1<<4)
0020 #define DISGARTIO   (1<<5)
0021 #define DISTLBWALKPRB   (1<<6)
0022
0023 /* GART cache control register bits. */
0024 #define INVGART     (1<<0)
0025 #define GARTPTEERR  (1<<1)
0026
0027 /* K8 On-cpu GART registers */
0028 #define AMD64_GARTAPERTURECTL   0x90
0029 #define AMD64_GARTAPERTUREBASE  0x94
0030 #define AMD64_GARTTABLEBASE 0x98
0031 #define AMD64_GARTCACHECTL  0x9c
0032
0033 #ifdef CONFIG_GART_IOMMU
0034 extern int gart_iommu_aperture;
0035 extern int gart_iommu_aperture_allowed;
0036 extern int gart_iommu_aperture_disabled;
0037
0038 extern void early_gart_iommu_check(void);
0039 extern int gart_iommu_init(void);
0040 extern void __init gart_parse_options(char *);
0041 void gart_iommu_hole_init(void);
0042
0043 #else
0044 #define gart_iommu_aperture            0
0045 #define gart_iommu_aperture_allowed    0
0046 #define gart_iommu_aperture_disabled   1
0047
0048 static inline void early_gart_iommu_check(void)
0049 {
0050 }
0051 static inline void gart_parse_options(char *options)
0052 {
0053 }
0054 static inline void gart_iommu_hole_init(void)
0055 {
0056 }
0057 #endif
0058
0059 extern int agp_amd64_init(void);
0060
0061 static inline void gart_set_size_and_enable(struct pci_dev *dev, u32 order)
0062 {
0063     u32 ctl;
0064
0065     /*
0066      * Don't enable translation but enable GART IO and CPU accesses.
0067      * Also, set DISTLBWALKPRB since GART tables memory is UC.
0068      */
0069     ctl = order << 1;
0070
0071     pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
0072 }
0073
0074 static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
0075 {
0076     u32 tmp, ctl;
0077
0078     /* address of the mappings table */
0079     addr >>= 12;
0080     tmp = (u32) addr<<4;
0081     tmp &= ~0xf;
0082     pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
0083
0084     /* Enable GART translation for this hammer. */
0085     pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
0086     ctl |= GARTEN | DISTLBWALKPRB;
0087     ctl &= ~(DISGARTCPU | DISGARTIO);
0088     pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
0089 }
0090
0091 static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
0092 {
0093     if (!aper_base)
0094         return 0;
0095
0096     if (aper_base + aper_size > 0x100000000ULL) {
0097         printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
0098         return 0;
0099     }
0100     if (e820__mapped_any(aper_base, aper_base + aper_size, E820_TYPE_RAM)) {
0101         printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
0102         return 0;
0103     }
0104     if (aper_size < min_size) {
0105         printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
0106                  aper_size>>20, min_size>>20);
0107         return 0;
0108     }
0109
0110     return 1;
0111 }
0112
0113 #endif /* _ASM_X86_GART_H */