include/asm/dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
0004  * Written by Hennus Bergman, 1992.
0005  * High DMA channel support & info by Hannu Savolainen
0006  * and John Boyd, Nov. 1992.
0007  */
0008
0009 #ifndef _ASM_X86_DMA_H
0010 #define _ASM_X86_DMA_H
0011
0012 #include <linux/spinlock.h> /* And spinlocks */
0013 #include <asm/io.h>     /* need byte IO */
0014
0015 #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
0016 #define dma_outb    outb_p
0017 #else
0018 #define dma_outb    outb
0019 #endif
0020
0021 #define dma_inb     inb
0022
0023 /*
0024  * NOTES about DMA transfers:
0025  *
0026  *  controller 1: channels 0-3, byte operations, ports 00-1F
0027  *  controller 2: channels 4-7, word operations, ports C0-DF
0028  *
0029  *  - ALL registers are 8 bits only, regardless of transfer size
0030  *  - channel 4 is not used - cascades 1 into 2.
0031  *  - channels 0-3 are byte - addresses/counts are for physical bytes
0032  *  - channels 5-7 are word - addresses/counts are for physical words
0033  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
0034  *  - transfer count loaded to registers is 1 less than actual count
0035  *  - controller 2 offsets are all even (2x offsets for controller 1)
0036  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
0037  *  - page registers for 0-3 use bit 0, represent 64K pages
0038  *
0039  * DMA transfers are limited to the lower 16MB of _physical_ memory.
0040  * Note that addresses loaded into registers must be _physical_ addresses,
0041  * not logical addresses (which may differ if paging is active).
0042  *
0043  *  Address mapping for channels 0-3:
0044  *
0045  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
0046  *    |  ...  |   |  ... |   |  ... |
0047  *    |  ...  |   |  ... |   |  ... |
0048  *    |  ...  |   |  ... |   |  ... |
0049  *   P7  ...  P0  A7 ... A0  A7 ... A0
0050  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
0051  *
0052  *  Address mapping for channels 5-7:
0053  *
0054  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
0055  *    |  ...  |   \   \   ... \  \  \  ... \  \
0056  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
0057  *    |  ...  |     \   \   ... \  \  \  ... \
0058  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
0059  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
0060  *
0061  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
0062  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
0063  * the hardware level, so odd-byte transfers aren't possible).
0064  *
0065  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
0066  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
0067  * and up to 128K bytes may be transferred on channels 5-7 in one operation.
0068  *
0069  */
0070
0071 #define MAX_DMA_CHANNELS    8
0072
0073 /* 16MB ISA DMA zone */
0074 #define MAX_DMA_PFN   ((16UL * 1024 * 1024) >> PAGE_SHIFT)
0075
0076 /* 4GB broken PCI/AGP hardware bus master zone */
0077 #define MAX_DMA32_PFN (1UL << (32 - PAGE_SHIFT))
0078
0079 #ifdef CONFIG_X86_32
0080 /* The maximum address that we can perform a DMA transfer to on this platform */
0081 #define MAX_DMA_ADDRESS      (PAGE_OFFSET + 0x1000000)
0082 #else
0083 /* Compat define for old dma zone */
0084 #define MAX_DMA_ADDRESS ((unsigned long)__va(MAX_DMA_PFN << PAGE_SHIFT))
0085 #endif
0086
0087 /* 8237 DMA controllers */
0088 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
0089 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
0090
0091 /* DMA controller registers */
0092 #define DMA1_CMD_REG        0x08    /* command register (w) */
0093 #define DMA1_STAT_REG       0x08    /* status register (r) */
0094 #define DMA1_REQ_REG        0x09    /* request register (w) */
0095 #define DMA1_MASK_REG       0x0A    /* single-channel mask (w) */
0096 #define DMA1_MODE_REG       0x0B    /* mode register (w) */
0097 #define DMA1_CLEAR_FF_REG   0x0C    /* clear pointer flip-flop (w) */
0098 #define DMA1_TEMP_REG       0x0D    /* Temporary Register (r) */
0099 #define DMA1_RESET_REG      0x0D    /* Master Clear (w) */
0100 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
0101 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
0102
0103 #define DMA2_CMD_REG        0xD0    /* command register (w) */
0104 #define DMA2_STAT_REG       0xD0    /* status register (r) */
0105 #define DMA2_REQ_REG        0xD2    /* request register (w) */
0106 #define DMA2_MASK_REG       0xD4    /* single-channel mask (w) */
0107 #define DMA2_MODE_REG       0xD6    /* mode register (w) */
0108 #define DMA2_CLEAR_FF_REG   0xD8    /* clear pointer flip-flop (w) */
0109 #define DMA2_TEMP_REG       0xDA    /* Temporary Register (r) */
0110 #define DMA2_RESET_REG      0xDA    /* Master Clear (w) */
0111 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
0112 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
0113
0114 #define DMA_ADDR_0      0x00    /* DMA address registers */
0115 #define DMA_ADDR_1      0x02
0116 #define DMA_ADDR_2      0x04
0117 #define DMA_ADDR_3      0x06
0118 #define DMA_ADDR_4      0xC0
0119 #define DMA_ADDR_5      0xC4
0120 #define DMA_ADDR_6      0xC8
0121 #define DMA_ADDR_7      0xCC
0122
0123 #define DMA_CNT_0       0x01    /* DMA count registers */
0124 #define DMA_CNT_1       0x03
0125 #define DMA_CNT_2       0x05
0126 #define DMA_CNT_3       0x07
0127 #define DMA_CNT_4       0xC2
0128 #define DMA_CNT_5       0xC6
0129 #define DMA_CNT_6       0xCA
0130 #define DMA_CNT_7       0xCE
0131
0132 #define DMA_PAGE_0      0x87    /* DMA page registers */
0133 #define DMA_PAGE_1      0x83
0134 #define DMA_PAGE_2      0x81
0135 #define DMA_PAGE_3      0x82
0136 #define DMA_PAGE_5      0x8B
0137 #define DMA_PAGE_6      0x89
0138 #define DMA_PAGE_7      0x8A
0139
0140 /* I/O to memory, no autoinit, increment, single mode */
0141 #define DMA_MODE_READ       0x44
0142 /* memory to I/O, no autoinit, increment, single mode */
0143 #define DMA_MODE_WRITE      0x48
0144 /* pass thru DREQ->HRQ, DACK<-HLDA only */
0145 #define DMA_MODE_CASCADE    0xC0
0146
0147 #define DMA_AUTOINIT        0x10
0148
0149
0150 #ifdef CONFIG_ISA_DMA_API
0151 extern spinlock_t  dma_spin_lock;
0152
0153 static inline unsigned long claim_dma_lock(void)
0154 {
0155     unsigned long flags;
0156     spin_lock_irqsave(&dma_spin_lock, flags);
0157     return flags;
0158 }
0159
0160 static inline void release_dma_lock(unsigned long flags)
0161 {
0162     spin_unlock_irqrestore(&dma_spin_lock, flags);
0163 }
0164 #endif /* CONFIG_ISA_DMA_API */
0165
0166 /* enable/disable a specific DMA channel */
0167 static inline void enable_dma(unsigned int dmanr)
0168 {
0169     if (dmanr <= 3)
0170         dma_outb(dmanr, DMA1_MASK_REG);
0171     else
0172         dma_outb(dmanr & 3, DMA2_MASK_REG);
0173 }
0174
0175 static inline void disable_dma(unsigned int dmanr)
0176 {
0177     if (dmanr <= 3)
0178         dma_outb(dmanr | 4, DMA1_MASK_REG);
0179     else
0180         dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
0181 }
0182
0183 /* Clear the 'DMA Pointer Flip Flop'.
0184  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
0185  * Use this once to initialize the FF to a known state.
0186  * After that, keep track of it. :-)
0187  * --- In order to do that, the DMA routines below should ---
0188  * --- only be used while holding the DMA lock ! ---
0189  */
0190 static inline void clear_dma_ff(unsigned int dmanr)
0191 {
0192     if (dmanr <= 3)
0193         dma_outb(0, DMA1_CLEAR_FF_REG);
0194     else
0195         dma_outb(0, DMA2_CLEAR_FF_REG);
0196 }
0197
0198 /* set mode (above) for a specific DMA channel */
0199 static inline void set_dma_mode(unsigned int dmanr, char mode)
0200 {
0201     if (dmanr <= 3)
0202         dma_outb(mode | dmanr, DMA1_MODE_REG);
0203     else
0204         dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
0205 }
0206
0207 /* Set only the page register bits of the transfer address.
0208  * This is used for successive transfers when we know the contents of
0209  * the lower 16 bits of the DMA current address register, but a 64k boundary
0210  * may have been crossed.
0211  */
0212 static inline void set_dma_page(unsigned int dmanr, char pagenr)
0213 {
0214     switch (dmanr) {
0215     case 0:
0216         dma_outb(pagenr, DMA_PAGE_0);
0217         break;
0218     case 1:
0219         dma_outb(pagenr, DMA_PAGE_1);
0220         break;
0221     case 2:
0222         dma_outb(pagenr, DMA_PAGE_2);
0223         break;
0224     case 3:
0225         dma_outb(pagenr, DMA_PAGE_3);
0226         break;
0227     case 5:
0228         dma_outb(pagenr & 0xfe, DMA_PAGE_5);
0229         break;
0230     case 6:
0231         dma_outb(pagenr & 0xfe, DMA_PAGE_6);
0232         break;
0233     case 7:
0234         dma_outb(pagenr & 0xfe, DMA_PAGE_7);
0235         break;
0236     }
0237 }
0238
0239
0240 /* Set transfer address & page bits for specific DMA channel.
0241  * Assumes dma flipflop is clear.
0242  */
0243 static inline void set_dma_addr(unsigned int dmanr, unsigned int a)
0244 {
0245     set_dma_page(dmanr, a>>16);
0246     if (dmanr <= 3)  {
0247         dma_outb(a & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
0248         dma_outb((a >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
0249     }  else  {
0250         dma_outb((a >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
0251         dma_outb((a >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
0252     }
0253 }
0254
0255
0256 /* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
0257  * a specific DMA channel.
0258  * You must ensure the parameters are valid.
0259  * NOTE: from a manual: "the number of transfers is one more
0260  * than the initial word count"! This is taken into account.
0261  * Assumes dma flip-flop is clear.
0262  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
0263  */
0264 static inline void set_dma_count(unsigned int dmanr, unsigned int count)
0265 {
0266     count--;
0267     if (dmanr <= 3)  {
0268         dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
0269         dma_outb((count >> 8) & 0xff,
0270              ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
0271     } else {
0272         dma_outb((count >> 1) & 0xff,
0273              ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
0274         dma_outb((count >> 9) & 0xff,
0275              ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
0276     }
0277 }
0278
0279
0280 /* Get DMA residue count. After a DMA transfer, this
0281  * should return zero. Reading this while a DMA transfer is
0282  * still in progress will return unpredictable results.
0283  * If called before the channel has been used, it may return 1.
0284  * Otherwise, it returns the number of _bytes_ left to transfer.
0285  *
0286  * Assumes DMA flip-flop is clear.
0287  */
0288 static inline int get_dma_residue(unsigned int dmanr)
0289 {
0290     unsigned int io_port;
0291     /* using short to get 16-bit wrap around */
0292     unsigned short count;
0293
0294     io_port = (dmanr <= 3) ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
0295         : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
0296
0297     count = 1 + dma_inb(io_port);
0298     count += dma_inb(io_port) << 8;
0299
0300     return (dmanr <= 3) ? count : (count << 1);
0301 }
0302
0303
0304 /* These are in kernel/dma.c because x86 uses CONFIG_GENERIC_ISA_DMA */
0305 #ifdef CONFIG_ISA_DMA_API
0306 extern int request_dma(unsigned int dmanr, const char *device_id);
0307 extern void free_dma(unsigned int dmanr);
0308 #endif
0309
0310 #endif /* _ASM_X86_DMA_H */