include/asm/apicdef.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_APICDEF_H
0003 #define _ASM_X86_APICDEF_H
0004
0005 /*
0006  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
0007  *
0008  * Alan Cox <Alan.Cox@linux.org>, 1995.
0009  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
0010  */
0011
0012 #define IO_APIC_DEFAULT_PHYS_BASE   0xfec00000
0013 #define APIC_DEFAULT_PHYS_BASE      0xfee00000
0014
0015 /*
0016  * This is the IO-APIC register space as specified
0017  * by Intel docs:
0018  */
0019 #define IO_APIC_SLOT_SIZE       1024
0020
0021 #define APIC_ID     0x20
0022
0023 #define APIC_LVR    0x30
0024 #define     APIC_LVR_MASK       0xFF00FF
0025 #define     APIC_LVR_DIRECTED_EOI   (1 << 24)
0026 #define     GET_APIC_VERSION(x) ((x) & 0xFFu)
0027 #define     GET_APIC_MAXLVT(x)  (((x) >> 16) & 0xFFu)
0028 #ifdef CONFIG_X86_32
0029 #  define   APIC_INTEGRATED(x)  ((x) & 0xF0u)
0030 #else
0031 #  define   APIC_INTEGRATED(x)  (1)
0032 #endif
0033 #define     APIC_XAPIC(x)       ((x) >= 0x14)
0034 #define     APIC_EXT_SPACE(x)   ((x) & 0x80000000)
0035 #define APIC_TASKPRI    0x80
0036 #define     APIC_TPRI_MASK      0xFFu
0037 #define APIC_ARBPRI 0x90
0038 #define     APIC_ARBPRI_MASK    0xFFu
0039 #define APIC_PROCPRI    0xA0
0040 #define APIC_EOI    0xB0
0041 #define     APIC_EOI_ACK        0x0 /* Docs say 0 for future compat. */
0042 #define APIC_RRR    0xC0
0043 #define APIC_LDR    0xD0
0044 #define     APIC_LDR_MASK       (0xFFu << 24)
0045 #define     GET_APIC_LOGICAL_ID(x)  (((x) >> 24) & 0xFFu)
0046 #define     SET_APIC_LOGICAL_ID(x)  (((x) << 24))
0047 #define     APIC_ALL_CPUS       0xFFu
0048 #define APIC_DFR    0xE0
0049 #define     APIC_DFR_CLUSTER        0x0FFFFFFFul
0050 #define     APIC_DFR_FLAT           0xFFFFFFFFul
0051 #define APIC_SPIV   0xF0
0052 #define     APIC_SPIV_DIRECTED_EOI      (1 << 12)
0053 #define     APIC_SPIV_FOCUS_DISABLED    (1 << 9)
0054 #define     APIC_SPIV_APIC_ENABLED      (1 << 8)
0055 #define APIC_ISR    0x100
0056 #define APIC_ISR_NR     0x8     /* Number of 32 bit ISR registers. */
0057 #define APIC_TMR    0x180
0058 #define APIC_IRR    0x200
0059 #define APIC_ESR    0x280
0060 #define     APIC_ESR_SEND_CS    0x00001
0061 #define     APIC_ESR_RECV_CS    0x00002
0062 #define     APIC_ESR_SEND_ACC   0x00004
0063 #define     APIC_ESR_RECV_ACC   0x00008
0064 #define     APIC_ESR_SENDILL    0x00020
0065 #define     APIC_ESR_RECVILL    0x00040
0066 #define     APIC_ESR_ILLREGA    0x00080
0067 #define     APIC_LVTCMCI    0x2f0
0068 #define APIC_ICR    0x300
0069 #define     APIC_DEST_SELF      0x40000
0070 #define     APIC_DEST_ALLINC    0x80000
0071 #define     APIC_DEST_ALLBUT    0xC0000
0072 #define     APIC_ICR_RR_MASK    0x30000
0073 #define     APIC_ICR_RR_INVALID 0x00000
0074 #define     APIC_ICR_RR_INPROG  0x10000
0075 #define     APIC_ICR_RR_VALID   0x20000
0076 #define     APIC_INT_LEVELTRIG  0x08000
0077 #define     APIC_INT_ASSERT     0x04000
0078 #define     APIC_ICR_BUSY       0x01000
0079 #define     APIC_DEST_LOGICAL   0x00800
0080 #define     APIC_DEST_PHYSICAL  0x00000
0081 #define     APIC_DM_FIXED       0x00000
0082 #define     APIC_DM_FIXED_MASK  0x00700
0083 #define     APIC_DM_LOWEST      0x00100
0084 #define     APIC_DM_SMI     0x00200
0085 #define     APIC_DM_REMRD       0x00300
0086 #define     APIC_DM_NMI     0x00400
0087 #define     APIC_DM_INIT        0x00500
0088 #define     APIC_DM_STARTUP     0x00600
0089 #define     APIC_DM_EXTINT      0x00700
0090 #define     APIC_VECTOR_MASK    0x000FF
0091 #define APIC_ICR2   0x310
0092 #define     GET_XAPIC_DEST_FIELD(x) (((x) >> 24) & 0xFF)
0093 #define     SET_XAPIC_DEST_FIELD(x) ((x) << 24)
0094 #define APIC_LVTT   0x320
0095 #define APIC_LVTTHMR    0x330
0096 #define APIC_LVTPC  0x340
0097 #define APIC_LVT0   0x350
0098 #define     APIC_LVT_TIMER_ONESHOT      (0 << 17)
0099 #define     APIC_LVT_TIMER_PERIODIC     (1 << 17)
0100 #define     APIC_LVT_TIMER_TSCDEADLINE  (2 << 17)
0101 #define     APIC_LVT_MASKED         (1 << 16)
0102 #define     APIC_LVT_LEVEL_TRIGGER      (1 << 15)
0103 #define     APIC_LVT_REMOTE_IRR     (1 << 14)
0104 #define     APIC_INPUT_POLARITY     (1 << 13)
0105 #define     APIC_SEND_PENDING       (1 << 12)
0106 #define     APIC_MODE_MASK          0x700
0107 #define     GET_APIC_DELIVERY_MODE(x)   (((x) >> 8) & 0x7)
0108 #define     SET_APIC_DELIVERY_MODE(x, y)    (((x) & ~0x700) | ((y) << 8))
0109 #define         APIC_MODE_FIXED     0x0
0110 #define         APIC_MODE_NMI       0x4
0111 #define         APIC_MODE_EXTINT    0x7
0112 #define APIC_LVT1   0x360
0113 #define APIC_LVTERR 0x370
0114 #define APIC_TMICT  0x380
0115 #define APIC_TMCCT  0x390
0116 #define APIC_TDCR   0x3E0
0117 #define APIC_SELF_IPI   0x3F0
0118 #define     APIC_TDR_DIV_TMBASE (1 << 2)
0119 #define     APIC_TDR_DIV_1      0xB
0120 #define     APIC_TDR_DIV_2      0x0
0121 #define     APIC_TDR_DIV_4      0x1
0122 #define     APIC_TDR_DIV_8      0x2
0123 #define     APIC_TDR_DIV_16     0x3
0124 #define     APIC_TDR_DIV_32     0x8
0125 #define     APIC_TDR_DIV_64     0x9
0126 #define     APIC_TDR_DIV_128    0xA
0127 #define APIC_EFEAT  0x400
0128 #define APIC_ECTRL  0x410
0129 #define APIC_EILVTn(n)  (0x500 + 0x10 * n)
0130 #define     APIC_EILVT_NR_AMD_K8    1   /* # of extended interrupts */
0131 #define     APIC_EILVT_NR_AMD_10H   4
0132 #define     APIC_EILVT_NR_MAX   APIC_EILVT_NR_AMD_10H
0133 #define     APIC_EILVT_LVTOFF(x)    (((x) >> 4) & 0xF)
0134 #define     APIC_EILVT_MSG_FIX  0x0
0135 #define     APIC_EILVT_MSG_SMI  0x2
0136 #define     APIC_EILVT_MSG_NMI  0x4
0137 #define     APIC_EILVT_MSG_EXT  0x7
0138 #define     APIC_EILVT_MASKED   (1 << 16)
0139
0140 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
0141 #define APIC_BASE_MSR   0x800
0142 #define XAPIC_ENABLE    (1UL << 11)
0143 #define X2APIC_ENABLE   (1UL << 10)
0144
0145 #ifdef CONFIG_X86_32
0146 # define MAX_IO_APICS 64
0147 # define MAX_LOCAL_APIC 256
0148 #else
0149 # define MAX_IO_APICS 128
0150 # define MAX_LOCAL_APIC 32768
0151 #endif
0152
0153 /*
0154  * All x86-64 systems are xAPIC compatible.
0155  * In the following, "apicid" is a physical APIC ID.
0156  */
0157 #define XAPIC_DEST_CPUS_SHIFT   4
0158 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
0159 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
0160 #define APIC_CLUSTER(apicid)    ((apicid) & XAPIC_DEST_CLUSTER_MASK)
0161 #define APIC_CLUSTERID(apicid)  (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT)
0162 #define APIC_CPUID(apicid)  ((apicid) & XAPIC_DEST_CPUS_MASK)
0163 #define NUM_APIC_CLUSTERS   ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
0164
0165 /*
0166  * the local APIC register structure, memory mapped. Not terribly well
0167  * tested, but we might eventually use this one in the future - the
0168  * problem why we cannot use it right now is the P5 APIC, it has an
0169  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
0170  */
0171 #define u32 unsigned int
0172
0173 struct local_apic {
0174
0175 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
0176
0177 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
0178
0179 /*020*/ struct { /* APIC ID Register */
0180         u32   __reserved_1  : 24,
0181             phys_apic_id    :  4,
0182             __reserved_2    :  4;
0183         u32 __reserved[3];
0184     } id;
0185
0186 /*030*/ const
0187     struct { /* APIC Version Register */
0188         u32   version       :  8,
0189             __reserved_1    :  8,
0190             max_lvt     :  8,
0191             __reserved_2    :  8;
0192         u32 __reserved[3];
0193     } version;
0194
0195 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
0196
0197 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
0198
0199 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
0200
0201 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
0202
0203 /*080*/ struct { /* Task Priority Register */
0204         u32   priority  :  8,
0205             __reserved_1    : 24;
0206         u32 __reserved_2[3];
0207     } tpr;
0208
0209 /*090*/ const
0210     struct { /* Arbitration Priority Register */
0211         u32   priority  :  8,
0212             __reserved_1    : 24;
0213         u32 __reserved_2[3];
0214     } apr;
0215
0216 /*0A0*/ const
0217     struct { /* Processor Priority Register */
0218         u32   priority  :  8,
0219             __reserved_1    : 24;
0220         u32 __reserved_2[3];
0221     } ppr;
0222
0223 /*0B0*/ struct { /* End Of Interrupt Register */
0224         u32   eoi;
0225         u32 __reserved[3];
0226     } eoi;
0227
0228 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
0229
0230 /*0D0*/ struct { /* Logical Destination Register */
0231         u32   __reserved_1  : 24,
0232             logical_dest    :  8;
0233         u32 __reserved_2[3];
0234     } ldr;
0235
0236 /*0E0*/ struct { /* Destination Format Register */
0237         u32   __reserved_1  : 28,
0238             model       :  4;
0239         u32 __reserved_2[3];
0240     } dfr;
0241
0242 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
0243         u32 spurious_vector :  8,
0244             apic_enabled    :  1,
0245             focus_cpu   :  1,
0246             __reserved_2    : 22;
0247         u32 __reserved_3[3];
0248     } svr;
0249
0250 /*100*/ struct { /* In Service Register */
0251 /*170*/     u32 bitfield;
0252         u32 __reserved[3];
0253     } isr [8];
0254
0255 /*180*/ struct { /* Trigger Mode Register */
0256 /*1F0*/     u32 bitfield;
0257         u32 __reserved[3];
0258     } tmr [8];
0259
0260 /*200*/ struct { /* Interrupt Request Register */
0261 /*270*/     u32 bitfield;
0262         u32 __reserved[3];
0263     } irr [8];
0264
0265 /*280*/ union { /* Error Status Register */
0266         struct {
0267             u32   send_cs_error         :  1,
0268                 receive_cs_error        :  1,
0269                 send_accept_error       :  1,
0270                 receive_accept_error        :  1,
0271                 __reserved_1            :  1,
0272                 send_illegal_vector     :  1,
0273                 receive_illegal_vector      :  1,
0274                 illegal_register_address    :  1,
0275                 __reserved_2            : 24;
0276             u32 __reserved_3[3];
0277         } error_bits;
0278         struct {
0279             u32 errors;
0280             u32 __reserved_3[3];
0281         } all_errors;
0282     } esr;
0283
0284 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
0285
0286 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
0287
0288 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
0289
0290 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
0291
0292 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
0293
0294 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
0295
0296 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
0297
0298 /*300*/ struct { /* Interrupt Command Register 1 */
0299         u32   vector            :  8,
0300             delivery_mode       :  3,
0301             destination_mode    :  1,
0302             delivery_status     :  1,
0303             __reserved_1        :  1,
0304             level           :  1,
0305             trigger         :  1,
0306             __reserved_2        :  2,
0307             shorthand       :  2,
0308             __reserved_3        :  12;
0309         u32 __reserved_4[3];
0310     } icr1;
0311
0312 /*310*/ struct { /* Interrupt Command Register 2 */
0313         union {
0314             u32   __reserved_1  : 24,
0315                 phys_dest   :  4,
0316                 __reserved_2    :  4;
0317             u32   __reserved_3  : 24,
0318                 logical_dest    :  8;
0319         } dest;
0320         u32 __reserved_4[3];
0321     } icr2;
0322
0323 /*320*/ struct { /* LVT - Timer */
0324         u32   vector        :  8,
0325             __reserved_1    :  4,
0326             delivery_status :  1,
0327             __reserved_2    :  3,
0328             mask        :  1,
0329             timer_mode  :  1,
0330             __reserved_3    : 14;
0331         u32 __reserved_4[3];
0332     } lvt_timer;
0333
0334 /*330*/ struct { /* LVT - Thermal Sensor */
0335         u32  vector     :  8,
0336             delivery_mode   :  3,
0337             __reserved_1    :  1,
0338             delivery_status :  1,
0339             __reserved_2    :  3,
0340             mask        :  1,
0341             __reserved_3    : 15;
0342         u32 __reserved_4[3];
0343     } lvt_thermal;
0344
0345 /*340*/ struct { /* LVT - Performance Counter */
0346         u32   vector        :  8,
0347             delivery_mode   :  3,
0348             __reserved_1    :  1,
0349             delivery_status :  1,
0350             __reserved_2    :  3,
0351             mask        :  1,
0352             __reserved_3    : 15;
0353         u32 __reserved_4[3];
0354     } lvt_pc;
0355
0356 /*350*/ struct { /* LVT - LINT0 */
0357         u32   vector        :  8,
0358             delivery_mode   :  3,
0359             __reserved_1    :  1,
0360             delivery_status :  1,
0361             polarity    :  1,
0362             remote_irr  :  1,
0363             trigger     :  1,
0364             mask        :  1,
0365             __reserved_2    : 15;
0366         u32 __reserved_3[3];
0367     } lvt_lint0;
0368
0369 /*360*/ struct { /* LVT - LINT1 */
0370         u32   vector        :  8,
0371             delivery_mode   :  3,
0372             __reserved_1    :  1,
0373             delivery_status :  1,
0374             polarity    :  1,
0375             remote_irr  :  1,
0376             trigger     :  1,
0377             mask        :  1,
0378             __reserved_2    : 15;
0379         u32 __reserved_3[3];
0380     } lvt_lint1;
0381
0382 /*370*/ struct { /* LVT - Error */
0383         u32   vector        :  8,
0384             __reserved_1    :  4,
0385             delivery_status :  1,
0386             __reserved_2    :  3,
0387             mask        :  1,
0388             __reserved_3    : 15;
0389         u32 __reserved_4[3];
0390     } lvt_error;
0391
0392 /*380*/ struct { /* Timer Initial Count Register */
0393         u32   initial_count;
0394         u32 __reserved_2[3];
0395     } timer_icr;
0396
0397 /*390*/ const
0398     struct { /* Timer Current Count Register */
0399         u32   curr_count;
0400         u32 __reserved_2[3];
0401     } timer_ccr;
0402
0403 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
0404
0405 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
0406
0407 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
0408
0409 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
0410
0411 /*3E0*/ struct { /* Timer Divide Configuration Register */
0412         u32   divisor       :  4,
0413             __reserved_1    : 28;
0414         u32 __reserved_2[3];
0415     } timer_dcr;
0416
0417 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
0418
0419 } __attribute__ ((packed));
0420
0421 #undef u32
0422
0423 #ifdef CONFIG_X86_32
0424  #define BAD_APICID 0xFFu
0425 #else
0426  #define BAD_APICID 0xFFFFu
0427 #endif
0428
0429 enum apic_delivery_modes {
0430     APIC_DELIVERY_MODE_FIXED    = 0,
0431     APIC_DELIVERY_MODE_LOWESTPRIO   = 1,
0432     APIC_DELIVERY_MODE_SMI      = 2,
0433     APIC_DELIVERY_MODE_NMI      = 4,
0434     APIC_DELIVERY_MODE_INIT     = 5,
0435     APIC_DELIVERY_MODE_EXTINT   = 7,
0436 };
0437
0438 #endif /* _ASM_X86_APICDEF_H */