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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 #ifndef _ASM_X86_APIC_H
0003 #define _ASM_X86_APIC_H
0004 
0005 #include <linux/cpumask.h>
0006 
0007 #include <asm/alternative.h>
0008 #include <asm/cpufeature.h>
0009 #include <asm/apicdef.h>
0010 #include <linux/atomic.h>
0011 #include <asm/fixmap.h>
0012 #include <asm/mpspec.h>
0013 #include <asm/msr.h>
0014 #include <asm/hardirq.h>
0015 
0016 #define ARCH_APICTIMER_STOPS_ON_C3  1
0017 
0018 /*
0019  * Debugging macros
0020  */
0021 #define APIC_QUIET   0
0022 #define APIC_VERBOSE 1
0023 #define APIC_DEBUG   2
0024 
0025 /* Macros for apic_extnmi which controls external NMI masking */
0026 #define APIC_EXTNMI_BSP     0 /* Default */
0027 #define APIC_EXTNMI_ALL     1
0028 #define APIC_EXTNMI_NONE    2
0029 
0030 /*
0031  * Define the default level of output to be very little
0032  * This can be turned up by using apic=verbose for more
0033  * information and apic=debug for _lots_ of information.
0034  * apic_verbosity is defined in apic.c
0035  */
0036 #define apic_printk(v, s, a...) do {       \
0037         if ((v) <= apic_verbosity) \
0038             printk(s, ##a);    \
0039     } while (0)
0040 
0041 
0042 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
0043 extern void generic_apic_probe(void);
0044 #else
0045 static inline void generic_apic_probe(void)
0046 {
0047 }
0048 #endif
0049 
0050 #ifdef CONFIG_X86_LOCAL_APIC
0051 
0052 extern int apic_verbosity;
0053 extern int local_apic_timer_c2_ok;
0054 
0055 extern int disable_apic;
0056 extern unsigned int lapic_timer_period;
0057 
0058 extern enum apic_intr_mode_id apic_intr_mode;
0059 enum apic_intr_mode_id {
0060     APIC_PIC,
0061     APIC_VIRTUAL_WIRE,
0062     APIC_VIRTUAL_WIRE_NO_CONFIG,
0063     APIC_SYMMETRIC_IO,
0064     APIC_SYMMETRIC_IO_NO_ROUTING
0065 };
0066 
0067 #ifdef CONFIG_SMP
0068 extern void __inquire_remote_apic(int apicid);
0069 #else /* CONFIG_SMP */
0070 static inline void __inquire_remote_apic(int apicid)
0071 {
0072 }
0073 #endif /* CONFIG_SMP */
0074 
0075 static inline void default_inquire_remote_apic(int apicid)
0076 {
0077     if (apic_verbosity >= APIC_DEBUG)
0078         __inquire_remote_apic(apicid);
0079 }
0080 
0081 /*
0082  * With 82489DX we can't rely on apic feature bit
0083  * retrieved via cpuid but still have to deal with
0084  * such an apic chip so we assume that SMP configuration
0085  * is found from MP table (64bit case uses ACPI mostly
0086  * which set smp presence flag as well so we are safe
0087  * to use this helper too).
0088  */
0089 static inline bool apic_from_smp_config(void)
0090 {
0091     return smp_found_config && !disable_apic;
0092 }
0093 
0094 /*
0095  * Basic functions accessing APICs.
0096  */
0097 #ifdef CONFIG_PARAVIRT
0098 #include <asm/paravirt.h>
0099 #endif
0100 
0101 static inline void native_apic_mem_write(u32 reg, u32 v)
0102 {
0103     volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
0104 
0105     alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
0106                ASM_OUTPUT2("=r" (v), "=m" (*addr)),
0107                ASM_OUTPUT2("0" (v), "m" (*addr)));
0108 }
0109 
0110 static inline u32 native_apic_mem_read(u32 reg)
0111 {
0112     return *((volatile u32 *)(APIC_BASE + reg));
0113 }
0114 
0115 extern void native_apic_wait_icr_idle(void);
0116 extern u32 native_safe_apic_wait_icr_idle(void);
0117 extern void native_apic_icr_write(u32 low, u32 id);
0118 extern u64 native_apic_icr_read(void);
0119 
0120 static inline bool apic_is_x2apic_enabled(void)
0121 {
0122     u64 msr;
0123 
0124     if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
0125         return false;
0126     return msr & X2APIC_ENABLE;
0127 }
0128 
0129 extern void enable_IR_x2apic(void);
0130 
0131 extern int get_physical_broadcast(void);
0132 
0133 extern int lapic_get_maxlvt(void);
0134 extern void clear_local_APIC(void);
0135 extern void disconnect_bsp_APIC(int virt_wire_setup);
0136 extern void disable_local_APIC(void);
0137 extern void apic_soft_disable(void);
0138 extern void lapic_shutdown(void);
0139 extern void sync_Arb_IDs(void);
0140 extern void init_bsp_APIC(void);
0141 extern void apic_intr_mode_select(void);
0142 extern void apic_intr_mode_init(void);
0143 extern void init_apic_mappings(void);
0144 void register_lapic_address(unsigned long address);
0145 extern void setup_boot_APIC_clock(void);
0146 extern void setup_secondary_APIC_clock(void);
0147 extern void lapic_update_tsc_freq(void);
0148 
0149 #ifdef CONFIG_X86_64
0150 static inline int apic_force_enable(unsigned long addr)
0151 {
0152     return -1;
0153 }
0154 #else
0155 extern int apic_force_enable(unsigned long addr);
0156 #endif
0157 
0158 extern void apic_ap_setup(void);
0159 
0160 /*
0161  * On 32bit this is mach-xxx local
0162  */
0163 #ifdef CONFIG_X86_64
0164 extern int apic_is_clustered_box(void);
0165 #else
0166 static inline int apic_is_clustered_box(void)
0167 {
0168     return 0;
0169 }
0170 #endif
0171 
0172 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
0173 extern void lapic_assign_system_vectors(void);
0174 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
0175 extern void lapic_update_legacy_vectors(void);
0176 extern void lapic_online(void);
0177 extern void lapic_offline(void);
0178 extern bool apic_needs_pit(void);
0179 
0180 extern void apic_send_IPI_allbutself(unsigned int vector);
0181 
0182 #else /* !CONFIG_X86_LOCAL_APIC */
0183 static inline void lapic_shutdown(void) { }
0184 #define local_apic_timer_c2_ok      1
0185 static inline void init_apic_mappings(void) { }
0186 static inline void disable_local_APIC(void) { }
0187 # define setup_boot_APIC_clock x86_init_noop
0188 # define setup_secondary_APIC_clock x86_init_noop
0189 static inline void lapic_update_tsc_freq(void) { }
0190 static inline void init_bsp_APIC(void) { }
0191 static inline void apic_intr_mode_select(void) { }
0192 static inline void apic_intr_mode_init(void) { }
0193 static inline void lapic_assign_system_vectors(void) { }
0194 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
0195 static inline bool apic_needs_pit(void) { return true; }
0196 #endif /* !CONFIG_X86_LOCAL_APIC */
0197 
0198 #ifdef CONFIG_X86_X2APIC
0199 static inline void native_apic_msr_write(u32 reg, u32 v)
0200 {
0201     if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
0202         reg == APIC_LVR)
0203         return;
0204 
0205     wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
0206 }
0207 
0208 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
0209 {
0210     __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
0211 }
0212 
0213 static inline u32 native_apic_msr_read(u32 reg)
0214 {
0215     u64 msr;
0216 
0217     if (reg == APIC_DFR)
0218         return -1;
0219 
0220     rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
0221     return (u32)msr;
0222 }
0223 
0224 static inline void native_x2apic_wait_icr_idle(void)
0225 {
0226     /* no need to wait for icr idle in x2apic */
0227     return;
0228 }
0229 
0230 static inline u32 native_safe_x2apic_wait_icr_idle(void)
0231 {
0232     /* no need to wait for icr idle in x2apic */
0233     return 0;
0234 }
0235 
0236 static inline void native_x2apic_icr_write(u32 low, u32 id)
0237 {
0238     wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
0239 }
0240 
0241 static inline u64 native_x2apic_icr_read(void)
0242 {
0243     unsigned long val;
0244 
0245     rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
0246     return val;
0247 }
0248 
0249 extern int x2apic_mode;
0250 extern int x2apic_phys;
0251 extern void __init x2apic_set_max_apicid(u32 apicid);
0252 extern void __init check_x2apic(void);
0253 extern void x2apic_setup(void);
0254 static inline int x2apic_enabled(void)
0255 {
0256     return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
0257 }
0258 
0259 #define x2apic_supported()  (boot_cpu_has(X86_FEATURE_X2APIC))
0260 #else /* !CONFIG_X86_X2APIC */
0261 static inline void check_x2apic(void) { }
0262 static inline void x2apic_setup(void) { }
0263 static inline int x2apic_enabled(void) { return 0; }
0264 
0265 #define x2apic_mode     (0)
0266 #define x2apic_supported()  (0)
0267 #endif /* !CONFIG_X86_X2APIC */
0268 
0269 struct irq_data;
0270 
0271 /*
0272  * Copyright 2004 James Cleverdon, IBM.
0273  *
0274  * Generic APIC sub-arch data struct.
0275  *
0276  * Hacked for x86-64 by James Cleverdon from i386 architecture code by
0277  * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
0278  * James Cleverdon.
0279  */
0280 struct apic {
0281     /* Hotpath functions first */
0282     void    (*eoi_write)(u32 reg, u32 v);
0283     void    (*native_eoi_write)(u32 reg, u32 v);
0284     void    (*write)(u32 reg, u32 v);
0285     u32 (*read)(u32 reg);
0286 
0287     /* IPI related functions */
0288     void    (*wait_icr_idle)(void);
0289     u32 (*safe_wait_icr_idle)(void);
0290 
0291     void    (*send_IPI)(int cpu, int vector);
0292     void    (*send_IPI_mask)(const struct cpumask *mask, int vector);
0293     void    (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
0294     void    (*send_IPI_allbutself)(int vector);
0295     void    (*send_IPI_all)(int vector);
0296     void    (*send_IPI_self)(int vector);
0297 
0298     u32 disable_esr;
0299 
0300     enum apic_delivery_modes delivery_mode;
0301     bool    dest_mode_logical;
0302 
0303     u32 (*calc_dest_apicid)(unsigned int cpu);
0304 
0305     /* ICR related functions */
0306     u64 (*icr_read)(void);
0307     void    (*icr_write)(u32 low, u32 high);
0308 
0309     /* Probe, setup and smpboot functions */
0310     int (*probe)(void);
0311     int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
0312     int (*apic_id_valid)(u32 apicid);
0313     int (*apic_id_registered)(void);
0314 
0315     bool    (*check_apicid_used)(physid_mask_t *map, int apicid);
0316     void    (*init_apic_ldr)(void);
0317     void    (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
0318     void    (*setup_apic_routing)(void);
0319     int (*cpu_present_to_apicid)(int mps_cpu);
0320     void    (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
0321     int (*check_phys_apicid_present)(int phys_apicid);
0322     int (*phys_pkg_id)(int cpuid_apic, int index_msb);
0323 
0324     u32 (*get_apic_id)(unsigned long x);
0325     u32 (*set_apic_id)(unsigned int id);
0326 
0327     /* wakeup_secondary_cpu */
0328     int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
0329     /* wakeup secondary CPU using 64-bit wakeup point */
0330     int (*wakeup_secondary_cpu_64)(int apicid, unsigned long start_eip);
0331 
0332     void    (*inquire_remote_apic)(int apicid);
0333 
0334 #ifdef CONFIG_X86_32
0335     /*
0336      * Called very early during boot from get_smp_config().  It should
0337      * return the logical apicid.  x86_[bios]_cpu_to_apicid is
0338      * initialized before this function is called.
0339      *
0340      * If logical apicid can't be determined that early, the function
0341      * may return BAD_APICID.  Logical apicid will be configured after
0342      * init_apic_ldr() while bringing up CPUs.  Note that NUMA affinity
0343      * won't be applied properly during early boot in this case.
0344      */
0345     int (*x86_32_early_logical_apicid)(int cpu);
0346 #endif
0347     char    *name;
0348 };
0349 
0350 /*
0351  * Pointer to the local APIC driver in use on this system (there's
0352  * always just one such driver in use - the kernel decides via an
0353  * early probing process which one it picks - and then sticks to it):
0354  */
0355 extern struct apic *apic;
0356 
0357 /*
0358  * APIC drivers are probed based on how they are listed in the .apicdrivers
0359  * section. So the order is important and enforced by the ordering
0360  * of different apic driver files in the Makefile.
0361  *
0362  * For the files having two apic drivers, we use apic_drivers()
0363  * to enforce the order with in them.
0364  */
0365 #define apic_driver(sym)                    \
0366     static const struct apic *__apicdrivers_##sym __used        \
0367     __aligned(sizeof(struct apic *))            \
0368     __section(".apicdrivers") = { &sym }
0369 
0370 #define apic_drivers(sym1, sym2)                    \
0371     static struct apic *__apicdrivers_##sym1##sym2[2] __used    \
0372     __aligned(sizeof(struct apic *))                \
0373     __section(".apicdrivers") = { &sym1, &sym2 }
0374 
0375 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
0376 
0377 /*
0378  * APIC functionality to boot other CPUs - only used on SMP:
0379  */
0380 #ifdef CONFIG_SMP
0381 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
0382 extern int lapic_can_unplug_cpu(void);
0383 #endif
0384 
0385 #ifdef CONFIG_X86_LOCAL_APIC
0386 
0387 static inline u32 apic_read(u32 reg)
0388 {
0389     return apic->read(reg);
0390 }
0391 
0392 static inline void apic_write(u32 reg, u32 val)
0393 {
0394     apic->write(reg, val);
0395 }
0396 
0397 static inline void apic_eoi(void)
0398 {
0399     apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
0400 }
0401 
0402 static inline u64 apic_icr_read(void)
0403 {
0404     return apic->icr_read();
0405 }
0406 
0407 static inline void apic_icr_write(u32 low, u32 high)
0408 {
0409     apic->icr_write(low, high);
0410 }
0411 
0412 static inline void apic_wait_icr_idle(void)
0413 {
0414     apic->wait_icr_idle();
0415 }
0416 
0417 static inline u32 safe_apic_wait_icr_idle(void)
0418 {
0419     return apic->safe_wait_icr_idle();
0420 }
0421 
0422 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
0423 
0424 #else /* CONFIG_X86_LOCAL_APIC */
0425 
0426 static inline u32 apic_read(u32 reg) { return 0; }
0427 static inline void apic_write(u32 reg, u32 val) { }
0428 static inline void apic_eoi(void) { }
0429 static inline u64 apic_icr_read(void) { return 0; }
0430 static inline void apic_icr_write(u32 low, u32 high) { }
0431 static inline void apic_wait_icr_idle(void) { }
0432 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
0433 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
0434 
0435 #endif /* CONFIG_X86_LOCAL_APIC */
0436 
0437 extern void apic_ack_irq(struct irq_data *data);
0438 
0439 static inline void ack_APIC_irq(void)
0440 {
0441     /*
0442      * ack_APIC_irq() actually gets compiled as a single instruction
0443      * ... yummie.
0444      */
0445     apic_eoi();
0446 }
0447 
0448 
0449 static inline bool lapic_vector_set_in_irr(unsigned int vector)
0450 {
0451     u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
0452 
0453     return !!(irr & (1U << (vector % 32)));
0454 }
0455 
0456 static inline unsigned default_get_apic_id(unsigned long x)
0457 {
0458     unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
0459 
0460     if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
0461         return (x >> 24) & 0xFF;
0462     else
0463         return (x >> 24) & 0x0F;
0464 }
0465 
0466 /*
0467  * Warm reset vector position:
0468  */
0469 #define TRAMPOLINE_PHYS_LOW     0x467
0470 #define TRAMPOLINE_PHYS_HIGH        0x469
0471 
0472 extern void generic_bigsmp_probe(void);
0473 
0474 #ifdef CONFIG_X86_LOCAL_APIC
0475 
0476 #include <asm/smp.h>
0477 
0478 #define APIC_DFR_VALUE  (APIC_DFR_FLAT)
0479 
0480 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
0481 
0482 extern struct apic apic_noop;
0483 
0484 static inline unsigned int read_apic_id(void)
0485 {
0486     unsigned int reg = apic_read(APIC_ID);
0487 
0488     return apic->get_apic_id(reg);
0489 }
0490 
0491 #ifdef CONFIG_X86_64
0492 typedef int (*wakeup_cpu_handler)(int apicid, unsigned long start_eip);
0493 extern void acpi_wake_cpu_handler_update(wakeup_cpu_handler handler);
0494 #endif
0495 
0496 extern int default_apic_id_valid(u32 apicid);
0497 extern int default_acpi_madt_oem_check(char *, char *);
0498 extern void default_setup_apic_routing(void);
0499 
0500 extern u32 apic_default_calc_apicid(unsigned int cpu);
0501 extern u32 apic_flat_calc_apicid(unsigned int cpu);
0502 
0503 extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
0504 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
0505 extern int default_cpu_present_to_apicid(int mps_cpu);
0506 extern int default_check_phys_apicid_present(int phys_apicid);
0507 
0508 #endif /* CONFIG_X86_LOCAL_APIC */
0509 
0510 #ifdef CONFIG_SMP
0511 bool apic_id_is_primary_thread(unsigned int id);
0512 void apic_smt_update(void);
0513 #else
0514 static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
0515 static inline void apic_smt_update(void) { }
0516 #endif
0517 
0518 struct msi_msg;
0519 struct irq_cfg;
0520 
0521 extern void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
0522                   bool dmar);
0523 
0524 extern void ioapic_zap_locks(void);
0525 
0526 #endif /* _ASM_X86_APIC_H */
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