include/asm/amd_nb.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_AMD_NB_H
0003 #define _ASM_X86_AMD_NB_H
0004
0005 #include <linux/ioport.h>
0006 #include <linux/pci.h>
0007 #include <linux/refcount.h>
0008
0009 struct amd_nb_bus_dev_range {
0010     u8 bus;
0011     u8 dev_base;
0012     u8 dev_limit;
0013 };
0014
0015 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
0016
0017 extern bool early_is_amd_nb(u32 value);
0018 extern struct resource *amd_get_mmconfig_range(struct resource *res);
0019 extern void amd_flush_garts(void);
0020 extern int amd_numa_init(void);
0021 extern int amd_get_subcaches(int);
0022 extern int amd_set_subcaches(int, unsigned long);
0023
0024 extern int amd_smn_read(u16 node, u32 address, u32 *value);
0025 extern int amd_smn_write(u16 node, u32 address, u32 value);
0026
0027 struct amd_l3_cache {
0028     unsigned indices;
0029     u8   subcaches[4];
0030 };
0031
0032 struct threshold_block {
0033     unsigned int     block;         /* Number within bank */
0034     unsigned int     bank;          /* MCA bank the block belongs to */
0035     unsigned int     cpu;           /* CPU which controls MCA bank */
0036     u32      address;       /* MSR address for the block */
0037     u16      interrupt_enable;  /* Enable/Disable APIC interrupt */
0038     bool         interrupt_capable; /* Bank can generate an interrupt. */
0039
0040     u16      threshold_limit;   /*
0041                          * Value upon which threshold
0042                          * interrupt is generated.
0043                          */
0044
0045     struct kobject   kobj;          /* sysfs object */
0046     struct list_head miscj;         /*
0047                          * List of threshold blocks
0048                          * within a bank.
0049                          */
0050 };
0051
0052 struct threshold_bank {
0053     struct kobject      *kobj;
0054     struct threshold_block  *blocks;
0055
0056     /* initialized to the number of CPUs on the node sharing this bank */
0057     refcount_t      cpus;
0058     unsigned int        shared;
0059 };
0060
0061 struct amd_northbridge {
0062     struct pci_dev *root;
0063     struct pci_dev *misc;
0064     struct pci_dev *link;
0065     struct amd_l3_cache l3_cache;
0066     struct threshold_bank *bank4;
0067 };
0068
0069 struct amd_northbridge_info {
0070     u16 num;
0071     u64 flags;
0072     struct amd_northbridge *nb;
0073 };
0074
0075 #define AMD_NB_GART         BIT(0)
0076 #define AMD_NB_L3_INDEX_DISABLE     BIT(1)
0077 #define AMD_NB_L3_PARTITIONING      BIT(2)
0078
0079 #ifdef CONFIG_AMD_NB
0080
0081 u16 amd_nb_num(void);
0082 bool amd_nb_has_feature(unsigned int feature);
0083 struct amd_northbridge *node_to_amd_nb(int node);
0084
0085 static inline u16 amd_pci_dev_to_node_id(struct pci_dev *pdev)
0086 {
0087     struct pci_dev *misc;
0088     int i;
0089
0090     for (i = 0; i != amd_nb_num(); i++) {
0091         misc = node_to_amd_nb(i)->misc;
0092
0093         if (pci_domain_nr(misc->bus) == pci_domain_nr(pdev->bus) &&
0094             PCI_SLOT(misc->devfn) == PCI_SLOT(pdev->devfn))
0095             return i;
0096     }
0097
0098     WARN(1, "Unable to find AMD Northbridge id for %s\n", pci_name(pdev));
0099     return 0;
0100 }
0101
0102 static inline bool amd_gart_present(void)
0103 {
0104     if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
0105         return false;
0106
0107     /* GART present only on Fam15h, upto model 0fh */
0108     if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||
0109         (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))
0110         return true;
0111
0112     return false;
0113 }
0114
0115 #else
0116
0117 #define amd_nb_num(x)       0
0118 #define amd_nb_has_feature(x)   false
0119 #define node_to_amd_nb(x)   NULL
0120 #define amd_gart_present(x) false
0121
0122 #endif
0123
0124
0125 #endif /* _ASM_X86_AMD_NB_H */