include/asm/amd-ibs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * From PPR Vol 1 for AMD Family 19h Model 01h B1
0004  * 55898 Rev 0.35 - Feb 5, 2021
0005  */
0006
0007 #include <asm/msr-index.h>
0008
0009 /*
0010  * IBS Hardware MSRs
0011  */
0012
0013 /* MSR 0xc0011030: IBS Fetch Control */
0014 union ibs_fetch_ctl {
0015     __u64 val;
0016     struct {
0017         __u64   fetch_maxcnt:16,/* 0-15: instruction fetch max. count */
0018             fetch_cnt:16,   /* 16-31: instruction fetch count */
0019             fetch_lat:16,   /* 32-47: instruction fetch latency */
0020             fetch_en:1, /* 48: instruction fetch enable */
0021             fetch_val:1,    /* 49: instruction fetch valid */
0022             fetch_comp:1,   /* 50: instruction fetch complete */
0023             ic_miss:1,  /* 51: i-cache miss */
0024             phy_addr_valid:1,/* 52: physical address valid */
0025             l1tlb_pgsz:2,   /* 53-54: i-cache L1TLB page size
0026                      *    (needs IbsPhyAddrValid) */
0027             l1tlb_miss:1,   /* 55: i-cache fetch missed in L1TLB */
0028             l2tlb_miss:1,   /* 56: i-cache fetch missed in L2TLB */
0029             rand_en:1,  /* 57: random tagging enable */
0030             fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
0031                      *      (needs IbsFetchComp) */
0032             l3_miss_only:1, /* 59: Collect L3 miss samples only */
0033             fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */
0034             fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */
0035             reserved:2; /* 62-63: reserved */
0036     };
0037 };
0038
0039 /* MSR 0xc0011033: IBS Execution Control */
0040 union ibs_op_ctl {
0041     __u64 val;
0042     struct {
0043         __u64   opmaxcnt:16,    /* 0-15: periodic op max. count */
0044             l3_miss_only:1, /* 16: Collect L3 miss samples only */
0045             op_en:1,    /* 17: op sampling enable */
0046             op_val:1,   /* 18: op sample valid */
0047             cnt_ctl:1,  /* 19: periodic op counter control */
0048             opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */
0049             reserved0:5,    /* 27-31: reserved */
0050             opcurcnt:27,    /* 32-58: periodic op counter current count */
0051             reserved1:5;    /* 59-63: reserved */
0052     };
0053 };
0054
0055 /* MSR 0xc0011035: IBS Op Data 1 */
0056 union ibs_op_data {
0057     __u64 val;
0058     struct {
0059         __u64   comp_to_ret_ctr:16, /* 0-15: op completion to retire count */
0060             tag_to_ret_ctr:16,  /* 15-31: op tag to retire count */
0061             reserved1:2,        /* 32-33: reserved */
0062             op_return:1,        /* 34: return op */
0063             op_brn_taken:1,     /* 35: taken branch op */
0064             op_brn_misp:1,      /* 36: mispredicted branch op */
0065             op_brn_ret:1,       /* 37: branch op retired */
0066             op_rip_invalid:1,   /* 38: RIP is invalid */
0067             op_brn_fuse:1,      /* 39: fused branch op */
0068             op_microcode:1,     /* 40: microcode op */
0069             reserved2:23;       /* 41-63: reserved */
0070     };
0071 };
0072
0073 /* MSR 0xc0011036: IBS Op Data 2 */
0074 union ibs_op_data2 {
0075     __u64 val;
0076     struct {
0077         __u64   data_src_lo:3,  /* 0-2: data source low */
0078             reserved0:1,    /* 3: reserved */
0079             rmt_node:1, /* 4: destination node */
0080             cache_hit_st:1, /* 5: cache hit state */
0081             data_src_hi:2,  /* 6-7: data source high */
0082             reserved1:56;   /* 8-63: reserved */
0083     };
0084 };
0085
0086 /* MSR 0xc0011037: IBS Op Data 3 */
0087 union ibs_op_data3 {
0088     __u64 val;
0089     struct {
0090         __u64   ld_op:1,            /* 0: load op */
0091             st_op:1,            /* 1: store op */
0092             dc_l1tlb_miss:1,        /* 2: data cache L1TLB miss */
0093             dc_l2tlb_miss:1,        /* 3: data cache L2TLB hit in 2M page */
0094             dc_l1tlb_hit_2m:1,      /* 4: data cache L1TLB hit in 2M page */
0095             dc_l1tlb_hit_1g:1,      /* 5: data cache L1TLB hit in 1G page */
0096             dc_l2tlb_hit_2m:1,      /* 6: data cache L2TLB hit in 2M page */
0097             dc_miss:1,          /* 7: data cache miss */
0098             dc_mis_acc:1,           /* 8: misaligned access */
0099             reserved:4,         /* 9-12: reserved */
0100             dc_wc_mem_acc:1,        /* 13: write combining memory access */
0101             dc_uc_mem_acc:1,        /* 14: uncacheable memory access */
0102             dc_locked_op:1,         /* 15: locked operation */
0103             dc_miss_no_mab_alloc:1,     /* 16: DC miss with no MAB allocated */
0104             dc_lin_addr_valid:1,        /* 17: data cache linear address valid */
0105             dc_phy_addr_valid:1,        /* 18: data cache physical address valid */
0106             dc_l2_tlb_hit_1g:1,     /* 19: data cache L2 hit in 1GB page */
0107             l2_miss:1,          /* 20: L2 cache miss */
0108             sw_pf:1,            /* 21: software prefetch */
0109             op_mem_width:4,         /* 22-25: load/store size in bytes */
0110             op_dc_miss_open_mem_reqs:6, /* 26-31: outstanding mem reqs on DC fill */
0111             dc_miss_lat:16,         /* 32-47: data cache miss latency */
0112             tlb_refill_lat:16;      /* 48-63: L1 TLB refill latency */
0113     };
0114 };
0115
0116 /* MSR 0xc001103c: IBS Fetch Control Extended */
0117 union ic_ibs_extd_ctl {
0118     __u64 val;
0119     struct {
0120         __u64   itlb_refill_lat:16, /* 0-15: ITLB Refill latency for sampled fetch */
0121             reserved:48;        /* 16-63: reserved */
0122     };
0123 };
0124
0125 /*
0126  * IBS driver related
0127  */
0128
0129 struct perf_ibs_data {
0130     u32     size;
0131     union {
0132         u32 data[0];    /* data buffer starts here */
0133         u32 caps;
0134     };
0135     u64     regs[MSR_AMD64_IBS_REG_COUNT_MAX];
0136 };