include/asm/acenv.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * X86 specific ACPICA environments and implementation
0004  *
0005  * Copyright (C) 2014, Intel Corporation
0006  *   Author: Lv Zheng <lv.zheng@intel.com>
0007  */
0008
0009 #ifndef _ASM_X86_ACENV_H
0010 #define _ASM_X86_ACENV_H
0011
0012 #include <asm/special_insns.h>
0013
0014 /* Asm macros */
0015
0016 /*
0017  * ACPI_FLUSH_CPU_CACHE() flushes caches on entering sleep states.
0018  * It is required to prevent data loss.
0019  *
0020  * While running inside virtual machine, the kernel can bypass cache flushing.
0021  * Changing sleep state in a virtual machine doesn't affect the host system
0022  * sleep state and cannot lead to data loss.
0023  */
0024 #define ACPI_FLUSH_CPU_CACHE()                  \
0025 do {                                \
0026     if (!cpu_feature_enabled(X86_FEATURE_HYPERVISOR))   \
0027         wbinvd();                   \
0028 } while (0)
0029
0030 int __acpi_acquire_global_lock(unsigned int *lock);
0031 int __acpi_release_global_lock(unsigned int *lock);
0032
0033 #define ACPI_ACQUIRE_GLOBAL_LOCK(facs, Acq) \
0034     ((Acq) = __acpi_acquire_global_lock(&facs->global_lock))
0035
0036 #define ACPI_RELEASE_GLOBAL_LOCK(facs, Acq) \
0037     ((Acq) = __acpi_release_global_lock(&facs->global_lock))
0038
0039 /*
0040  * Math helper asm macros
0041  */
0042 #define ACPI_DIV_64_BY_32(n_hi, n_lo, d32, q32, r32) \
0043     asm("divl %2;"                   \
0044         : "=a"(q32), "=d"(r32)           \
0045         : "r"(d32),                  \
0046          "0"(n_lo), "1"(n_hi))
0047
0048 #define ACPI_SHIFT_RIGHT_64(n_hi, n_lo) \
0049     asm("shrl   $1,%2   ;"  \
0050         "rcrl   $1,%3;"     \
0051         : "=r"(n_hi), "=r"(n_lo)    \
0052         : "0"(n_hi), "1"(n_lo))
0053
0054 #endif /* _ASM_X86_ACENV_H */