Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Nehalem/SandBridge/Haswell/Broadwell/Skylake uncore support */
0003 #include "uncore.h"
0004 #include "uncore_discovery.h"
0005 
0006 /* Uncore IMC PCI IDs */
0007 #define PCI_DEVICE_ID_INTEL_SNB_IMC     0x0100
0008 #define PCI_DEVICE_ID_INTEL_IVB_IMC     0x0154
0009 #define PCI_DEVICE_ID_INTEL_IVB_E3_IMC      0x0150
0010 #define PCI_DEVICE_ID_INTEL_HSW_IMC     0x0c00
0011 #define PCI_DEVICE_ID_INTEL_HSW_U_IMC       0x0a04
0012 #define PCI_DEVICE_ID_INTEL_BDW_IMC     0x1604
0013 #define PCI_DEVICE_ID_INTEL_SKL_U_IMC       0x1904
0014 #define PCI_DEVICE_ID_INTEL_SKL_Y_IMC       0x190c
0015 #define PCI_DEVICE_ID_INTEL_SKL_HD_IMC      0x1900
0016 #define PCI_DEVICE_ID_INTEL_SKL_HQ_IMC      0x1910
0017 #define PCI_DEVICE_ID_INTEL_SKL_SD_IMC      0x190f
0018 #define PCI_DEVICE_ID_INTEL_SKL_SQ_IMC      0x191f
0019 #define PCI_DEVICE_ID_INTEL_SKL_E3_IMC      0x1918
0020 #define PCI_DEVICE_ID_INTEL_KBL_Y_IMC       0x590c
0021 #define PCI_DEVICE_ID_INTEL_KBL_U_IMC       0x5904
0022 #define PCI_DEVICE_ID_INTEL_KBL_UQ_IMC      0x5914
0023 #define PCI_DEVICE_ID_INTEL_KBL_SD_IMC      0x590f
0024 #define PCI_DEVICE_ID_INTEL_KBL_SQ_IMC      0x591f
0025 #define PCI_DEVICE_ID_INTEL_KBL_HQ_IMC      0x5910
0026 #define PCI_DEVICE_ID_INTEL_KBL_WQ_IMC      0x5918
0027 #define PCI_DEVICE_ID_INTEL_CFL_2U_IMC      0x3ecc
0028 #define PCI_DEVICE_ID_INTEL_CFL_4U_IMC      0x3ed0
0029 #define PCI_DEVICE_ID_INTEL_CFL_4H_IMC      0x3e10
0030 #define PCI_DEVICE_ID_INTEL_CFL_6H_IMC      0x3ec4
0031 #define PCI_DEVICE_ID_INTEL_CFL_2S_D_IMC    0x3e0f
0032 #define PCI_DEVICE_ID_INTEL_CFL_4S_D_IMC    0x3e1f
0033 #define PCI_DEVICE_ID_INTEL_CFL_6S_D_IMC    0x3ec2
0034 #define PCI_DEVICE_ID_INTEL_CFL_8S_D_IMC    0x3e30
0035 #define PCI_DEVICE_ID_INTEL_CFL_4S_W_IMC    0x3e18
0036 #define PCI_DEVICE_ID_INTEL_CFL_6S_W_IMC    0x3ec6
0037 #define PCI_DEVICE_ID_INTEL_CFL_8S_W_IMC    0x3e31
0038 #define PCI_DEVICE_ID_INTEL_CFL_4S_S_IMC    0x3e33
0039 #define PCI_DEVICE_ID_INTEL_CFL_6S_S_IMC    0x3eca
0040 #define PCI_DEVICE_ID_INTEL_CFL_8S_S_IMC    0x3e32
0041 #define PCI_DEVICE_ID_INTEL_AML_YD_IMC      0x590c
0042 #define PCI_DEVICE_ID_INTEL_AML_YQ_IMC      0x590d
0043 #define PCI_DEVICE_ID_INTEL_WHL_UQ_IMC      0x3ed0
0044 #define PCI_DEVICE_ID_INTEL_WHL_4_UQ_IMC    0x3e34
0045 #define PCI_DEVICE_ID_INTEL_WHL_UD_IMC      0x3e35
0046 #define PCI_DEVICE_ID_INTEL_CML_H1_IMC      0x9b44
0047 #define PCI_DEVICE_ID_INTEL_CML_H2_IMC      0x9b54
0048 #define PCI_DEVICE_ID_INTEL_CML_H3_IMC      0x9b64
0049 #define PCI_DEVICE_ID_INTEL_CML_U1_IMC      0x9b51
0050 #define PCI_DEVICE_ID_INTEL_CML_U2_IMC      0x9b61
0051 #define PCI_DEVICE_ID_INTEL_CML_U3_IMC      0x9b71
0052 #define PCI_DEVICE_ID_INTEL_CML_S1_IMC      0x9b33
0053 #define PCI_DEVICE_ID_INTEL_CML_S2_IMC      0x9b43
0054 #define PCI_DEVICE_ID_INTEL_CML_S3_IMC      0x9b53
0055 #define PCI_DEVICE_ID_INTEL_CML_S4_IMC      0x9b63
0056 #define PCI_DEVICE_ID_INTEL_CML_S5_IMC      0x9b73
0057 #define PCI_DEVICE_ID_INTEL_ICL_U_IMC       0x8a02
0058 #define PCI_DEVICE_ID_INTEL_ICL_U2_IMC      0x8a12
0059 #define PCI_DEVICE_ID_INTEL_TGL_U1_IMC      0x9a02
0060 #define PCI_DEVICE_ID_INTEL_TGL_U2_IMC      0x9a04
0061 #define PCI_DEVICE_ID_INTEL_TGL_U3_IMC      0x9a12
0062 #define PCI_DEVICE_ID_INTEL_TGL_U4_IMC      0x9a14
0063 #define PCI_DEVICE_ID_INTEL_TGL_H_IMC       0x9a36
0064 #define PCI_DEVICE_ID_INTEL_RKL_1_IMC       0x4c43
0065 #define PCI_DEVICE_ID_INTEL_RKL_2_IMC       0x4c53
0066 #define PCI_DEVICE_ID_INTEL_ADL_1_IMC       0x4660
0067 #define PCI_DEVICE_ID_INTEL_ADL_2_IMC       0x4641
0068 #define PCI_DEVICE_ID_INTEL_ADL_3_IMC       0x4601
0069 #define PCI_DEVICE_ID_INTEL_ADL_4_IMC       0x4602
0070 #define PCI_DEVICE_ID_INTEL_ADL_5_IMC       0x4609
0071 #define PCI_DEVICE_ID_INTEL_ADL_6_IMC       0x460a
0072 #define PCI_DEVICE_ID_INTEL_ADL_7_IMC       0x4621
0073 #define PCI_DEVICE_ID_INTEL_ADL_8_IMC       0x4623
0074 #define PCI_DEVICE_ID_INTEL_ADL_9_IMC       0x4629
0075 #define PCI_DEVICE_ID_INTEL_ADL_10_IMC      0x4637
0076 #define PCI_DEVICE_ID_INTEL_ADL_11_IMC      0x463b
0077 #define PCI_DEVICE_ID_INTEL_ADL_12_IMC      0x4648
0078 #define PCI_DEVICE_ID_INTEL_ADL_13_IMC      0x4649
0079 #define PCI_DEVICE_ID_INTEL_ADL_14_IMC      0x4650
0080 #define PCI_DEVICE_ID_INTEL_ADL_15_IMC      0x4668
0081 #define PCI_DEVICE_ID_INTEL_ADL_16_IMC      0x4670
0082 #define PCI_DEVICE_ID_INTEL_ADL_17_IMC      0x4614
0083 #define PCI_DEVICE_ID_INTEL_ADL_18_IMC      0x4617
0084 #define PCI_DEVICE_ID_INTEL_ADL_19_IMC      0x4618
0085 #define PCI_DEVICE_ID_INTEL_ADL_20_IMC      0x461B
0086 #define PCI_DEVICE_ID_INTEL_ADL_21_IMC      0x461C
0087 #define PCI_DEVICE_ID_INTEL_RPL_1_IMC       0xA700
0088 #define PCI_DEVICE_ID_INTEL_RPL_2_IMC       0xA702
0089 #define PCI_DEVICE_ID_INTEL_RPL_3_IMC       0xA706
0090 #define PCI_DEVICE_ID_INTEL_RPL_4_IMC       0xA709
0091 #define PCI_DEVICE_ID_INTEL_RPL_5_IMC       0xA701
0092 #define PCI_DEVICE_ID_INTEL_RPL_6_IMC       0xA703
0093 #define PCI_DEVICE_ID_INTEL_RPL_7_IMC       0xA704
0094 #define PCI_DEVICE_ID_INTEL_RPL_8_IMC       0xA705
0095 #define PCI_DEVICE_ID_INTEL_RPL_9_IMC       0xA706
0096 #define PCI_DEVICE_ID_INTEL_RPL_10_IMC      0xA707
0097 #define PCI_DEVICE_ID_INTEL_RPL_11_IMC      0xA708
0098 #define PCI_DEVICE_ID_INTEL_RPL_12_IMC      0xA709
0099 #define PCI_DEVICE_ID_INTEL_RPL_13_IMC      0xA70a
0100 #define PCI_DEVICE_ID_INTEL_RPL_14_IMC      0xA70b
0101 #define PCI_DEVICE_ID_INTEL_RPL_15_IMC      0xA715
0102 #define PCI_DEVICE_ID_INTEL_RPL_16_IMC      0xA716
0103 #define PCI_DEVICE_ID_INTEL_RPL_17_IMC      0xA717
0104 #define PCI_DEVICE_ID_INTEL_RPL_18_IMC      0xA718
0105 #define PCI_DEVICE_ID_INTEL_RPL_19_IMC      0xA719
0106 #define PCI_DEVICE_ID_INTEL_RPL_20_IMC      0xA71A
0107 #define PCI_DEVICE_ID_INTEL_RPL_21_IMC      0xA71B
0108 #define PCI_DEVICE_ID_INTEL_RPL_22_IMC      0xA71C
0109 #define PCI_DEVICE_ID_INTEL_RPL_23_IMC      0xA728
0110 #define PCI_DEVICE_ID_INTEL_RPL_24_IMC      0xA729
0111 #define PCI_DEVICE_ID_INTEL_RPL_25_IMC      0xA72A
0112 
0113 
0114 #define IMC_UNCORE_DEV(a)                       \
0115 {                                   \
0116     PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_##a##_IMC), \
0117     .driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),  \
0118 }
0119 
0120 /* SNB event control */
0121 #define SNB_UNC_CTL_EV_SEL_MASK         0x000000ff
0122 #define SNB_UNC_CTL_UMASK_MASK          0x0000ff00
0123 #define SNB_UNC_CTL_EDGE_DET            (1 << 18)
0124 #define SNB_UNC_CTL_EN              (1 << 22)
0125 #define SNB_UNC_CTL_INVERT          (1 << 23)
0126 #define SNB_UNC_CTL_CMASK_MASK          0x1f000000
0127 #define NHM_UNC_CTL_CMASK_MASK          0xff000000
0128 #define NHM_UNC_FIXED_CTR_CTL_EN        (1 << 0)
0129 
0130 #define SNB_UNC_RAW_EVENT_MASK          (SNB_UNC_CTL_EV_SEL_MASK | \
0131                          SNB_UNC_CTL_UMASK_MASK | \
0132                          SNB_UNC_CTL_EDGE_DET | \
0133                          SNB_UNC_CTL_INVERT | \
0134                          SNB_UNC_CTL_CMASK_MASK)
0135 
0136 #define NHM_UNC_RAW_EVENT_MASK          (SNB_UNC_CTL_EV_SEL_MASK | \
0137                          SNB_UNC_CTL_UMASK_MASK | \
0138                          SNB_UNC_CTL_EDGE_DET | \
0139                          SNB_UNC_CTL_INVERT | \
0140                          NHM_UNC_CTL_CMASK_MASK)
0141 
0142 /* SNB global control register */
0143 #define SNB_UNC_PERF_GLOBAL_CTL                 0x391
0144 #define SNB_UNC_FIXED_CTR_CTRL                  0x394
0145 #define SNB_UNC_FIXED_CTR                       0x395
0146 
0147 /* SNB uncore global control */
0148 #define SNB_UNC_GLOBAL_CTL_CORE_ALL             ((1 << 4) - 1)
0149 #define SNB_UNC_GLOBAL_CTL_EN                   (1 << 29)
0150 
0151 /* SNB Cbo register */
0152 #define SNB_UNC_CBO_0_PERFEVTSEL0               0x700
0153 #define SNB_UNC_CBO_0_PER_CTR0                  0x706
0154 #define SNB_UNC_CBO_MSR_OFFSET                  0x10
0155 
0156 /* SNB ARB register */
0157 #define SNB_UNC_ARB_PER_CTR0            0x3b0
0158 #define SNB_UNC_ARB_PERFEVTSEL0         0x3b2
0159 #define SNB_UNC_ARB_MSR_OFFSET          0x10
0160 
0161 /* NHM global control register */
0162 #define NHM_UNC_PERF_GLOBAL_CTL                 0x391
0163 #define NHM_UNC_FIXED_CTR                       0x394
0164 #define NHM_UNC_FIXED_CTR_CTRL                  0x395
0165 
0166 /* NHM uncore global control */
0167 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL            ((1ULL << 8) - 1)
0168 #define NHM_UNC_GLOBAL_CTL_EN_FC                (1ULL << 32)
0169 
0170 /* NHM uncore register */
0171 #define NHM_UNC_PERFEVTSEL0                     0x3c0
0172 #define NHM_UNC_UNCORE_PMC0                     0x3b0
0173 
0174 /* SKL uncore global control */
0175 #define SKL_UNC_PERF_GLOBAL_CTL         0xe01
0176 #define SKL_UNC_GLOBAL_CTL_CORE_ALL     ((1 << 5) - 1)
0177 
0178 /* ICL Cbo register */
0179 #define ICL_UNC_CBO_CONFIG          0x396
0180 #define ICL_UNC_NUM_CBO_MASK            0xf
0181 #define ICL_UNC_CBO_0_PER_CTR0          0x702
0182 #define ICL_UNC_CBO_MSR_OFFSET          0x8
0183 
0184 /* ICL ARB register */
0185 #define ICL_UNC_ARB_PER_CTR         0x3b1
0186 #define ICL_UNC_ARB_PERFEVTSEL          0x3b3
0187 
0188 /* ADL uncore global control */
0189 #define ADL_UNC_PERF_GLOBAL_CTL         0x2ff0
0190 #define ADL_UNC_FIXED_CTR_CTRL                  0x2fde
0191 #define ADL_UNC_FIXED_CTR                       0x2fdf
0192 
0193 /* ADL Cbo register */
0194 #define ADL_UNC_CBO_0_PER_CTR0          0x2002
0195 #define ADL_UNC_CBO_0_PERFEVTSEL0       0x2000
0196 #define ADL_UNC_CTL_THRESHOLD           0x3f000000
0197 #define ADL_UNC_RAW_EVENT_MASK          (SNB_UNC_CTL_EV_SEL_MASK | \
0198                          SNB_UNC_CTL_UMASK_MASK | \
0199                          SNB_UNC_CTL_EDGE_DET | \
0200                          SNB_UNC_CTL_INVERT | \
0201                          ADL_UNC_CTL_THRESHOLD)
0202 
0203 /* ADL ARB register */
0204 #define ADL_UNC_ARB_PER_CTR0            0x2FD2
0205 #define ADL_UNC_ARB_PERFEVTSEL0         0x2FD0
0206 #define ADL_UNC_ARB_MSR_OFFSET          0x8
0207 
0208 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
0209 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
0210 DEFINE_UNCORE_FORMAT_ATTR(chmask, chmask, "config:8-11");
0211 DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
0212 DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
0213 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
0214 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
0215 DEFINE_UNCORE_FORMAT_ATTR(threshold, threshold, "config:24-29");
0216 
0217 /* Sandy Bridge uncore support */
0218 static void snb_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
0219 {
0220     struct hw_perf_event *hwc = &event->hw;
0221 
0222     if (hwc->idx < UNCORE_PMC_IDX_FIXED)
0223         wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
0224     else
0225         wrmsrl(hwc->config_base, SNB_UNC_CTL_EN);
0226 }
0227 
0228 static void snb_uncore_msr_disable_event(struct intel_uncore_box *box, struct perf_event *event)
0229 {
0230     wrmsrl(event->hw.config_base, 0);
0231 }
0232 
0233 static void snb_uncore_msr_init_box(struct intel_uncore_box *box)
0234 {
0235     if (box->pmu->pmu_idx == 0) {
0236         wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
0237             SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
0238     }
0239 }
0240 
0241 static void snb_uncore_msr_enable_box(struct intel_uncore_box *box)
0242 {
0243     wrmsrl(SNB_UNC_PERF_GLOBAL_CTL,
0244         SNB_UNC_GLOBAL_CTL_EN | SNB_UNC_GLOBAL_CTL_CORE_ALL);
0245 }
0246 
0247 static void snb_uncore_msr_exit_box(struct intel_uncore_box *box)
0248 {
0249     if (box->pmu->pmu_idx == 0)
0250         wrmsrl(SNB_UNC_PERF_GLOBAL_CTL, 0);
0251 }
0252 
0253 static struct uncore_event_desc snb_uncore_events[] = {
0254     INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
0255     { /* end: all zeroes */ },
0256 };
0257 
0258 static struct attribute *snb_uncore_formats_attr[] = {
0259     &format_attr_event.attr,
0260     &format_attr_umask.attr,
0261     &format_attr_edge.attr,
0262     &format_attr_inv.attr,
0263     &format_attr_cmask5.attr,
0264     NULL,
0265 };
0266 
0267 static const struct attribute_group snb_uncore_format_group = {
0268     .name       = "format",
0269     .attrs      = snb_uncore_formats_attr,
0270 };
0271 
0272 static struct intel_uncore_ops snb_uncore_msr_ops = {
0273     .init_box   = snb_uncore_msr_init_box,
0274     .enable_box = snb_uncore_msr_enable_box,
0275     .exit_box   = snb_uncore_msr_exit_box,
0276     .disable_event  = snb_uncore_msr_disable_event,
0277     .enable_event   = snb_uncore_msr_enable_event,
0278     .read_counter   = uncore_msr_read_counter,
0279 };
0280 
0281 static struct event_constraint snb_uncore_arb_constraints[] = {
0282     UNCORE_EVENT_CONSTRAINT(0x80, 0x1),
0283     UNCORE_EVENT_CONSTRAINT(0x83, 0x1),
0284     EVENT_CONSTRAINT_END
0285 };
0286 
0287 static struct intel_uncore_type snb_uncore_cbox = {
0288     .name       = "cbox",
0289     .num_counters   = 2,
0290     .num_boxes  = 4,
0291     .perf_ctr_bits  = 44,
0292     .fixed_ctr_bits = 48,
0293     .perf_ctr   = SNB_UNC_CBO_0_PER_CTR0,
0294     .event_ctl  = SNB_UNC_CBO_0_PERFEVTSEL0,
0295     .fixed_ctr  = SNB_UNC_FIXED_CTR,
0296     .fixed_ctl  = SNB_UNC_FIXED_CTR_CTRL,
0297     .single_fixed   = 1,
0298     .event_mask = SNB_UNC_RAW_EVENT_MASK,
0299     .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
0300     .ops        = &snb_uncore_msr_ops,
0301     .format_group   = &snb_uncore_format_group,
0302     .event_descs    = snb_uncore_events,
0303 };
0304 
0305 static struct intel_uncore_type snb_uncore_arb = {
0306     .name       = "arb",
0307     .num_counters   = 2,
0308     .num_boxes  = 1,
0309     .perf_ctr_bits  = 44,
0310     .perf_ctr   = SNB_UNC_ARB_PER_CTR0,
0311     .event_ctl  = SNB_UNC_ARB_PERFEVTSEL0,
0312     .event_mask = SNB_UNC_RAW_EVENT_MASK,
0313     .msr_offset = SNB_UNC_ARB_MSR_OFFSET,
0314     .constraints    = snb_uncore_arb_constraints,
0315     .ops        = &snb_uncore_msr_ops,
0316     .format_group   = &snb_uncore_format_group,
0317 };
0318 
0319 static struct intel_uncore_type *snb_msr_uncores[] = {
0320     &snb_uncore_cbox,
0321     &snb_uncore_arb,
0322     NULL,
0323 };
0324 
0325 void snb_uncore_cpu_init(void)
0326 {
0327     uncore_msr_uncores = snb_msr_uncores;
0328     if (snb_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
0329         snb_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
0330 }
0331 
0332 static void skl_uncore_msr_init_box(struct intel_uncore_box *box)
0333 {
0334     if (box->pmu->pmu_idx == 0) {
0335         wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
0336             SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);
0337     }
0338 
0339     /* The 8th CBOX has different MSR space */
0340     if (box->pmu->pmu_idx == 7)
0341         __set_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags);
0342 }
0343 
0344 static void skl_uncore_msr_enable_box(struct intel_uncore_box *box)
0345 {
0346     wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,
0347         SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);
0348 }
0349 
0350 static void skl_uncore_msr_exit_box(struct intel_uncore_box *box)
0351 {
0352     if (box->pmu->pmu_idx == 0)
0353         wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, 0);
0354 }
0355 
0356 static struct intel_uncore_ops skl_uncore_msr_ops = {
0357     .init_box   = skl_uncore_msr_init_box,
0358     .enable_box = skl_uncore_msr_enable_box,
0359     .exit_box   = skl_uncore_msr_exit_box,
0360     .disable_event  = snb_uncore_msr_disable_event,
0361     .enable_event   = snb_uncore_msr_enable_event,
0362     .read_counter   = uncore_msr_read_counter,
0363 };
0364 
0365 static struct intel_uncore_type skl_uncore_cbox = {
0366     .name       = "cbox",
0367     .num_counters   = 4,
0368     .num_boxes  = 8,
0369     .perf_ctr_bits  = 44,
0370     .fixed_ctr_bits = 48,
0371     .perf_ctr   = SNB_UNC_CBO_0_PER_CTR0,
0372     .event_ctl  = SNB_UNC_CBO_0_PERFEVTSEL0,
0373     .fixed_ctr  = SNB_UNC_FIXED_CTR,
0374     .fixed_ctl  = SNB_UNC_FIXED_CTR_CTRL,
0375     .single_fixed   = 1,
0376     .event_mask = SNB_UNC_RAW_EVENT_MASK,
0377     .msr_offset = SNB_UNC_CBO_MSR_OFFSET,
0378     .ops        = &skl_uncore_msr_ops,
0379     .format_group   = &snb_uncore_format_group,
0380     .event_descs    = snb_uncore_events,
0381 };
0382 
0383 static struct intel_uncore_type *skl_msr_uncores[] = {
0384     &skl_uncore_cbox,
0385     &snb_uncore_arb,
0386     NULL,
0387 };
0388 
0389 void skl_uncore_cpu_init(void)
0390 {
0391     uncore_msr_uncores = skl_msr_uncores;
0392     if (skl_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores)
0393         skl_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores;
0394     snb_uncore_arb.ops = &skl_uncore_msr_ops;
0395 }
0396 
0397 static struct intel_uncore_ops icl_uncore_msr_ops = {
0398     .disable_event  = snb_uncore_msr_disable_event,
0399     .enable_event   = snb_uncore_msr_enable_event,
0400     .read_counter   = uncore_msr_read_counter,
0401 };
0402 
0403 static struct intel_uncore_type icl_uncore_cbox = {
0404     .name       = "cbox",
0405     .num_counters   = 2,
0406     .perf_ctr_bits  = 44,
0407     .perf_ctr   = ICL_UNC_CBO_0_PER_CTR0,
0408     .event_ctl  = SNB_UNC_CBO_0_PERFEVTSEL0,
0409     .event_mask = SNB_UNC_RAW_EVENT_MASK,
0410     .msr_offset = ICL_UNC_CBO_MSR_OFFSET,
0411     .ops        = &icl_uncore_msr_ops,
0412     .format_group   = &snb_uncore_format_group,
0413 };
0414 
0415 static struct uncore_event_desc icl_uncore_events[] = {
0416     INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff"),
0417     { /* end: all zeroes */ },
0418 };
0419 
0420 static struct attribute *icl_uncore_clock_formats_attr[] = {
0421     &format_attr_event.attr,
0422     NULL,
0423 };
0424 
0425 static struct attribute_group icl_uncore_clock_format_group = {
0426     .name = "format",
0427     .attrs = icl_uncore_clock_formats_attr,
0428 };
0429 
0430 static struct intel_uncore_type icl_uncore_clockbox = {
0431     .name       = "clock",
0432     .num_counters   = 1,
0433     .num_boxes  = 1,
0434     .fixed_ctr_bits = 48,
0435     .fixed_ctr  = SNB_UNC_FIXED_CTR,
0436     .fixed_ctl  = SNB_UNC_FIXED_CTR_CTRL,
0437     .single_fixed   = 1,
0438     .event_mask = SNB_UNC_CTL_EV_SEL_MASK,
0439     .format_group   = &icl_uncore_clock_format_group,
0440     .ops        = &icl_uncore_msr_ops,
0441     .event_descs    = icl_uncore_events,
0442 };
0443 
0444 static struct intel_uncore_type icl_uncore_arb = {
0445     .name       = "arb",
0446     .num_counters   = 1,
0447     .num_boxes  = 1,
0448     .perf_ctr_bits  = 44,
0449     .perf_ctr   = ICL_UNC_ARB_PER_CTR,
0450     .event_ctl  = ICL_UNC_ARB_PERFEVTSEL,
0451     .event_mask = SNB_UNC_RAW_EVENT_MASK,
0452     .ops        = &icl_uncore_msr_ops,
0453     .format_group   = &snb_uncore_format_group,
0454 };
0455 
0456 static struct intel_uncore_type *icl_msr_uncores[] = {
0457     &icl_uncore_cbox,
0458     &icl_uncore_arb,
0459     &icl_uncore_clockbox,
0460     NULL,
0461 };
0462 
0463 static int icl_get_cbox_num(void)
0464 {
0465     u64 num_boxes;
0466 
0467     rdmsrl(ICL_UNC_CBO_CONFIG, num_boxes);
0468 
0469     return num_boxes & ICL_UNC_NUM_CBO_MASK;
0470 }
0471 
0472 void icl_uncore_cpu_init(void)
0473 {
0474     uncore_msr_uncores = icl_msr_uncores;
0475     icl_uncore_cbox.num_boxes = icl_get_cbox_num();
0476 }
0477 
0478 static struct intel_uncore_type *tgl_msr_uncores[] = {
0479     &icl_uncore_cbox,
0480     &snb_uncore_arb,
0481     &icl_uncore_clockbox,
0482     NULL,
0483 };
0484 
0485 static void rkl_uncore_msr_init_box(struct intel_uncore_box *box)
0486 {
0487     if (box->pmu->pmu_idx == 0)
0488         wrmsrl(SKL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
0489 }
0490 
0491 void tgl_uncore_cpu_init(void)
0492 {
0493     uncore_msr_uncores = tgl_msr_uncores;
0494     icl_uncore_cbox.num_boxes = icl_get_cbox_num();
0495     icl_uncore_cbox.ops = &skl_uncore_msr_ops;
0496     icl_uncore_clockbox.ops = &skl_uncore_msr_ops;
0497     snb_uncore_arb.ops = &skl_uncore_msr_ops;
0498     skl_uncore_msr_ops.init_box = rkl_uncore_msr_init_box;
0499 }
0500 
0501 static void adl_uncore_msr_init_box(struct intel_uncore_box *box)
0502 {
0503     if (box->pmu->pmu_idx == 0)
0504         wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
0505 }
0506 
0507 static void adl_uncore_msr_enable_box(struct intel_uncore_box *box)
0508 {
0509     wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, SNB_UNC_GLOBAL_CTL_EN);
0510 }
0511 
0512 static void adl_uncore_msr_disable_box(struct intel_uncore_box *box)
0513 {
0514     if (box->pmu->pmu_idx == 0)
0515         wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, 0);
0516 }
0517 
0518 static void adl_uncore_msr_exit_box(struct intel_uncore_box *box)
0519 {
0520     if (box->pmu->pmu_idx == 0)
0521         wrmsrl(ADL_UNC_PERF_GLOBAL_CTL, 0);
0522 }
0523 
0524 static struct intel_uncore_ops adl_uncore_msr_ops = {
0525     .init_box   = adl_uncore_msr_init_box,
0526     .enable_box = adl_uncore_msr_enable_box,
0527     .disable_box    = adl_uncore_msr_disable_box,
0528     .exit_box   = adl_uncore_msr_exit_box,
0529     .disable_event  = snb_uncore_msr_disable_event,
0530     .enable_event   = snb_uncore_msr_enable_event,
0531     .read_counter   = uncore_msr_read_counter,
0532 };
0533 
0534 static struct attribute *adl_uncore_formats_attr[] = {
0535     &format_attr_event.attr,
0536     &format_attr_umask.attr,
0537     &format_attr_edge.attr,
0538     &format_attr_inv.attr,
0539     &format_attr_threshold.attr,
0540     NULL,
0541 };
0542 
0543 static const struct attribute_group adl_uncore_format_group = {
0544     .name       = "format",
0545     .attrs      = adl_uncore_formats_attr,
0546 };
0547 
0548 static struct intel_uncore_type adl_uncore_cbox = {
0549     .name       = "cbox",
0550     .num_counters   = 2,
0551     .perf_ctr_bits  = 44,
0552     .perf_ctr   = ADL_UNC_CBO_0_PER_CTR0,
0553     .event_ctl  = ADL_UNC_CBO_0_PERFEVTSEL0,
0554     .event_mask = ADL_UNC_RAW_EVENT_MASK,
0555     .msr_offset = ICL_UNC_CBO_MSR_OFFSET,
0556     .ops        = &adl_uncore_msr_ops,
0557     .format_group   = &adl_uncore_format_group,
0558 };
0559 
0560 static struct intel_uncore_type adl_uncore_arb = {
0561     .name       = "arb",
0562     .num_counters   = 2,
0563     .num_boxes  = 2,
0564     .perf_ctr_bits  = 44,
0565     .perf_ctr   = ADL_UNC_ARB_PER_CTR0,
0566     .event_ctl  = ADL_UNC_ARB_PERFEVTSEL0,
0567     .event_mask = SNB_UNC_RAW_EVENT_MASK,
0568     .msr_offset = ADL_UNC_ARB_MSR_OFFSET,
0569     .constraints    = snb_uncore_arb_constraints,
0570     .ops        = &adl_uncore_msr_ops,
0571     .format_group   = &snb_uncore_format_group,
0572 };
0573 
0574 static struct intel_uncore_type adl_uncore_clockbox = {
0575     .name       = "clock",
0576     .num_counters   = 1,
0577     .num_boxes  = 1,
0578     .fixed_ctr_bits = 48,
0579     .fixed_ctr  = ADL_UNC_FIXED_CTR,
0580     .fixed_ctl  = ADL_UNC_FIXED_CTR_CTRL,
0581     .single_fixed   = 1,
0582     .event_mask = SNB_UNC_CTL_EV_SEL_MASK,
0583     .format_group   = &icl_uncore_clock_format_group,
0584     .ops        = &adl_uncore_msr_ops,
0585     .event_descs    = icl_uncore_events,
0586 };
0587 
0588 static struct intel_uncore_type *adl_msr_uncores[] = {
0589     &adl_uncore_cbox,
0590     &adl_uncore_arb,
0591     &adl_uncore_clockbox,
0592     NULL,
0593 };
0594 
0595 void adl_uncore_cpu_init(void)
0596 {
0597     adl_uncore_cbox.num_boxes = icl_get_cbox_num();
0598     uncore_msr_uncores = adl_msr_uncores;
0599 }
0600 
0601 enum {
0602     SNB_PCI_UNCORE_IMC,
0603 };
0604 
0605 static struct uncore_event_desc snb_uncore_imc_events[] = {
0606     INTEL_UNCORE_EVENT_DESC(data_reads,  "event=0x01"),
0607     INTEL_UNCORE_EVENT_DESC(data_reads.scale, "6.103515625e-5"),
0608     INTEL_UNCORE_EVENT_DESC(data_reads.unit, "MiB"),
0609 
0610     INTEL_UNCORE_EVENT_DESC(data_writes, "event=0x02"),
0611     INTEL_UNCORE_EVENT_DESC(data_writes.scale, "6.103515625e-5"),
0612     INTEL_UNCORE_EVENT_DESC(data_writes.unit, "MiB"),
0613 
0614     INTEL_UNCORE_EVENT_DESC(gt_requests, "event=0x03"),
0615     INTEL_UNCORE_EVENT_DESC(gt_requests.scale, "6.103515625e-5"),
0616     INTEL_UNCORE_EVENT_DESC(gt_requests.unit, "MiB"),
0617 
0618     INTEL_UNCORE_EVENT_DESC(ia_requests, "event=0x04"),
0619     INTEL_UNCORE_EVENT_DESC(ia_requests.scale, "6.103515625e-5"),
0620     INTEL_UNCORE_EVENT_DESC(ia_requests.unit, "MiB"),
0621 
0622     INTEL_UNCORE_EVENT_DESC(io_requests, "event=0x05"),
0623     INTEL_UNCORE_EVENT_DESC(io_requests.scale, "6.103515625e-5"),
0624     INTEL_UNCORE_EVENT_DESC(io_requests.unit, "MiB"),
0625 
0626     { /* end: all zeroes */ },
0627 };
0628 
0629 #define SNB_UNCORE_PCI_IMC_EVENT_MASK       0xff
0630 #define SNB_UNCORE_PCI_IMC_BAR_OFFSET       0x48
0631 
0632 /* page size multiple covering all config regs */
0633 #define SNB_UNCORE_PCI_IMC_MAP_SIZE     0x6000
0634 
0635 #define SNB_UNCORE_PCI_IMC_DATA_READS       0x1
0636 #define SNB_UNCORE_PCI_IMC_DATA_READS_BASE  0x5050
0637 #define SNB_UNCORE_PCI_IMC_DATA_WRITES      0x2
0638 #define SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE 0x5054
0639 #define SNB_UNCORE_PCI_IMC_CTR_BASE     SNB_UNCORE_PCI_IMC_DATA_READS_BASE
0640 
0641 /* BW break down- legacy counters */
0642 #define SNB_UNCORE_PCI_IMC_GT_REQUESTS      0x3
0643 #define SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE 0x5040
0644 #define SNB_UNCORE_PCI_IMC_IA_REQUESTS      0x4
0645 #define SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE 0x5044
0646 #define SNB_UNCORE_PCI_IMC_IO_REQUESTS      0x5
0647 #define SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE 0x5048
0648 
0649 enum perf_snb_uncore_imc_freerunning_types {
0650     SNB_PCI_UNCORE_IMC_DATA_READS       = 0,
0651     SNB_PCI_UNCORE_IMC_DATA_WRITES,
0652     SNB_PCI_UNCORE_IMC_GT_REQUESTS,
0653     SNB_PCI_UNCORE_IMC_IA_REQUESTS,
0654     SNB_PCI_UNCORE_IMC_IO_REQUESTS,
0655 
0656     SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
0657 };
0658 
0659 static struct freerunning_counters snb_uncore_imc_freerunning[] = {
0660     [SNB_PCI_UNCORE_IMC_DATA_READS]     = { SNB_UNCORE_PCI_IMC_DATA_READS_BASE,
0661                             0x0, 0x0, 1, 32 },
0662     [SNB_PCI_UNCORE_IMC_DATA_WRITES]    = { SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE,
0663                             0x0, 0x0, 1, 32 },
0664     [SNB_PCI_UNCORE_IMC_GT_REQUESTS]    = { SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE,
0665                             0x0, 0x0, 1, 32 },
0666     [SNB_PCI_UNCORE_IMC_IA_REQUESTS]    = { SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE,
0667                             0x0, 0x0, 1, 32 },
0668     [SNB_PCI_UNCORE_IMC_IO_REQUESTS]    = { SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE,
0669                             0x0, 0x0, 1, 32 },
0670 };
0671 
0672 static struct attribute *snb_uncore_imc_formats_attr[] = {
0673     &format_attr_event.attr,
0674     NULL,
0675 };
0676 
0677 static const struct attribute_group snb_uncore_imc_format_group = {
0678     .name = "format",
0679     .attrs = snb_uncore_imc_formats_attr,
0680 };
0681 
0682 static void snb_uncore_imc_init_box(struct intel_uncore_box *box)
0683 {
0684     struct intel_uncore_type *type = box->pmu->type;
0685     struct pci_dev *pdev = box->pci_dev;
0686     int where = SNB_UNCORE_PCI_IMC_BAR_OFFSET;
0687     resource_size_t addr;
0688     u32 pci_dword;
0689 
0690     pci_read_config_dword(pdev, where, &pci_dword);
0691     addr = pci_dword;
0692 
0693 #ifdef CONFIG_PHYS_ADDR_T_64BIT
0694     pci_read_config_dword(pdev, where + 4, &pci_dword);
0695     addr |= ((resource_size_t)pci_dword << 32);
0696 #endif
0697 
0698     addr &= ~(PAGE_SIZE - 1);
0699 
0700     box->io_addr = ioremap(addr, type->mmio_map_size);
0701     if (!box->io_addr)
0702         pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name);
0703 
0704     box->hrtimer_duration = UNCORE_SNB_IMC_HRTIMER_INTERVAL;
0705 }
0706 
0707 static void snb_uncore_imc_enable_box(struct intel_uncore_box *box)
0708 {}
0709 
0710 static void snb_uncore_imc_disable_box(struct intel_uncore_box *box)
0711 {}
0712 
0713 static void snb_uncore_imc_enable_event(struct intel_uncore_box *box, struct perf_event *event)
0714 {}
0715 
0716 static void snb_uncore_imc_disable_event(struct intel_uncore_box *box, struct perf_event *event)
0717 {}
0718 
0719 /*
0720  * Keep the custom event_init() function compatible with old event
0721  * encoding for free running counters.
0722  */
0723 static int snb_uncore_imc_event_init(struct perf_event *event)
0724 {
0725     struct intel_uncore_pmu *pmu;
0726     struct intel_uncore_box *box;
0727     struct hw_perf_event *hwc = &event->hw;
0728     u64 cfg = event->attr.config & SNB_UNCORE_PCI_IMC_EVENT_MASK;
0729     int idx, base;
0730 
0731     if (event->attr.type != event->pmu->type)
0732         return -ENOENT;
0733 
0734     pmu = uncore_event_to_pmu(event);
0735     /* no device found for this pmu */
0736     if (pmu->func_id < 0)
0737         return -ENOENT;
0738 
0739     /* Sampling not supported yet */
0740     if (hwc->sample_period)
0741         return -EINVAL;
0742 
0743     /* unsupported modes and filters */
0744     if (event->attr.sample_period) /* no sampling */
0745         return -EINVAL;
0746 
0747     /*
0748      * Place all uncore events for a particular physical package
0749      * onto a single cpu
0750      */
0751     if (event->cpu < 0)
0752         return -EINVAL;
0753 
0754     /* check only supported bits are set */
0755     if (event->attr.config & ~SNB_UNCORE_PCI_IMC_EVENT_MASK)
0756         return -EINVAL;
0757 
0758     box = uncore_pmu_to_box(pmu, event->cpu);
0759     if (!box || box->cpu < 0)
0760         return -EINVAL;
0761 
0762     event->cpu = box->cpu;
0763     event->pmu_private = box;
0764 
0765     event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG;
0766 
0767     event->hw.idx = -1;
0768     event->hw.last_tag = ~0ULL;
0769     event->hw.extra_reg.idx = EXTRA_REG_NONE;
0770     event->hw.branch_reg.idx = EXTRA_REG_NONE;
0771     /*
0772      * check event is known (whitelist, determines counter)
0773      */
0774     switch (cfg) {
0775     case SNB_UNCORE_PCI_IMC_DATA_READS:
0776         base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE;
0777         idx = UNCORE_PMC_IDX_FREERUNNING;
0778         break;
0779     case SNB_UNCORE_PCI_IMC_DATA_WRITES:
0780         base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
0781         idx = UNCORE_PMC_IDX_FREERUNNING;
0782         break;
0783     case SNB_UNCORE_PCI_IMC_GT_REQUESTS:
0784         base = SNB_UNCORE_PCI_IMC_GT_REQUESTS_BASE;
0785         idx = UNCORE_PMC_IDX_FREERUNNING;
0786         break;
0787     case SNB_UNCORE_PCI_IMC_IA_REQUESTS:
0788         base = SNB_UNCORE_PCI_IMC_IA_REQUESTS_BASE;
0789         idx = UNCORE_PMC_IDX_FREERUNNING;
0790         break;
0791     case SNB_UNCORE_PCI_IMC_IO_REQUESTS:
0792         base = SNB_UNCORE_PCI_IMC_IO_REQUESTS_BASE;
0793         idx = UNCORE_PMC_IDX_FREERUNNING;
0794         break;
0795     default:
0796         return -EINVAL;
0797     }
0798 
0799     /* must be done before validate_group */
0800     event->hw.event_base = base;
0801     event->hw.idx = idx;
0802 
0803     /* Convert to standard encoding format for freerunning counters */
0804     event->hw.config = ((cfg - 1) << 8) | 0x10ff;
0805 
0806     /* no group validation needed, we have free running counters */
0807 
0808     return 0;
0809 }
0810 
0811 static int snb_uncore_imc_hw_config(struct intel_uncore_box *box, struct perf_event *event)
0812 {
0813     return 0;
0814 }
0815 
0816 int snb_pci2phy_map_init(int devid)
0817 {
0818     struct pci_dev *dev = NULL;
0819     struct pci2phy_map *map;
0820     int bus, segment;
0821 
0822     dev = pci_get_device(PCI_VENDOR_ID_INTEL, devid, dev);
0823     if (!dev)
0824         return -ENOTTY;
0825 
0826     bus = dev->bus->number;
0827     segment = pci_domain_nr(dev->bus);
0828 
0829     raw_spin_lock(&pci2phy_map_lock);
0830     map = __find_pci2phy_map(segment);
0831     if (!map) {
0832         raw_spin_unlock(&pci2phy_map_lock);
0833         pci_dev_put(dev);
0834         return -ENOMEM;
0835     }
0836     map->pbus_to_dieid[bus] = 0;
0837     raw_spin_unlock(&pci2phy_map_lock);
0838 
0839     pci_dev_put(dev);
0840 
0841     return 0;
0842 }
0843 
0844 static u64 snb_uncore_imc_read_counter(struct intel_uncore_box *box, struct perf_event *event)
0845 {
0846     struct hw_perf_event *hwc = &event->hw;
0847 
0848     /*
0849      * SNB IMC counters are 32-bit and are laid out back to back
0850      * in MMIO space. Therefore we must use a 32-bit accessor function
0851      * using readq() from uncore_mmio_read_counter() causes problems
0852      * because it is reading 64-bit at a time. This is okay for the
0853      * uncore_perf_event_update() function because it drops the upper
0854      * 32-bits but not okay for plain uncore_read_counter() as invoked
0855      * in uncore_pmu_event_start().
0856      */
0857     return (u64)readl(box->io_addr + hwc->event_base);
0858 }
0859 
0860 static struct pmu snb_uncore_imc_pmu = {
0861     .task_ctx_nr    = perf_invalid_context,
0862     .event_init = snb_uncore_imc_event_init,
0863     .add        = uncore_pmu_event_add,
0864     .del        = uncore_pmu_event_del,
0865     .start      = uncore_pmu_event_start,
0866     .stop       = uncore_pmu_event_stop,
0867     .read       = uncore_pmu_event_read,
0868     .capabilities   = PERF_PMU_CAP_NO_EXCLUDE,
0869 };
0870 
0871 static struct intel_uncore_ops snb_uncore_imc_ops = {
0872     .init_box   = snb_uncore_imc_init_box,
0873     .exit_box   = uncore_mmio_exit_box,
0874     .enable_box = snb_uncore_imc_enable_box,
0875     .disable_box    = snb_uncore_imc_disable_box,
0876     .disable_event  = snb_uncore_imc_disable_event,
0877     .enable_event   = snb_uncore_imc_enable_event,
0878     .hw_config  = snb_uncore_imc_hw_config,
0879     .read_counter   = snb_uncore_imc_read_counter,
0880 };
0881 
0882 static struct intel_uncore_type snb_uncore_imc = {
0883     .name       = "imc",
0884     .num_counters   = 5,
0885     .num_boxes  = 1,
0886     .num_freerunning_types  = SNB_PCI_UNCORE_IMC_FREERUNNING_TYPE_MAX,
0887     .mmio_map_size  = SNB_UNCORE_PCI_IMC_MAP_SIZE,
0888     .freerunning    = snb_uncore_imc_freerunning,
0889     .event_descs    = snb_uncore_imc_events,
0890     .format_group   = &snb_uncore_imc_format_group,
0891     .ops        = &snb_uncore_imc_ops,
0892     .pmu        = &snb_uncore_imc_pmu,
0893 };
0894 
0895 static struct intel_uncore_type *snb_pci_uncores[] = {
0896     [SNB_PCI_UNCORE_IMC]    = &snb_uncore_imc,
0897     NULL,
0898 };
0899 
0900 static const struct pci_device_id snb_uncore_pci_ids[] = {
0901     IMC_UNCORE_DEV(SNB),
0902     { /* end: all zeroes */ },
0903 };
0904 
0905 static const struct pci_device_id ivb_uncore_pci_ids[] = {
0906     IMC_UNCORE_DEV(IVB),
0907     IMC_UNCORE_DEV(IVB_E3),
0908     { /* end: all zeroes */ },
0909 };
0910 
0911 static const struct pci_device_id hsw_uncore_pci_ids[] = {
0912     IMC_UNCORE_DEV(HSW),
0913     IMC_UNCORE_DEV(HSW_U),
0914     { /* end: all zeroes */ },
0915 };
0916 
0917 static const struct pci_device_id bdw_uncore_pci_ids[] = {
0918     IMC_UNCORE_DEV(BDW),
0919     { /* end: all zeroes */ },
0920 };
0921 
0922 static const struct pci_device_id skl_uncore_pci_ids[] = {
0923     IMC_UNCORE_DEV(SKL_Y),
0924     IMC_UNCORE_DEV(SKL_U),
0925     IMC_UNCORE_DEV(SKL_HD),
0926     IMC_UNCORE_DEV(SKL_HQ),
0927     IMC_UNCORE_DEV(SKL_SD),
0928     IMC_UNCORE_DEV(SKL_SQ),
0929     IMC_UNCORE_DEV(SKL_E3),
0930     IMC_UNCORE_DEV(KBL_Y),
0931     IMC_UNCORE_DEV(KBL_U),
0932     IMC_UNCORE_DEV(KBL_UQ),
0933     IMC_UNCORE_DEV(KBL_SD),
0934     IMC_UNCORE_DEV(KBL_SQ),
0935     IMC_UNCORE_DEV(KBL_HQ),
0936     IMC_UNCORE_DEV(KBL_WQ),
0937     IMC_UNCORE_DEV(CFL_2U),
0938     IMC_UNCORE_DEV(CFL_4U),
0939     IMC_UNCORE_DEV(CFL_4H),
0940     IMC_UNCORE_DEV(CFL_6H),
0941     IMC_UNCORE_DEV(CFL_2S_D),
0942     IMC_UNCORE_DEV(CFL_4S_D),
0943     IMC_UNCORE_DEV(CFL_6S_D),
0944     IMC_UNCORE_DEV(CFL_8S_D),
0945     IMC_UNCORE_DEV(CFL_4S_W),
0946     IMC_UNCORE_DEV(CFL_6S_W),
0947     IMC_UNCORE_DEV(CFL_8S_W),
0948     IMC_UNCORE_DEV(CFL_4S_S),
0949     IMC_UNCORE_DEV(CFL_6S_S),
0950     IMC_UNCORE_DEV(CFL_8S_S),
0951     IMC_UNCORE_DEV(AML_YD),
0952     IMC_UNCORE_DEV(AML_YQ),
0953     IMC_UNCORE_DEV(WHL_UQ),
0954     IMC_UNCORE_DEV(WHL_4_UQ),
0955     IMC_UNCORE_DEV(WHL_UD),
0956     IMC_UNCORE_DEV(CML_H1),
0957     IMC_UNCORE_DEV(CML_H2),
0958     IMC_UNCORE_DEV(CML_H3),
0959     IMC_UNCORE_DEV(CML_U1),
0960     IMC_UNCORE_DEV(CML_U2),
0961     IMC_UNCORE_DEV(CML_U3),
0962     IMC_UNCORE_DEV(CML_S1),
0963     IMC_UNCORE_DEV(CML_S2),
0964     IMC_UNCORE_DEV(CML_S3),
0965     IMC_UNCORE_DEV(CML_S4),
0966     IMC_UNCORE_DEV(CML_S5),
0967     { /* end: all zeroes */ },
0968 };
0969 
0970 static const struct pci_device_id icl_uncore_pci_ids[] = {
0971     IMC_UNCORE_DEV(ICL_U),
0972     IMC_UNCORE_DEV(ICL_U2),
0973     IMC_UNCORE_DEV(RKL_1),
0974     IMC_UNCORE_DEV(RKL_2),
0975     { /* end: all zeroes */ },
0976 };
0977 
0978 static struct pci_driver snb_uncore_pci_driver = {
0979     .name       = "snb_uncore",
0980     .id_table   = snb_uncore_pci_ids,
0981 };
0982 
0983 static struct pci_driver ivb_uncore_pci_driver = {
0984     .name       = "ivb_uncore",
0985     .id_table   = ivb_uncore_pci_ids,
0986 };
0987 
0988 static struct pci_driver hsw_uncore_pci_driver = {
0989     .name       = "hsw_uncore",
0990     .id_table   = hsw_uncore_pci_ids,
0991 };
0992 
0993 static struct pci_driver bdw_uncore_pci_driver = {
0994     .name       = "bdw_uncore",
0995     .id_table   = bdw_uncore_pci_ids,
0996 };
0997 
0998 static struct pci_driver skl_uncore_pci_driver = {
0999     .name       = "skl_uncore",
1000     .id_table   = skl_uncore_pci_ids,
1001 };
1002 
1003 static struct pci_driver icl_uncore_pci_driver = {
1004     .name       = "icl_uncore",
1005     .id_table   = icl_uncore_pci_ids,
1006 };
1007 
1008 struct imc_uncore_pci_dev {
1009     __u32 pci_id;
1010     struct pci_driver *driver;
1011 };
1012 #define IMC_DEV(a, d) \
1013     { .pci_id = PCI_DEVICE_ID_INTEL_##a, .driver = (d) }
1014 
1015 static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
1016     IMC_DEV(SNB_IMC, &snb_uncore_pci_driver),
1017     IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver),    /* 3rd Gen Core processor */
1018     IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */
1019     IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver),    /* 4th Gen Core Processor */
1020     IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver),  /* 4th Gen Core ULT Mobile Processor */
1021     IMC_DEV(BDW_IMC, &bdw_uncore_pci_driver),    /* 5th Gen Core U */
1022     IMC_DEV(SKL_Y_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core Y */
1023     IMC_DEV(SKL_U_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core U */
1024     IMC_DEV(SKL_HD_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core H Dual Core */
1025     IMC_DEV(SKL_HQ_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core H Quad Core */
1026     IMC_DEV(SKL_SD_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core S Dual Core */
1027     IMC_DEV(SKL_SQ_IMC, &skl_uncore_pci_driver),  /* 6th Gen Core S Quad Core */
1028     IMC_DEV(SKL_E3_IMC, &skl_uncore_pci_driver),  /* Xeon E3 V5 Gen Core processor */
1029     IMC_DEV(KBL_Y_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core Y */
1030     IMC_DEV(KBL_U_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core U */
1031     IMC_DEV(KBL_UQ_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core U Quad Core */
1032     IMC_DEV(KBL_SD_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core S Dual Core */
1033     IMC_DEV(KBL_SQ_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core S Quad Core */
1034     IMC_DEV(KBL_HQ_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core H Quad Core */
1035     IMC_DEV(KBL_WQ_IMC, &skl_uncore_pci_driver),  /* 7th Gen Core S 4 cores Work Station */
1036     IMC_DEV(CFL_2U_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core U 2 Cores */
1037     IMC_DEV(CFL_4U_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core U 4 Cores */
1038     IMC_DEV(CFL_4H_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core H 4 Cores */
1039     IMC_DEV(CFL_6H_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core H 6 Cores */
1040     IMC_DEV(CFL_2S_D_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 2 Cores Desktop */
1041     IMC_DEV(CFL_4S_D_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 4 Cores Desktop */
1042     IMC_DEV(CFL_6S_D_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 6 Cores Desktop */
1043     IMC_DEV(CFL_8S_D_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 8 Cores Desktop */
1044     IMC_DEV(CFL_4S_W_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 4 Cores Work Station */
1045     IMC_DEV(CFL_6S_W_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 6 Cores Work Station */
1046     IMC_DEV(CFL_8S_W_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 8 Cores Work Station */
1047     IMC_DEV(CFL_4S_S_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 4 Cores Server */
1048     IMC_DEV(CFL_6S_S_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 6 Cores Server */
1049     IMC_DEV(CFL_8S_S_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core S 8 Cores Server */
1050     IMC_DEV(AML_YD_IMC, &skl_uncore_pci_driver),    /* 8th Gen Core Y Mobile Dual Core */
1051     IMC_DEV(AML_YQ_IMC, &skl_uncore_pci_driver),    /* 8th Gen Core Y Mobile Quad Core */
1052     IMC_DEV(WHL_UQ_IMC, &skl_uncore_pci_driver),    /* 8th Gen Core U Mobile Quad Core */
1053     IMC_DEV(WHL_4_UQ_IMC, &skl_uncore_pci_driver),  /* 8th Gen Core U Mobile Quad Core */
1054     IMC_DEV(WHL_UD_IMC, &skl_uncore_pci_driver),    /* 8th Gen Core U Mobile Dual Core */
1055     IMC_DEV(CML_H1_IMC, &skl_uncore_pci_driver),
1056     IMC_DEV(CML_H2_IMC, &skl_uncore_pci_driver),
1057     IMC_DEV(CML_H3_IMC, &skl_uncore_pci_driver),
1058     IMC_DEV(CML_U1_IMC, &skl_uncore_pci_driver),
1059     IMC_DEV(CML_U2_IMC, &skl_uncore_pci_driver),
1060     IMC_DEV(CML_U3_IMC, &skl_uncore_pci_driver),
1061     IMC_DEV(CML_S1_IMC, &skl_uncore_pci_driver),
1062     IMC_DEV(CML_S2_IMC, &skl_uncore_pci_driver),
1063     IMC_DEV(CML_S3_IMC, &skl_uncore_pci_driver),
1064     IMC_DEV(CML_S4_IMC, &skl_uncore_pci_driver),
1065     IMC_DEV(CML_S5_IMC, &skl_uncore_pci_driver),
1066     IMC_DEV(ICL_U_IMC, &icl_uncore_pci_driver), /* 10th Gen Core Mobile */
1067     IMC_DEV(ICL_U2_IMC, &icl_uncore_pci_driver),    /* 10th Gen Core Mobile */
1068     IMC_DEV(RKL_1_IMC, &icl_uncore_pci_driver),
1069     IMC_DEV(RKL_2_IMC, &icl_uncore_pci_driver),
1070     {  /* end marker */ }
1071 };
1072 
1073 
1074 #define for_each_imc_pci_id(x, t) \
1075     for (x = (t); (x)->pci_id; x++)
1076 
1077 static struct pci_driver *imc_uncore_find_dev(void)
1078 {
1079     const struct imc_uncore_pci_dev *p;
1080     int ret;
1081 
1082     for_each_imc_pci_id(p, desktop_imc_pci_ids) {
1083         ret = snb_pci2phy_map_init(p->pci_id);
1084         if (ret == 0)
1085             return p->driver;
1086     }
1087     return NULL;
1088 }
1089 
1090 static int imc_uncore_pci_init(void)
1091 {
1092     struct pci_driver *imc_drv = imc_uncore_find_dev();
1093 
1094     if (!imc_drv)
1095         return -ENODEV;
1096 
1097     uncore_pci_uncores = snb_pci_uncores;
1098     uncore_pci_driver = imc_drv;
1099 
1100     return 0;
1101 }
1102 
1103 int snb_uncore_pci_init(void)
1104 {
1105     return imc_uncore_pci_init();
1106 }
1107 
1108 int ivb_uncore_pci_init(void)
1109 {
1110     return imc_uncore_pci_init();
1111 }
1112 int hsw_uncore_pci_init(void)
1113 {
1114     return imc_uncore_pci_init();
1115 }
1116 
1117 int bdw_uncore_pci_init(void)
1118 {
1119     return imc_uncore_pci_init();
1120 }
1121 
1122 int skl_uncore_pci_init(void)
1123 {
1124     return imc_uncore_pci_init();
1125 }
1126 
1127 /* end of Sandy Bridge uncore support */
1128 
1129 /* Nehalem uncore support */
1130 static void nhm_uncore_msr_disable_box(struct intel_uncore_box *box)
1131 {
1132     wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, 0);
1133 }
1134 
1135 static void nhm_uncore_msr_enable_box(struct intel_uncore_box *box)
1136 {
1137     wrmsrl(NHM_UNC_PERF_GLOBAL_CTL, NHM_UNC_GLOBAL_CTL_EN_PC_ALL | NHM_UNC_GLOBAL_CTL_EN_FC);
1138 }
1139 
1140 static void nhm_uncore_msr_enable_event(struct intel_uncore_box *box, struct perf_event *event)
1141 {
1142     struct hw_perf_event *hwc = &event->hw;
1143 
1144     if (hwc->idx < UNCORE_PMC_IDX_FIXED)
1145         wrmsrl(hwc->config_base, hwc->config | SNB_UNC_CTL_EN);
1146     else
1147         wrmsrl(hwc->config_base, NHM_UNC_FIXED_CTR_CTL_EN);
1148 }
1149 
1150 static struct attribute *nhm_uncore_formats_attr[] = {
1151     &format_attr_event.attr,
1152     &format_attr_umask.attr,
1153     &format_attr_edge.attr,
1154     &format_attr_inv.attr,
1155     &format_attr_cmask8.attr,
1156     NULL,
1157 };
1158 
1159 static const struct attribute_group nhm_uncore_format_group = {
1160     .name = "format",
1161     .attrs = nhm_uncore_formats_attr,
1162 };
1163 
1164 static struct uncore_event_desc nhm_uncore_events[] = {
1165     INTEL_UNCORE_EVENT_DESC(clockticks,                "event=0xff,umask=0x00"),
1166     INTEL_UNCORE_EVENT_DESC(qmc_writes_full_any,       "event=0x2f,umask=0x0f"),
1167     INTEL_UNCORE_EVENT_DESC(qmc_normal_reads_any,      "event=0x2c,umask=0x0f"),
1168     INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_reads,     "event=0x20,umask=0x01"),
1169     INTEL_UNCORE_EVENT_DESC(qhl_request_ioh_writes,    "event=0x20,umask=0x02"),
1170     INTEL_UNCORE_EVENT_DESC(qhl_request_remote_reads,  "event=0x20,umask=0x04"),
1171     INTEL_UNCORE_EVENT_DESC(qhl_request_remote_writes, "event=0x20,umask=0x08"),
1172     INTEL_UNCORE_EVENT_DESC(qhl_request_local_reads,   "event=0x20,umask=0x10"),
1173     INTEL_UNCORE_EVENT_DESC(qhl_request_local_writes,  "event=0x20,umask=0x20"),
1174     { /* end: all zeroes */ },
1175 };
1176 
1177 static struct intel_uncore_ops nhm_uncore_msr_ops = {
1178     .disable_box    = nhm_uncore_msr_disable_box,
1179     .enable_box = nhm_uncore_msr_enable_box,
1180     .disable_event  = snb_uncore_msr_disable_event,
1181     .enable_event   = nhm_uncore_msr_enable_event,
1182     .read_counter   = uncore_msr_read_counter,
1183 };
1184 
1185 static struct intel_uncore_type nhm_uncore = {
1186     .name       = "",
1187     .num_counters   = 8,
1188     .num_boxes  = 1,
1189     .perf_ctr_bits  = 48,
1190     .fixed_ctr_bits = 48,
1191     .event_ctl  = NHM_UNC_PERFEVTSEL0,
1192     .perf_ctr   = NHM_UNC_UNCORE_PMC0,
1193     .fixed_ctr  = NHM_UNC_FIXED_CTR,
1194     .fixed_ctl  = NHM_UNC_FIXED_CTR_CTRL,
1195     .event_mask = NHM_UNC_RAW_EVENT_MASK,
1196     .event_descs    = nhm_uncore_events,
1197     .ops        = &nhm_uncore_msr_ops,
1198     .format_group   = &nhm_uncore_format_group,
1199 };
1200 
1201 static struct intel_uncore_type *nhm_msr_uncores[] = {
1202     &nhm_uncore,
1203     NULL,
1204 };
1205 
1206 void nhm_uncore_cpu_init(void)
1207 {
1208     uncore_msr_uncores = nhm_msr_uncores;
1209 }
1210 
1211 /* end of Nehalem uncore support */
1212 
1213 /* Tiger Lake MMIO uncore support */
1214 
1215 static const struct pci_device_id tgl_uncore_pci_ids[] = {
1216     IMC_UNCORE_DEV(TGL_U1),
1217     IMC_UNCORE_DEV(TGL_U2),
1218     IMC_UNCORE_DEV(TGL_U3),
1219     IMC_UNCORE_DEV(TGL_U4),
1220     IMC_UNCORE_DEV(TGL_H),
1221     IMC_UNCORE_DEV(ADL_1),
1222     IMC_UNCORE_DEV(ADL_2),
1223     IMC_UNCORE_DEV(ADL_3),
1224     IMC_UNCORE_DEV(ADL_4),
1225     IMC_UNCORE_DEV(ADL_5),
1226     IMC_UNCORE_DEV(ADL_6),
1227     IMC_UNCORE_DEV(ADL_7),
1228     IMC_UNCORE_DEV(ADL_8),
1229     IMC_UNCORE_DEV(ADL_9),
1230     IMC_UNCORE_DEV(ADL_10),
1231     IMC_UNCORE_DEV(ADL_11),
1232     IMC_UNCORE_DEV(ADL_12),
1233     IMC_UNCORE_DEV(ADL_13),
1234     IMC_UNCORE_DEV(ADL_14),
1235     IMC_UNCORE_DEV(ADL_15),
1236     IMC_UNCORE_DEV(ADL_16),
1237     IMC_UNCORE_DEV(ADL_17),
1238     IMC_UNCORE_DEV(ADL_18),
1239     IMC_UNCORE_DEV(ADL_19),
1240     IMC_UNCORE_DEV(ADL_20),
1241     IMC_UNCORE_DEV(ADL_21),
1242     IMC_UNCORE_DEV(RPL_1),
1243     IMC_UNCORE_DEV(RPL_2),
1244     IMC_UNCORE_DEV(RPL_3),
1245     IMC_UNCORE_DEV(RPL_4),
1246     IMC_UNCORE_DEV(RPL_5),
1247     IMC_UNCORE_DEV(RPL_6),
1248     IMC_UNCORE_DEV(RPL_7),
1249     IMC_UNCORE_DEV(RPL_8),
1250     IMC_UNCORE_DEV(RPL_9),
1251     IMC_UNCORE_DEV(RPL_10),
1252     IMC_UNCORE_DEV(RPL_11),
1253     IMC_UNCORE_DEV(RPL_12),
1254     IMC_UNCORE_DEV(RPL_13),
1255     IMC_UNCORE_DEV(RPL_14),
1256     IMC_UNCORE_DEV(RPL_15),
1257     IMC_UNCORE_DEV(RPL_16),
1258     IMC_UNCORE_DEV(RPL_17),
1259     IMC_UNCORE_DEV(RPL_18),
1260     IMC_UNCORE_DEV(RPL_19),
1261     IMC_UNCORE_DEV(RPL_20),
1262     IMC_UNCORE_DEV(RPL_21),
1263     IMC_UNCORE_DEV(RPL_22),
1264     IMC_UNCORE_DEV(RPL_23),
1265     IMC_UNCORE_DEV(RPL_24),
1266     IMC_UNCORE_DEV(RPL_25),
1267     { /* end: all zeroes */ }
1268 };
1269 
1270 enum perf_tgl_uncore_imc_freerunning_types {
1271     TGL_MMIO_UNCORE_IMC_DATA_TOTAL,
1272     TGL_MMIO_UNCORE_IMC_DATA_READ,
1273     TGL_MMIO_UNCORE_IMC_DATA_WRITE,
1274     TGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX
1275 };
1276 
1277 static struct freerunning_counters tgl_l_uncore_imc_freerunning[] = {
1278     [TGL_MMIO_UNCORE_IMC_DATA_TOTAL]    = { 0x5040, 0x0, 0x0, 1, 64 },
1279     [TGL_MMIO_UNCORE_IMC_DATA_READ]     = { 0x5058, 0x0, 0x0, 1, 64 },
1280     [TGL_MMIO_UNCORE_IMC_DATA_WRITE]    = { 0x50A0, 0x0, 0x0, 1, 64 },
1281 };
1282 
1283 static struct freerunning_counters tgl_uncore_imc_freerunning[] = {
1284     [TGL_MMIO_UNCORE_IMC_DATA_TOTAL]    = { 0xd840, 0x0, 0x0, 1, 64 },
1285     [TGL_MMIO_UNCORE_IMC_DATA_READ]     = { 0xd858, 0x0, 0x0, 1, 64 },
1286     [TGL_MMIO_UNCORE_IMC_DATA_WRITE]    = { 0xd8A0, 0x0, 0x0, 1, 64 },
1287 };
1288 
1289 static struct uncore_event_desc tgl_uncore_imc_events[] = {
1290     INTEL_UNCORE_EVENT_DESC(data_total,         "event=0xff,umask=0x10"),
1291     INTEL_UNCORE_EVENT_DESC(data_total.scale,   "6.103515625e-5"),
1292     INTEL_UNCORE_EVENT_DESC(data_total.unit,    "MiB"),
1293 
1294     INTEL_UNCORE_EVENT_DESC(data_read,         "event=0xff,umask=0x20"),
1295     INTEL_UNCORE_EVENT_DESC(data_read.scale,   "6.103515625e-5"),
1296     INTEL_UNCORE_EVENT_DESC(data_read.unit,    "MiB"),
1297 
1298     INTEL_UNCORE_EVENT_DESC(data_write,        "event=0xff,umask=0x30"),
1299     INTEL_UNCORE_EVENT_DESC(data_write.scale,  "6.103515625e-5"),
1300     INTEL_UNCORE_EVENT_DESC(data_write.unit,   "MiB"),
1301 
1302     { /* end: all zeroes */ }
1303 };
1304 
1305 static struct pci_dev *tgl_uncore_get_mc_dev(void)
1306 {
1307     const struct pci_device_id *ids = tgl_uncore_pci_ids;
1308     struct pci_dev *mc_dev = NULL;
1309 
1310     while (ids && ids->vendor) {
1311         mc_dev = pci_get_device(PCI_VENDOR_ID_INTEL, ids->device, NULL);
1312         if (mc_dev)
1313             return mc_dev;
1314         ids++;
1315     }
1316 
1317     return mc_dev;
1318 }
1319 
1320 #define TGL_UNCORE_MMIO_IMC_MEM_OFFSET      0x10000
1321 #define TGL_UNCORE_PCI_IMC_MAP_SIZE     0xe000
1322 
1323 static void __uncore_imc_init_box(struct intel_uncore_box *box,
1324                   unsigned int base_offset)
1325 {
1326     struct pci_dev *pdev = tgl_uncore_get_mc_dev();
1327     struct intel_uncore_pmu *pmu = box->pmu;
1328     struct intel_uncore_type *type = pmu->type;
1329     resource_size_t addr;
1330     u32 mch_bar;
1331 
1332     if (!pdev) {
1333         pr_warn("perf uncore: Cannot find matched IMC device.\n");
1334         return;
1335     }
1336 
1337     pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET, &mch_bar);
1338     /* MCHBAR is disabled */
1339     if (!(mch_bar & BIT(0))) {
1340         pr_warn("perf uncore: MCHBAR is disabled. Failed to map IMC free-running counters.\n");
1341         return;
1342     }
1343     mch_bar &= ~BIT(0);
1344     addr = (resource_size_t)(mch_bar + TGL_UNCORE_MMIO_IMC_MEM_OFFSET * pmu->pmu_idx);
1345 
1346 #ifdef CONFIG_PHYS_ADDR_T_64BIT
1347     pci_read_config_dword(pdev, SNB_UNCORE_PCI_IMC_BAR_OFFSET + 4, &mch_bar);
1348     addr |= ((resource_size_t)mch_bar << 32);
1349 #endif
1350 
1351     addr += base_offset;
1352     box->io_addr = ioremap(addr, type->mmio_map_size);
1353     if (!box->io_addr)
1354         pr_warn("perf uncore: Failed to ioremap for %s.\n", type->name);
1355 }
1356 
1357 static void tgl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)
1358 {
1359     __uncore_imc_init_box(box, 0);
1360 }
1361 
1362 static struct intel_uncore_ops tgl_uncore_imc_freerunning_ops = {
1363     .init_box   = tgl_uncore_imc_freerunning_init_box,
1364     .exit_box   = uncore_mmio_exit_box,
1365     .read_counter   = uncore_mmio_read_counter,
1366     .hw_config  = uncore_freerunning_hw_config,
1367 };
1368 
1369 static struct attribute *tgl_uncore_imc_formats_attr[] = {
1370     &format_attr_event.attr,
1371     &format_attr_umask.attr,
1372     NULL
1373 };
1374 
1375 static const struct attribute_group tgl_uncore_imc_format_group = {
1376     .name = "format",
1377     .attrs = tgl_uncore_imc_formats_attr,
1378 };
1379 
1380 static struct intel_uncore_type tgl_uncore_imc_free_running = {
1381     .name           = "imc_free_running",
1382     .num_counters       = 3,
1383     .num_boxes      = 2,
1384     .num_freerunning_types  = TGL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX,
1385     .mmio_map_size      = TGL_UNCORE_PCI_IMC_MAP_SIZE,
1386     .freerunning        = tgl_uncore_imc_freerunning,
1387     .ops            = &tgl_uncore_imc_freerunning_ops,
1388     .event_descs        = tgl_uncore_imc_events,
1389     .format_group       = &tgl_uncore_imc_format_group,
1390 };
1391 
1392 static struct intel_uncore_type *tgl_mmio_uncores[] = {
1393     &tgl_uncore_imc_free_running,
1394     NULL
1395 };
1396 
1397 void tgl_l_uncore_mmio_init(void)
1398 {
1399     tgl_uncore_imc_free_running.freerunning = tgl_l_uncore_imc_freerunning;
1400     uncore_mmio_uncores = tgl_mmio_uncores;
1401 }
1402 
1403 void tgl_uncore_mmio_init(void)
1404 {
1405     uncore_mmio_uncores = tgl_mmio_uncores;
1406 }
1407 
1408 /* end of Tiger Lake MMIO uncore support */
1409 
1410 /* Alder Lake MMIO uncore support */
1411 #define ADL_UNCORE_IMC_BASE         0xd900
1412 #define ADL_UNCORE_IMC_MAP_SIZE         0x200
1413 #define ADL_UNCORE_IMC_CTR          0xe8
1414 #define ADL_UNCORE_IMC_CTRL         0xd0
1415 #define ADL_UNCORE_IMC_GLOBAL_CTL       0xc0
1416 #define ADL_UNCORE_IMC_BOX_CTL          0xc4
1417 #define ADL_UNCORE_IMC_FREERUNNING_BASE     0xd800
1418 #define ADL_UNCORE_IMC_FREERUNNING_MAP_SIZE 0x100
1419 
1420 #define ADL_UNCORE_IMC_CTL_FRZ          (1 << 0)
1421 #define ADL_UNCORE_IMC_CTL_RST_CTRL     (1 << 1)
1422 #define ADL_UNCORE_IMC_CTL_RST_CTRS     (1 << 2)
1423 #define ADL_UNCORE_IMC_CTL_INT          (ADL_UNCORE_IMC_CTL_RST_CTRL | \
1424                         ADL_UNCORE_IMC_CTL_RST_CTRS)
1425 
1426 static void adl_uncore_imc_init_box(struct intel_uncore_box *box)
1427 {
1428     __uncore_imc_init_box(box, ADL_UNCORE_IMC_BASE);
1429 
1430     /* The global control in MC1 can control both MCs. */
1431     if (box->io_addr && (box->pmu->pmu_idx == 1))
1432         writel(ADL_UNCORE_IMC_CTL_INT, box->io_addr + ADL_UNCORE_IMC_GLOBAL_CTL);
1433 }
1434 
1435 static void adl_uncore_mmio_disable_box(struct intel_uncore_box *box)
1436 {
1437     if (!box->io_addr)
1438         return;
1439 
1440     writel(ADL_UNCORE_IMC_CTL_FRZ, box->io_addr + uncore_mmio_box_ctl(box));
1441 }
1442 
1443 static void adl_uncore_mmio_enable_box(struct intel_uncore_box *box)
1444 {
1445     if (!box->io_addr)
1446         return;
1447 
1448     writel(0, box->io_addr + uncore_mmio_box_ctl(box));
1449 }
1450 
1451 static struct intel_uncore_ops adl_uncore_mmio_ops = {
1452     .init_box   = adl_uncore_imc_init_box,
1453     .exit_box   = uncore_mmio_exit_box,
1454     .disable_box    = adl_uncore_mmio_disable_box,
1455     .enable_box = adl_uncore_mmio_enable_box,
1456     .disable_event  = intel_generic_uncore_mmio_disable_event,
1457     .enable_event   = intel_generic_uncore_mmio_enable_event,
1458     .read_counter   = uncore_mmio_read_counter,
1459 };
1460 
1461 #define ADL_UNC_CTL_CHMASK_MASK         0x00000f00
1462 #define ADL_UNC_IMC_EVENT_MASK          (SNB_UNC_CTL_EV_SEL_MASK | \
1463                          ADL_UNC_CTL_CHMASK_MASK | \
1464                          SNB_UNC_CTL_EDGE_DET)
1465 
1466 static struct attribute *adl_uncore_imc_formats_attr[] = {
1467     &format_attr_event.attr,
1468     &format_attr_chmask.attr,
1469     &format_attr_edge.attr,
1470     NULL,
1471 };
1472 
1473 static const struct attribute_group adl_uncore_imc_format_group = {
1474     .name       = "format",
1475     .attrs      = adl_uncore_imc_formats_attr,
1476 };
1477 
1478 static struct intel_uncore_type adl_uncore_imc = {
1479     .name       = "imc",
1480     .num_counters   = 5,
1481     .num_boxes  = 2,
1482     .perf_ctr_bits  = 64,
1483     .perf_ctr   = ADL_UNCORE_IMC_CTR,
1484     .event_ctl  = ADL_UNCORE_IMC_CTRL,
1485     .event_mask = ADL_UNC_IMC_EVENT_MASK,
1486     .box_ctl    = ADL_UNCORE_IMC_BOX_CTL,
1487     .mmio_offset    = 0,
1488     .mmio_map_size  = ADL_UNCORE_IMC_MAP_SIZE,
1489     .ops        = &adl_uncore_mmio_ops,
1490     .format_group   = &adl_uncore_imc_format_group,
1491 };
1492 
1493 enum perf_adl_uncore_imc_freerunning_types {
1494     ADL_MMIO_UNCORE_IMC_DATA_TOTAL,
1495     ADL_MMIO_UNCORE_IMC_DATA_READ,
1496     ADL_MMIO_UNCORE_IMC_DATA_WRITE,
1497     ADL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX
1498 };
1499 
1500 static struct freerunning_counters adl_uncore_imc_freerunning[] = {
1501     [ADL_MMIO_UNCORE_IMC_DATA_TOTAL]    = { 0x40, 0x0, 0x0, 1, 64 },
1502     [ADL_MMIO_UNCORE_IMC_DATA_READ]     = { 0x58, 0x0, 0x0, 1, 64 },
1503     [ADL_MMIO_UNCORE_IMC_DATA_WRITE]    = { 0xA0, 0x0, 0x0, 1, 64 },
1504 };
1505 
1506 static void adl_uncore_imc_freerunning_init_box(struct intel_uncore_box *box)
1507 {
1508     __uncore_imc_init_box(box, ADL_UNCORE_IMC_FREERUNNING_BASE);
1509 }
1510 
1511 static struct intel_uncore_ops adl_uncore_imc_freerunning_ops = {
1512     .init_box   = adl_uncore_imc_freerunning_init_box,
1513     .exit_box   = uncore_mmio_exit_box,
1514     .read_counter   = uncore_mmio_read_counter,
1515     .hw_config  = uncore_freerunning_hw_config,
1516 };
1517 
1518 static struct intel_uncore_type adl_uncore_imc_free_running = {
1519     .name           = "imc_free_running",
1520     .num_counters       = 3,
1521     .num_boxes      = 2,
1522     .num_freerunning_types  = ADL_MMIO_UNCORE_IMC_FREERUNNING_TYPE_MAX,
1523     .mmio_map_size      = ADL_UNCORE_IMC_FREERUNNING_MAP_SIZE,
1524     .freerunning        = adl_uncore_imc_freerunning,
1525     .ops            = &adl_uncore_imc_freerunning_ops,
1526     .event_descs        = tgl_uncore_imc_events,
1527     .format_group       = &tgl_uncore_imc_format_group,
1528 };
1529 
1530 static struct intel_uncore_type *adl_mmio_uncores[] = {
1531     &adl_uncore_imc,
1532     &adl_uncore_imc_free_running,
1533     NULL
1534 };
1535 
1536 void adl_uncore_mmio_init(void)
1537 {
1538     uncore_mmio_uncores = adl_mmio_uncores;
1539 }
1540 
1541 /* end of Alder Lake MMIO uncore support */
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!