0001
0002
0003
0004 #define UNCORE_DISCOVERY_TABLE_DEVICE 0x09a7
0005
0006 #define UNCORE_EXT_CAP_ID_DISCOVERY 0x23
0007
0008 #define UNCORE_DISCOVERY_DVSEC_OFFSET 0x8
0009
0010 #define UNCORE_DISCOVERY_DVSEC_ID_MASK 0xffff
0011
0012 #define UNCORE_DISCOVERY_DVSEC_ID_PMON 0x1
0013
0014 #define UNCORE_DISCOVERY_DVSEC2_OFFSET 0xc
0015
0016 #define UNCORE_DISCOVERY_DVSEC2_BIR_MASK 0x7
0017
0018 #define UNCORE_DISCOVERY_BIR_BASE 0x10
0019
0020 #define UNCORE_DISCOVERY_BIR_STEP 0x4
0021
0022 #define UNCORE_DISCOVERY_GLOBAL_MAP_SIZE 0x20
0023
0024 #define UNCORE_DISCOVERY_PCI_DOMAIN(data) ((data >> 28) & 0x7)
0025 #define UNCORE_DISCOVERY_PCI_BUS(data) ((data >> 20) & 0xff)
0026 #define UNCORE_DISCOVERY_PCI_DEVFN(data) ((data >> 12) & 0xff)
0027 #define UNCORE_DISCOVERY_PCI_BOX_CTRL(data) (data & 0xfff)
0028
0029
0030 #define uncore_discovery_invalid_unit(unit) \
0031 (!unit.table1 || !unit.ctl || \
0032 unit.table1 == -1ULL || unit.ctl == -1ULL || \
0033 unit.table3 == -1ULL)
0034
0035 #define GENERIC_PMON_CTL_EV_SEL_MASK 0x000000ff
0036 #define GENERIC_PMON_CTL_UMASK_MASK 0x0000ff00
0037 #define GENERIC_PMON_CTL_EDGE_DET (1 << 18)
0038 #define GENERIC_PMON_CTL_INVERT (1 << 23)
0039 #define GENERIC_PMON_CTL_TRESH_MASK 0xff000000
0040 #define GENERIC_PMON_RAW_EVENT_MASK (GENERIC_PMON_CTL_EV_SEL_MASK | \
0041 GENERIC_PMON_CTL_UMASK_MASK | \
0042 GENERIC_PMON_CTL_EDGE_DET | \
0043 GENERIC_PMON_CTL_INVERT | \
0044 GENERIC_PMON_CTL_TRESH_MASK)
0045
0046 #define GENERIC_PMON_BOX_CTL_FRZ (1 << 0)
0047 #define GENERIC_PMON_BOX_CTL_RST_CTRL (1 << 8)
0048 #define GENERIC_PMON_BOX_CTL_RST_CTRS (1 << 9)
0049 #define GENERIC_PMON_BOX_CTL_INT (GENERIC_PMON_BOX_CTL_RST_CTRL | \
0050 GENERIC_PMON_BOX_CTL_RST_CTRS)
0051
0052 enum uncore_access_type {
0053 UNCORE_ACCESS_MSR = 0,
0054 UNCORE_ACCESS_MMIO,
0055 UNCORE_ACCESS_PCI,
0056
0057 UNCORE_ACCESS_MAX,
0058 };
0059
0060 struct uncore_global_discovery {
0061 union {
0062 u64 table1;
0063 struct {
0064 u64 type : 8,
0065 stride : 8,
0066 max_units : 10,
0067 __reserved_1 : 36,
0068 access_type : 2;
0069 };
0070 };
0071
0072 u64 ctl;
0073
0074 union {
0075 u64 table3;
0076 struct {
0077 u64 status_offset : 8,
0078 num_status : 16,
0079 __reserved_2 : 40;
0080 };
0081 };
0082 };
0083
0084 struct uncore_unit_discovery {
0085 union {
0086 u64 table1;
0087 struct {
0088 u64 num_regs : 8,
0089 ctl_offset : 8,
0090 bit_width : 8,
0091 ctr_offset : 8,
0092 status_offset : 8,
0093 __reserved_1 : 22,
0094 access_type : 2;
0095 };
0096 };
0097
0098 u64 ctl;
0099
0100 union {
0101 u64 table3;
0102 struct {
0103 u64 box_type : 16,
0104 box_id : 16,
0105 __reserved_2 : 32;
0106 };
0107 };
0108 };
0109
0110 struct intel_uncore_discovery_type {
0111 struct rb_node node;
0112 enum uncore_access_type access_type;
0113 u64 box_ctrl;
0114 u64 *box_ctrl_die;
0115 u16 type;
0116 u8 num_counters;
0117 u8 counter_width;
0118 u8 ctl_offset;
0119 u8 ctr_offset;
0120 u16 num_boxes;
0121 unsigned int *ids;
0122 unsigned int *box_offset;
0123 };
0124
0125 bool intel_uncore_has_discovery_tables(void);
0126 void intel_uncore_clear_discovery_tables(void);
0127 void intel_uncore_generic_uncore_cpu_init(void);
0128 int intel_uncore_generic_uncore_pci_init(void);
0129 void intel_uncore_generic_uncore_mmio_init(void);
0130
0131 void intel_generic_uncore_msr_init_box(struct intel_uncore_box *box);
0132 void intel_generic_uncore_msr_disable_box(struct intel_uncore_box *box);
0133 void intel_generic_uncore_msr_enable_box(struct intel_uncore_box *box);
0134
0135 void intel_generic_uncore_mmio_init_box(struct intel_uncore_box *box);
0136 void intel_generic_uncore_mmio_disable_box(struct intel_uncore_box *box);
0137 void intel_generic_uncore_mmio_enable_box(struct intel_uncore_box *box);
0138 void intel_generic_uncore_mmio_disable_event(struct intel_uncore_box *box,
0139 struct perf_event *event);
0140 void intel_generic_uncore_mmio_enable_event(struct intel_uncore_box *box,
0141 struct perf_event *event);
0142
0143 void intel_generic_uncore_pci_init_box(struct intel_uncore_box *box);
0144 void intel_generic_uncore_pci_disable_box(struct intel_uncore_box *box);
0145 void intel_generic_uncore_pci_enable_box(struct intel_uncore_box *box);
0146 void intel_generic_uncore_pci_disable_event(struct intel_uncore_box *box,
0147 struct perf_event *event);
0148 u64 intel_generic_uncore_pci_read_counter(struct intel_uncore_box *box,
0149 struct perf_event *event);
0150
0151 struct intel_uncore_type **
0152 intel_uncore_generic_init_uncores(enum uncore_access_type type_id, int num_extra);